diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
7 files changed, 6114 insertions, 6100 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index e4317ec15..f7d0d7b39 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867052000 # Number of ticks simulated -final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783855 # Number of seconds simulated +sim_ticks 2783854535000 # Number of ticks simulated +final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 624684 # Simulator instruction rate (inst/s) -host_op_rate 760453 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12180447765 # Simulator tick rate (ticks/s) -host_mem_usage 563036 # Number of bytes of host memory used -host_seconds 228.55 # Real time elapsed on the host -sim_insts 142772879 # Number of instructions simulated -sim_ops 173803124 # Number of ops (including micro ops) simulated +host_inst_rate 1852974 # Simulator instruction rate (inst/s) +host_op_rate 2255698 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36130480826 # Simulator tick rate (ticks/s) +host_mem_usage 581484 # Number of bytes of host memory used +host_seconds 77.05 # Real time elapsed on the host +sim_insts 142771651 # Number of instructions simulated +sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory @@ -21,36 +21,36 @@ system.physmem.bytes_read::realview.ide 960 # Nu system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 433574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708827 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182056 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 433574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -99,29 +99,29 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 10029 # Table walker walks requested -system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 10028 # Table walker walks requested +system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526223 # DTB read hits -system.cpu.dtb.read_misses 8581 # DTB read misses -system.cpu.dtb.write_hits 23124452 # DTB write hits +system.cpu.dtb.read_hits 31525949 # DTB read hits +system.cpu.dtb.read_misses 8580 # DTB read misses +system.cpu.dtb.write_hits 23124104 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534804 # DTB read accesses -system.cpu.dtb.write_accesses 23125900 # DTB write accesses +system.cpu.dtb.read_accesses 31534529 # DTB read accesses +system.cpu.dtb.write_accesses 23125552 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650675 # DTB hits -system.cpu.dtb.misses 10029 # DTB misses -system.cpu.dtb.accesses 54660704 # DTB accesses +system.cpu.dtb.hits 54650053 # DTB hits +system.cpu.dtb.misses 10028 # DTB misses +system.cpu.dtb.accesses 54660081 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147039346 # ITB inst hits +system.cpu.itb.inst_hits 147038166 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -202,40 +202,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147044108 # ITB inst accesses -system.cpu.itb.hits 147039346 # DTB hits +system.cpu.itb.inst_accesses 147042928 # ITB inst accesses +system.cpu.itb.hits 147038166 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147044108 # DTB accesses -system.cpu.numCycles 5567737188 # number of cpu cycles simulated +system.cpu.itb.accesses 147042928 # DTB accesses +system.cpu.numCycles 5567712151 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu.committedInsts 142772879 # Number of instructions committed -system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses +system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed +system.cpu.committedInsts 142771651 # Number of instructions committed +system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873899 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls -system.cpu.num_int_insts 153162683 # number of integer instructions +system.cpu.num_func_calls 16873962 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls +system.cpu.num_int_insts 153161279 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read -system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written +system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written -system.cpu.num_mem_refs 55939276 # number of memory refs -system.cpu.num_load_insts 31855884 # Number of load instructions -system.cpu.num_store_insts 24083392 # Number of store instructions -system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles -system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles +system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written +system.cpu.num_mem_refs 55938616 # number of memory refs +system.cpu.num_load_insts 31855585 # Number of load instructions +system.cpu.num_store_insts 24083031 # Number of store instructions +system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles +system.cpu.num_busy_cycles 178081957.060993 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396981 # Number of branches fetched +system.cpu.Branches 36396978 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121152037 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -263,16 +263,16 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.dcache.tags.replacements 819402 # number of replacements +system.cpu.op_class::total 177218432 # Class of executed instruction +system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,58 +282,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits -system.cpu.dcache.overall_hits::total 52864242 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits +system.cpu.dcache.overall_hits::total 52863656 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses -system.cpu.dcache.overall_misses::total 814074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses +system.cpu.dcache.overall_misses::total 814065 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses @@ -348,16 +348,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682040 # number of writebacks -system.cpu.dcache.writebacks::total 682040 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks +system.cpu.dcache.writebacks::total 682017 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699214 # number of replacements -system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1698998 # number of replacements +system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -366,32 +366,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits -system.cpu.icache.overall_hits::total 145342721 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses -system.cpu.icache.overall_misses::total 1699732 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits +system.cpu.icache.overall_hits::total 145341757 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699516 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699516 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699516 # number of overall misses +system.cpu.icache.overall_misses::total 1699516 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147041273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147041273 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147041273 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,20 +400,20 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks -system.cpu.icache.writebacks::total 1699214 # number of writebacks +system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks +system.cpu.icache.writebacks::total 1698998 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.708883 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.628332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.704513 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.623437 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -430,33 +430,33 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits +system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151146 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681416 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151131 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151131 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681201 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505445 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681416 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656586 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2349224 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 1681201 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656576 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348995 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681416 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656586 # number of overall hits -system.cpu.l2cache.overall_hits::total 2349224 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681201 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656576 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348995 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses @@ -480,56 +480,56 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 2 system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses system.cpu.l2cache.overall_misses::total 181651 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699714 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699499 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530646 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530646 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000801 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494363 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010765 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010765 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199217 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071774 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199219 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071780 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010765 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199217 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071774 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199219 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071780 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,51 +538,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks -system.cpu.l2cache.writebacks::total 101949 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks +system.cpu.l2cache.writebacks::total 101950 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116074 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581970 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7753470 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306721 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182974 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313958557 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 182975 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5318737 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018478 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134674 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -634,14 +634,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -686,8 +686,8 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 7977 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -701,17 +701,17 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092412 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255385 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586905 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 434821 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index c3e49583c..df10533fc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.802895 # Number of seconds simulated -sim_ticks 2802894699500 # Number of ticks simulated -final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.802883 # Number of seconds simulated +sim_ticks 2802882879000 # Number of ticks simulated +final_tick 2802882879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 526774 # Simulator instruction rate (inst/s) -host_op_rate 641866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10055912327 # Simulator tick rate (ticks/s) -host_mem_usage 575028 # Number of bytes of host memory used -host_seconds 278.73 # Real time elapsed on the host -sim_insts 146828240 # Number of instructions simulated -sim_ops 178908039 # Number of ops (including micro ops) simulated +host_inst_rate 1272297 # Simulator instruction rate (inst/s) +host_op_rate 1550275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24287502010 # Simulator tick rate (ticks/s) +host_mem_usage 596572 # Number of bytes of host memory used +host_seconds 115.40 # Real time elapsed on the host +sim_insts 146828562 # Number of instructions simulated +sim_ops 178908371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1108644 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9410404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1082576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1109732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9413156 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 152660 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1082192 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11757100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1108644 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1262520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8452288 # Number of bytes written to this memory +system.physmem.bytes_read::total 11759340 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1109732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 152660 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1262392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8477312 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8469852 # Number of bytes written to this memory +system.physmem.bytes_written::total 8494876 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25776 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147557 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2540 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16929 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192852 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132067 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192887 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132458 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136458 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136849 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 395535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3357388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 395925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3358384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386100 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4194628 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 395535 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 450434 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3015557 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4195445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 395925 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54465 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 450391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3024497 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3021823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3015557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3030764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3024497 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 395535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3363640 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 395925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3364636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386114 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7216451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7226208 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -118,29 +118,29 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7967 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 7964 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339720 # DTB read hits -system.cpu0.dtb.read_misses 6874 # DTB read misses -system.cpu0.dtb.write_hits 16391078 # DTB write hits +system.cpu0.dtb.read_hits 20339777 # DTB read hits +system.cpu0.dtb.read_misses 6871 # DTB read misses +system.cpu0.dtb.write_hits 16391027 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -151,12 +151,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346594 # DTB read accesses -system.cpu0.dtb.write_accesses 16392171 # DTB write accesses +system.cpu0.dtb.read_accesses 20346648 # DTB read accesses +system.cpu0.dtb.write_accesses 16392120 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36730798 # DTB hits -system.cpu0.dtb.misses 7967 # DTB misses -system.cpu0.dtb.accesses 36738765 # DTB accesses +system.cpu0.dtb.hits 36730804 # DTB hits +system.cpu0.dtb.misses 7964 # DTB misses +system.cpu0.dtb.accesses 36738768 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -204,7 +204,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 97439331 # ITB inst hits +system.cpu0.itb.inst_hits 97439598 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -221,40 +221,40 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses -system.cpu0.itb.hits 97439331 # DTB hits +system.cpu0.itb.inst_accesses 97442956 # ITB inst accesses +system.cpu0.itb.hits 97439598 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97442689 # DTB accesses -system.cpu0.numCycles 5605791368 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442956 # DTB accesses +system.cpu0.numCycles 5605767724 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed -system.cpu0.committedInsts 95426926 # Number of instructions committed -system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed +system.cpu0.committedInsts 95427136 # Number of instructions committed +system.cpu0.committedOps 115560651 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762921 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000180 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100762696 # number of integer instructions +system.cpu0.num_func_calls 8000357 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204240 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762921 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182457857 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135716 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written -system.cpu0.num_mem_refs 37873810 # number of memory refs -system.cpu0.num_load_insts 20597310 # Number of load instructions -system.cpu0.num_store_insts 17276500 # Number of store instructions -system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles -system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles +system.cpu0.num_cc_register_reads 349972220 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907498 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873797 # number of memory refs +system.cpu0.num_load_insts 20597358 # Number of load instructions +system.cpu0.num_store_insts 17276439 # Number of store instructions +system.cpu0.num_idle_cycles 5488182951.223861 # Number of idle cycles +system.cpu0.num_busy_cycles 117584772.776139 # Number of busy cycles system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941499 # Number of branches fetched +system.cpu0.Branches 21941714 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction -system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887557 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction @@ -282,18 +282,18 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597358 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276439 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116882065 # Class of executed instruction -system.cpu0.dcache.tags.replacements 693486 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks. +system.cpu0.op_class::total 116882349 # Class of executed instruction +system.cpu0.dcache.tags.replacements 693475 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853481 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932424 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.776797 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853481 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -301,60 +301,60 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690389 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690389 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363050 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363050 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798930 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798930 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145023 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145023 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295796 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295796 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18435 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18435 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses -system.cpu0.dcache.overall_misses::total 769220 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses +system.cpu0.dcache.tags.tag_accesses 74113882 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113882 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108626 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108626 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690357 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690357 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798983 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798983 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145063 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145063 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373096 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373096 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295789 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295789 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668885 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668885 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769207 # number of overall misses +system.cpu0.dcache.overall_misses::total 769207 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481722 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481722 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986146 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986146 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35467868 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467868 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914270 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914270 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048324 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048324 # miss rate for StoreCondReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses @@ -367,16 +367,16 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 693486 # number of writebacks -system.cpu0.dcache.writebacks::total 693486 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 693475 # number of writebacks +system.cpu0.dcache.writebacks::total 693475 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1109735 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1109624 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 96331795 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110136 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.774769 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -384,32 +384,32 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits -system.cpu0.icache.overall_hits::total 96331417 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses -system.cpu0.icache.overall_misses::total 1110256 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 195994025 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195994025 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331795 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331795 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331795 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331795 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331795 # number of overall hits +system.cpu0.icache.overall_hits::total 96331795 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110145 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1110145 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1110145 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1110145 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1110145 # number of overall misses +system.cpu0.icache.overall_misses::total 1110145 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441940 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441940 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441940 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441940 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441940 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441940 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,8 +418,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1109735 # number of writebacks -system.cpu0.icache.writebacks::total 1109735 # number of writebacks +system.cpu0.icache.writebacks::writebacks 1109624 # number of writebacks +system.cpu0.icache.writebacks::total 1109624 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -427,128 +427,128 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 249527 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16129.991654 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2731505 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 265646 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.282500 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 249486 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16123.886747 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2730668 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 265599 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.281168 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 16127.358870 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.556147 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076637 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.984336 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000156 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984497 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16112 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 16122.057477 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.758477 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070793 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.984012 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000107 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984124 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16108 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5452 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7536 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2638 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983398 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 59699237 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 59699237 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10182 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4496 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14678 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 510201 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 510201 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1265145 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1265145 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94344 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94344 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068613 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1068613 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352244 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 352244 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10182 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4496 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1068613 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446588 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1529879 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10182 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4496 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1068613 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446588 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1529879 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 130 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 344 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26273 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26273 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18435 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18435 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175179 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175179 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41643 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 41643 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127922 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 127922 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 130 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 41643 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303101 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 345088 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 130 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 41643 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303101 # number of overall misses -system.cpu0.l2cache.overall_misses::total 345088 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10396 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4626 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 15022 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510201 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 510201 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265145 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1265145 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18435 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18435 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10396 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4626 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1874967 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10396 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4626 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1874967 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028102 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.022900 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5529 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7406 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2667 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983154 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 59695806 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59695806 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10175 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4509 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14684 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 510631 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 510631 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1264603 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1264603 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94360 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94360 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068362 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1068362 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352230 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 352230 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10175 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4509 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1068362 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446590 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1529636 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10175 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4509 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1068362 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446590 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1529636 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 118 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 334 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26269 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26269 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175160 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175160 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41783 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 41783 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127928 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 127928 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 118 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 41783 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303088 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 345205 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 118 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 41783 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303088 # number of overall misses +system.cpu0.l2cache.overall_misses::total 345205 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10391 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 15018 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510631 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 510631 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1264603 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1264603 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26269 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26269 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269520 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269520 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110145 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1110145 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480158 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 480158 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10391 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110145 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1874841 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10391 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110145 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1874841 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025502 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.022240 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649959 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649959 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037508 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037508 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266412 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266412 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028102 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037508 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404302 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.184050 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028102 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037508 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404302 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.184050 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649896 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649896 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037637 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037637 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266429 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266429 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025502 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037637 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404291 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.184125 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025502 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037637 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404291 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.184125 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -557,50 +557,50 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192911 # number of writebacks -system.cpu0.l2cache.writebacks::total 192911 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 193020 # number of writebacks +system.cpu0.l2cache.writebacks::total 193020 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3720245 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860324 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 218142 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2894 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution +system.cpu0.toL2Bus.snoop_filter.tot_requests 3720001 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860202 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 218277 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215192 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3085 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651713 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 510201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1265145 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26273 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18435 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395284 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::WritebackDirty 510631 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1292468 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26269 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 269520 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269520 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110145 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480158 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347958 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402091 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5764166 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140768632 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92116612 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5791673 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142101304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552324 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 232968516 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 623122 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4318148 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.066969 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.252635 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 234736876 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 623160 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4317939 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.067042 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.252935 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4031861 93.37% 93.37% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 283393 6.56% 99.93% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 2894 0.07% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031542 93.37% 93.37% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 283312 6.56% 99.93% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3085 0.07% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4318148 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4317939 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -630,29 +630,29 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3358 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 3359 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173916 # DTB read hits -system.cpu1.dtb.read_misses 2852 # DTB read misses -system.cpu1.dtb.write_hits 7587209 # DTB write hits +system.cpu1.dtb.read_hits 12173929 # DTB read hits +system.cpu1.dtb.read_misses 2853 # DTB read misses +system.cpu1.dtb.write_hits 7587213 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -663,12 +663,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176768 # DTB read accesses -system.cpu1.dtb.write_accesses 7587715 # DTB write accesses +system.cpu1.dtb.read_accesses 12176782 # DTB read accesses +system.cpu1.dtb.write_accesses 7587719 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761125 # DTB hits -system.cpu1.dtb.misses 3358 # DTB misses -system.cpu1.dtb.accesses 19764483 # DTB accesses +system.cpu1.dtb.hits 19761142 # DTB hits +system.cpu1.dtb.misses 3359 # DTB misses +system.cpu1.dtb.accesses 19764501 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -716,7 +716,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 53671575 # ITB inst hits +system.cpu1.itb.inst_hits 53671686 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -733,40 +733,40 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses -system.cpu1.itb.hits 53671575 # DTB hits +system.cpu1.itb.inst_accesses 53673420 # ITB inst accesses +system.cpu1.itb.hits 53671686 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673309 # DTB accesses -system.cpu1.numCycles 5605320274 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673420 # DTB accesses +system.cpu1.numCycles 5605296633 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed -system.cpu1.committedInsts 51401314 # Number of instructions committed -system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses +system.cpu1.committedInsts 51401426 # Number of instructions committed +system.cpu1.committedOps 63347720 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984340 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170855 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984241 # number of integer instructions +system.cpu1.num_func_calls 9170857 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967107 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984340 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674879 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298438 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026381 # number of memory refs -system.cpu1.num_load_insts 12289537 # Number of load instructions -system.cpu1.num_store_insts 7736844 # Number of store instructions -system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles -system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles +system.cpu1.num_cc_register_reads 196268976 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894428 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026400 # number of memory refs +system.cpu1.num_load_insts 12289552 # Number of load instructions +system.cpu1.num_store_insts 7736848 # Number of store instructions +system.cpu1.num_idle_cycles 5539683011.597479 # Number of idle cycles +system.cpu1.num_busy_cycles 65613621.402521 # Number of busy cycles system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217493 # Number of branches fetched +system.cpu1.Branches 15217504 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction -system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401392 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction @@ -794,80 +794,80 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289552 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736848 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459464 # Class of executed instruction -system.cpu1.dcache.tags.replacements 191938 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. +system.cpu1.op_class::total 65459571 # Class of executed instruction +system.cpu1.dcache.tags.replacements 191946 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503521 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.422366 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397500 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397500 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits +system.cpu1.dcache.tags.tag_accesses 39752021 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39752021 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858700 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858700 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397505 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397505 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256194 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256194 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306293 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306293 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92462 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92462 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72417 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72417 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256205 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256205 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306305 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306305 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 136638 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 136638 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92461 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92461 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259811 # number of overall misses -system.cpu1.dcache.overall_misses::total 259811 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22562 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22562 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229099 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229099 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses +system.cpu1.dcache.overall_misses::total 259817 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995338 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995338 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489966 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489966 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 19485304 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485304 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566122 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566122 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237347 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237347 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237547 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237547 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -878,42 +878,42 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 191938 # number of writebacks -system.cpu1.dcache.writebacks::total 191938 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks +system.cpu1.dcache.writebacks::total 191946 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 523373 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 523401 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53148863 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.445971 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits -system.cpu1.icache.overall_hits::total 53148780 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses -system.cpu1.icache.overall_misses::total 523885 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses +system.cpu1.icache.tags.tag_accesses 107869465 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869465 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148863 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148863 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148863 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148863 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148863 # number of overall hits +system.cpu1.icache.overall_hits::total 53148863 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523913 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523913 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523913 # number of overall misses +system.cpu1.icache.overall_misses::total 523913 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672776 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672776 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672776 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672776 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672776 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672776 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses @@ -928,8 +928,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 523373 # number of writebacks -system.cpu1.icache.writebacks::total 523373 # number of writebacks +system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks +system.cpu1.icache.writebacks::total 523401 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -937,127 +937,127 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 47555 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15235.297156 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1184961 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62593 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 18.931206 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 47378 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15226.816500 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1184475 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62425 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 18.974369 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 15230.950549 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.335617 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010990 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.929623 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 15223.544149 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 1.255151 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.017200 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.929171 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000077 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.929889 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15019 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::total 0.929371 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15027 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 530 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9526 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4963 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.916687 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24500378 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24500378 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1913 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 5534 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 121109 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 121109 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 583044 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 583044 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19763 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19763 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510346 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 510346 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99093 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99093 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1913 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510346 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 118856 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634736 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1913 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510346 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 118856 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634736 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 607 # number of ReadReq misses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9441 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5060 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.917175 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 24501973 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24501973 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3627 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1923 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5550 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 121108 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 121108 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 583081 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 583081 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19862 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19862 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510444 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 510444 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99124 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 99124 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3627 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1923 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510444 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 118986 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634980 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3627 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1923 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510444 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 118986 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634980 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 268 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 606 # number of ReadReq misses system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43853 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43853 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13539 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13539 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73574 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 73574 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13539 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117427 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13539 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117427 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3957 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2184 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121109 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 121109 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 583044 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 583044 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22562 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22562 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43753 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43753 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13469 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 13469 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73550 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73550 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 268 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13469 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117303 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131378 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 268 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13469 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117303 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131378 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121108 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 121108 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 583081 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 583081 # number of WritebackClean accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3957 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2184 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 766309 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3957 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2184 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 766309 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124084 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.098844 # miss rate for ReadReq accesses +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22562 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22562 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523913 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 523913 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172674 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 172674 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3965 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 523913 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 236289 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 766358 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3965 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 523913 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 236289 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 766358 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.122319 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.098441 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689339 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689339 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025843 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025843 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.426103 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.426103 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124084 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025843 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496976 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171697 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124084 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025843 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496976 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171697 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.687778 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.687778 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025708 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025708 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425947 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425947 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.122319 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025708 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496439 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171432 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.122319 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025708 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496439 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171432 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1066,50 +1066,50 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32818 # number of writebacks -system.cpu1.l2cache.writebacks::total 32818 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32706 # number of writebacks +system.cpu1.l2cache.writebacks::total 32706 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1533421 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773256 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533509 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773310 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 165978 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_snoops 166217 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164146 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2071 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 121109 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 583044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 121108 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 594239 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776509 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22562 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51408 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523913 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172674 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571581 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778800 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2357775 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66454020 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27282414 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2369077 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67028804 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27426222 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 93773822 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 347349 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1819817 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.108136 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.313960 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94492418 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 347790 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1820349 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.108308 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.314409 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1624967 89.29% 89.29% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 192913 10.60% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1937 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1625261 89.28% 89.28% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 193017 10.60% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2071 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1819817 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1820349 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1161,14 +1161,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1209,175 +1209,175 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 107037 # number of replacements -system.l2c.tags.tagsinuse 62176.956554 # Cycle average of tags in use -system.l2c.tags.total_refs 241620 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167464 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.442818 # Average number of references to valid blocks. +system.l2c.tags.replacements 107729 # number of replacements +system.l2c.tags.tagsinuse 62410.633039 # Cycle average of tags in use +system.l2c.tags.total_refs 243914 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168410 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.448334 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 47954.224141 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010653 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030815 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7778.474758 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4056.241083 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1664.556464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 718.418639 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.731723 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 48132.772899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010469 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030814 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7764.318269 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4071.663088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1666.007629 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 770.829870 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.734448 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.118690 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.061893 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010962 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.948745 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.118474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.062129 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025421 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011762 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.952311 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60421 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60675 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1839 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45269 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1869 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13225 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45497 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.921951 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5183068 # Number of tag accesses -system.l2c.tags.data_accesses 5183068 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 225729 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 225729 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 511 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 575 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13894 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3132 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17026 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 74 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 24882 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76059 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11145 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11759 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 124050 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 24882 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89953 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11145 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14891 # number of demand (read+write) hits -system.l2c.demand_hits::total 141076 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits -system.l2c.overall_hits::cpu0.inst 24882 # number of overall hits -system.l2c.overall_hits::cpu0.data 89953 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11145 # number of overall hits -system.l2c.overall_hits::cpu1.data 14891 # number of overall hits -system.l2c.overall_hits::total 141076 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 10043 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13338 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1932 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136525 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15837 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152362 # number of ReadExReq misses +system.l2c.tags.occ_task_id_percent::1024 0.925827 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5179303 # Number of tag accesses +system.l2c.tags.data_accesses 5179303 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 225726 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 225726 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 564 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 115 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 679 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 81 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 38 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 119 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13900 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3040 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16940 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 77 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 58 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 25005 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76077 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 34 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11094 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11733 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 124113 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 77 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 58 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 25005 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 89977 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11094 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14773 # number of demand (read+write) hits +system.l2c.demand_hits::total 141053 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 77 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 58 # number of overall hits +system.l2c.overall_hits::cpu0.inst 25005 # number of overall hits +system.l2c.overall_hits::cpu0.data 89977 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11094 # number of overall hits +system.l2c.overall_hits::cpu1.data 14773 # number of overall hits +system.l2c.overall_hits::total 141053 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9970 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3255 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13225 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 737 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1148 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1885 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136548 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15822 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152370 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 16761 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 11173 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1126 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 31464 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 16778 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 11188 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2375 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1125 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 31476 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16761 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 147698 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16963 # number of demand (read+write) misses -system.l2c.demand_misses::total 183826 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16778 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 147736 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2375 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16947 # number of demand (read+write) misses +system.l2c.demand_misses::total 183846 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16761 # number of overall misses -system.l2c.overall_misses::cpu0.data 147698 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses -system.l2c.overall_misses::cpu1.data 16963 # number of overall misses -system.l2c.overall_misses::total 183826 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 225729 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 225729 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10554 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3359 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13913 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1185 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 16778 # number of overall misses +system.l2c.overall_misses::cpu0.data 147736 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2375 # number of overall misses +system.l2c.overall_misses::cpu1.data 16947 # number of overall misses +system.l2c.overall_misses::total 183846 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 225726 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 225726 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10534 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3370 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13904 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 818 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150419 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18969 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169388 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 82 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 41643 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 87232 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 13539 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12885 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 155514 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 82 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 41643 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 237651 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13539 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31854 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 324902 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 82 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 41643 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 237651 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13539 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31854 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 324902 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951582 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980947 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.958672 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920635 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994093 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.964072 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.907631 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.834889 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899485 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402493 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128084 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176823 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087388 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.202323 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.402493 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.621491 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.176823 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.532523 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.565789 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.402493 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.621491 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.176823 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.532523 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.565789 # miss rate for overall accesses +system.l2c.ReadExReq_accesses::cpu0.data 150448 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18862 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169310 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 85 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 60 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 41783 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 87265 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 34 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 13469 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12858 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 155589 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 85 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 60 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 41783 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 237713 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 34 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13469 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31720 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 324899 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 85 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 60 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 41783 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 237713 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 34 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13469 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31720 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 324899 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946459 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.965875 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.951165 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.900978 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.967960 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.940619 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.907609 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.838829 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899947 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.033333 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.401551 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128207 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176331 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087494 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.202302 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.033333 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.401551 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.621489 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.176331 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.534269 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.565856 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.033333 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.401551 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.621489 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.176331 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.534269 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.565856 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1386,51 +1386,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95877 # number of writebacks -system.l2c.writebacks::total 95877 # number of writebacks +system.l2c.writebacks::writebacks 96268 # number of writebacks +system.l2c.writebacks::total 96268 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 43996 # Transaction distribution -system.membus.trans_dist::ReadResp 75712 # Transaction distribution +system.membus.trans_dist::ReadResp 75724 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::WritebackDirty 132067 # Transaction distribution -system.membus.trans_dist::CleanEvict 8465 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60519 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15741 # Transaction distribution -system.membus.trans_dist::ReadExReq 196031 # Transaction distribution -system.membus.trans_dist::ReadExResp 151891 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution +system.membus.trans_dist::WritebackDirty 132458 # Transaction distribution +system.membus.trans_dist::CleanEvict 8718 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60357 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40887 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15566 # Transaction distribution +system.membus.trans_dist::ReadExReq 152312 # Transaction distribution +system.membus.trans_dist::ReadExResp 151914 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31728 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782029 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 891184 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 738406 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 847800 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17927560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18117342 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17954824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18144606 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20449630 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20476894 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 581009 # Request fanout histogram +system.membus.snoop_fanout::samples 537526 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 581009 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 537526 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 581009 # Request fanout histogram +system.membus.snoop_fanout::total 537526 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1472,41 +1472,41 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 863003 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 444472 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 128485 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 9552 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 9071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 481 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 862694 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 444199 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 128774 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9862 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 9376 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 486 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 301629 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 301670 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 225729 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 38612 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60623 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40978 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101601 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213528 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213528 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 257629 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1143706 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 415843 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1559549 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34428348 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10418866 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 44847214 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 180208 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1117804 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.282168 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.451010 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 225726 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 64248 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60580 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41006 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213448 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213448 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 257670 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1161849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423225 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1585074 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34444668 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10399858 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44844526 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 180900 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1118187 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.282688 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.451270 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 802876 71.83% 71.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 314447 28.13% 99.96% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 481 0.04% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 802575 71.77% 71.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 315126 28.18% 99.96% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 486 0.04% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1117804 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1118187 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 4c4524faa..ef75cc834 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867052000 # Number of ticks simulated -final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783855 # Number of seconds simulated +sim_ticks 2783854535000 # Number of ticks simulated +final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 540254 # Simulator instruction rate (inst/s) -host_op_rate 657673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10534181577 # Simulator tick rate (ticks/s) -host_mem_usage 560556 # Number of bytes of host memory used -host_seconds 264.27 # Real time elapsed on the host -sim_insts 142772879 # Number of instructions simulated -sim_ops 173803124 # Number of ops (including micro ops) simulated +host_inst_rate 1173204 # Simulator instruction rate (inst/s) +host_op_rate 1428188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22875895912 # Simulator tick rate (ticks/s) +host_mem_usage 581200 # Number of bytes of host memory used +host_seconds 121.69 # Real time elapsed on the host +sim_insts 142771651 # Number of instructions simulated +sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory @@ -21,36 +21,36 @@ system.physmem.bytes_read::realview.ide 960 # Nu system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 433574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708827 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182056 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 433574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -99,29 +99,29 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 10029 # Table walker walks requested -system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 10028 # Table walker walks requested +system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526223 # DTB read hits -system.cpu.dtb.read_misses 8581 # DTB read misses -system.cpu.dtb.write_hits 23124452 # DTB write hits +system.cpu.dtb.read_hits 31525949 # DTB read hits +system.cpu.dtb.read_misses 8580 # DTB read misses +system.cpu.dtb.write_hits 23124104 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534804 # DTB read accesses -system.cpu.dtb.write_accesses 23125900 # DTB write accesses +system.cpu.dtb.read_accesses 31534529 # DTB read accesses +system.cpu.dtb.write_accesses 23125552 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650675 # DTB hits -system.cpu.dtb.misses 10029 # DTB misses -system.cpu.dtb.accesses 54660704 # DTB accesses +system.cpu.dtb.hits 54650053 # DTB hits +system.cpu.dtb.misses 10028 # DTB misses +system.cpu.dtb.accesses 54660081 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147039346 # ITB inst hits +system.cpu.itb.inst_hits 147038166 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -202,40 +202,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147044108 # ITB inst accesses -system.cpu.itb.hits 147039346 # DTB hits +system.cpu.itb.inst_accesses 147042928 # ITB inst accesses +system.cpu.itb.hits 147038166 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147044108 # DTB accesses -system.cpu.numCycles 5567737188 # number of cpu cycles simulated +system.cpu.itb.accesses 147042928 # DTB accesses +system.cpu.numCycles 5567712151 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu.committedInsts 142772879 # Number of instructions committed -system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses +system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed +system.cpu.committedInsts 142771651 # Number of instructions committed +system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873899 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls -system.cpu.num_int_insts 153162683 # number of integer instructions +system.cpu.num_func_calls 16873962 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls +system.cpu.num_int_insts 153161279 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read -system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written +system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written -system.cpu.num_mem_refs 55939276 # number of memory refs -system.cpu.num_load_insts 31855884 # Number of load instructions -system.cpu.num_store_insts 24083392 # Number of store instructions -system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles -system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles +system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written +system.cpu.num_mem_refs 55938616 # number of memory refs +system.cpu.num_load_insts 31855585 # Number of load instructions +system.cpu.num_store_insts 24083031 # Number of store instructions +system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles +system.cpu.num_busy_cycles 178081957.060993 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396981 # Number of branches fetched +system.cpu.Branches 36396978 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121152037 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -263,16 +263,16 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.dcache.tags.replacements 819402 # number of replacements +system.cpu.op_class::total 177218432 # Class of executed instruction +system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,58 +282,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits -system.cpu.dcache.overall_hits::total 52864242 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits +system.cpu.dcache.overall_hits::total 52863656 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses -system.cpu.dcache.overall_misses::total 814074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses +system.cpu.dcache.overall_misses::total 814065 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses @@ -348,16 +348,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682040 # number of writebacks -system.cpu.dcache.writebacks::total 682040 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks +system.cpu.dcache.writebacks::total 682017 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699214 # number of replacements -system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1698998 # number of replacements +system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -366,32 +366,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits -system.cpu.icache.overall_hits::total 145342721 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses -system.cpu.icache.overall_misses::total 1699732 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits +system.cpu.icache.overall_hits::total 145341757 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699516 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699516 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699516 # number of overall misses +system.cpu.icache.overall_misses::total 1699516 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147041273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147041273 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147041273 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,20 +400,20 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks -system.cpu.icache.writebacks::total 1699214 # number of writebacks +system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks +system.cpu.icache.writebacks::total 1698998 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.708883 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.628332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.704513 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.623437 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -430,33 +430,33 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits +system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151146 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681416 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151131 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151131 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681201 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505445 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681416 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656586 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2349224 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 1681201 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656576 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348995 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681416 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656586 # number of overall hits -system.cpu.l2cache.overall_hits::total 2349224 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681201 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656576 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348995 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses @@ -480,56 +480,56 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 2 system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses system.cpu.l2cache.overall_misses::total 181651 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699714 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699499 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530646 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530646 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000801 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494363 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010765 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010765 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199217 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071774 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199219 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071780 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010765 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199217 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071774 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199219 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071780 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,51 +538,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks -system.cpu.l2cache.writebacks::total 101949 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks +system.cpu.l2cache.writebacks::total 101950 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116074 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581970 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7753470 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306721 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182974 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313958557 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 182975 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5318737 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018478 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134674 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -634,14 +634,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -686,8 +686,8 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 7977 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -701,17 +701,17 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092412 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255385 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586905 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 434821 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 35b76497a..13b640b18 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,160 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.871850 # Number of seconds simulated -sim_ticks 2871850306000 # Number of ticks simulated -final_tick 2871850306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.871782 # Number of seconds simulated +sim_ticks 2871782342000 # Number of ticks simulated +final_tick 2871782342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 312956 # Simulator instruction rate (inst/s) -host_op_rate 378531 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6832247646 # Simulator tick rate (ticks/s) -host_mem_usage 599868 # Number of bytes of host memory used -host_seconds 420.34 # Real time elapsed on the host -sim_insts 131546959 # Number of instructions simulated -sim_ops 159110973 # Number of ops (including micro ops) simulated +host_inst_rate 937604 # Simulator instruction rate (inst/s) +host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20478123685 # Simulator tick rate (ticks/s) +host_mem_usage 614632 # Number of bytes of host memory used +host_seconds 140.24 # Real time elapsed on the host +sim_insts 131486349 # Number of instructions simulated +sim_ops 159039994 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1178404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1267556 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8608576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1156004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1264932 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602496 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 129300 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 549908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 341632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 151508 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 548500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 349120 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12076912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1178404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 129300 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1307704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8530240 # Number of bytes written to this memory +system.physmem.bytes_read::total 12074032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1156004 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151508 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1307512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8524352 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8547804 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8541916 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26866 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134509 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26516 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20284 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134414 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2175 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2522 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8591 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5455 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197850 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 133285 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197805 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 133193 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 137676 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 137584 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 111 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 410329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 441373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2997571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 402539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 440469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2995525 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 191482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 118959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 190996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 121569 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4205272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 410329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45023 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 455352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2970294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4204369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 402539 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52757 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2968314 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2976410 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2970294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2974430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2968314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 111 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 410329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 447475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2997571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 402539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 446571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2995525 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 191496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 118959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 191010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 121569 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7181682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197850 # Number of read requests accepted -system.physmem.writeReqs 137676 # Number of write requests accepted -system.physmem.readBursts 197850 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 137676 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12652352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue -system.physmem.bytesWritten 8560960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12076912 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8547804 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7178799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197805 # Number of read requests accepted +system.physmem.writeReqs 137584 # Number of write requests accepted +system.physmem.readBursts 197805 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 137584 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12650304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue +system.physmem.bytesWritten 8554240 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12074032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8541916 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 64578 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11583 # Per bank write bursts -system.physmem.perBankRdBursts::1 11800 # Per bank write bursts -system.physmem.perBankRdBursts::2 11971 # Per bank write bursts -system.physmem.perBankRdBursts::3 11847 # Per bank write bursts -system.physmem.perBankRdBursts::4 20098 # Per bank write bursts -system.physmem.perBankRdBursts::5 11961 # Per bank write bursts -system.physmem.perBankRdBursts::6 12460 # Per bank write bursts -system.physmem.perBankRdBursts::7 12487 # Per bank write bursts -system.physmem.perBankRdBursts::8 11821 # Per bank write bursts -system.physmem.perBankRdBursts::9 12495 # Per bank write bursts -system.physmem.perBankRdBursts::10 11828 # Per bank write bursts -system.physmem.perBankRdBursts::11 11338 # Per bank write bursts -system.physmem.perBankRdBursts::12 11476 # Per bank write bursts -system.physmem.perBankRdBursts::13 11922 # Per bank write bursts -system.physmem.perBankRdBursts::14 11270 # Per bank write bursts -system.physmem.perBankRdBursts::15 11336 # Per bank write bursts -system.physmem.perBankWrBursts::0 8288 # Per bank write bursts -system.physmem.perBankWrBursts::1 8566 # Per bank write bursts -system.physmem.perBankWrBursts::2 8821 # Per bank write bursts -system.physmem.perBankWrBursts::3 8522 # Per bank write bursts -system.physmem.perBankWrBursts::4 7854 # Per bank write bursts -system.physmem.perBankWrBursts::5 8398 # Per bank write bursts -system.physmem.perBankWrBursts::6 8910 # Per bank write bursts -system.physmem.perBankWrBursts::7 8793 # Per bank write bursts -system.physmem.perBankWrBursts::8 8333 # Per bank write bursts -system.physmem.perBankWrBursts::9 8912 # Per bank write bursts -system.physmem.perBankWrBursts::10 8495 # Per bank write bursts -system.physmem.perBankWrBursts::11 8357 # Per bank write bursts -system.physmem.perBankWrBursts::12 8083 # Per bank write bursts -system.physmem.perBankWrBursts::13 7998 # Per bank write bursts -system.physmem.perBankWrBursts::14 7822 # Per bank write bursts -system.physmem.perBankWrBursts::15 7613 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11699 # Per bank write bursts +system.physmem.perBankRdBursts::1 11843 # Per bank write bursts +system.physmem.perBankRdBursts::2 11790 # Per bank write bursts +system.physmem.perBankRdBursts::3 11735 # Per bank write bursts +system.physmem.perBankRdBursts::4 20524 # Per bank write bursts +system.physmem.perBankRdBursts::5 11797 # Per bank write bursts +system.physmem.perBankRdBursts::6 12442 # Per bank write bursts +system.physmem.perBankRdBursts::7 12572 # Per bank write bursts +system.physmem.perBankRdBursts::8 12187 # Per bank write bursts +system.physmem.perBankRdBursts::9 12631 # Per bank write bursts +system.physmem.perBankRdBursts::10 11774 # Per bank write bursts +system.physmem.perBankRdBursts::11 11306 # Per bank write bursts +system.physmem.perBankRdBursts::12 11587 # Per bank write bursts +system.physmem.perBankRdBursts::13 11723 # Per bank write bursts +system.physmem.perBankRdBursts::14 11020 # Per bank write bursts +system.physmem.perBankRdBursts::15 11031 # Per bank write bursts +system.physmem.perBankWrBursts::0 8350 # Per bank write bursts +system.physmem.perBankWrBursts::1 8610 # Per bank write bursts +system.physmem.perBankWrBursts::2 8670 # Per bank write bursts +system.physmem.perBankWrBursts::3 8312 # Per bank write bursts +system.physmem.perBankWrBursts::4 8160 # Per bank write bursts +system.physmem.perBankWrBursts::5 8304 # Per bank write bursts +system.physmem.perBankWrBursts::6 8940 # Per bank write bursts +system.physmem.perBankWrBursts::7 8786 # Per bank write bursts +system.physmem.perBankWrBursts::8 8636 # Per bank write bursts +system.physmem.perBankWrBursts::9 9040 # Per bank write bursts +system.physmem.perBankWrBursts::10 8341 # Per bank write bursts +system.physmem.perBankWrBursts::11 8261 # Per bank write bursts +system.physmem.perBankWrBursts::12 8330 # Per bank write bursts +system.physmem.perBankWrBursts::13 7860 # Per bank write bursts +system.physmem.perBankWrBursts::14 7712 # Per bank write bursts +system.physmem.perBankWrBursts::15 7348 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 27 # Number of times write queue was full causing retry -system.physmem.totGap 2871849883000 # Total gap between requests +system.physmem.totGap 2871781902000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188090 # Read request sizes (log2) +system.physmem.readPktSize::6 188045 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 133285 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 133193 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,161 +184,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87676 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.950454 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.764211 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.933653 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46396 52.92% 52.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17641 20.12% 73.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5908 6.74% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3515 4.01% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2504 2.86% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1565 1.78% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 855 0.98% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 945 1.08% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8347 9.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87676 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6535 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.251262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 585.438505 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6533 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87582 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.110023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.595388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.444001 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46635 53.25% 53.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17297 19.75% 73.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6011 6.86% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3421 3.91% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2493 2.85% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1531 1.75% 88.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 857 0.98% 89.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 971 1.11% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8366 9.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87582 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6415 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.812159 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.882305 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6413 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6535 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.469013 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.883832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.598321 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5330 81.56% 81.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 483 7.39% 88.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 73 1.12% 90.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 153 2.34% 92.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 33 0.50% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 123 1.88% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 36 0.55% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 26 0.40% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 25 0.38% 96.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.23% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.09% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 152 2.33% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.40% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.11% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6535 # Writes before turning the bus around for reads -system.physmem.totQLat 4503336233 # Total ticks spent queuing -system.physmem.totMemAccLat 8210079983 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 988465000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22779.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6415 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.835542 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.951972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.109397 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5337 83.20% 83.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 463 7.22% 90.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 65 1.01% 91.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 41 0.64% 92.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 43 0.67% 92.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.23% 92.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 61 0.95% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 94.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 120 1.87% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 12 0.19% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 12 0.19% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 75 1.17% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.14% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.39% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 75 1.17% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.17% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.08% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6415 # Writes before turning the bus around for reads +system.physmem.totQLat 4510532456 # Total ticks spent queuing +system.physmem.totMemAccLat 8216676206 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 988305000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22819.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41529.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41569.54 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.21 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.35 # Average write queue length when enqueuing -system.physmem.readRowHits 165103 # Number of row buffer hits during reads -system.physmem.writeRowHits 78678 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.88 # Average write queue length when enqueuing +system.physmem.readRowHits 165067 # Number of row buffer hits during reads +system.physmem.writeRowHits 78671 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.81 # Row buffer hit rate for writes -system.physmem.avgGap 8559246.92 # Average gap between requests -system.physmem.pageHitRate 73.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341250840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186198375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 812814600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 441624960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85820448015 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647828636000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1923006208950 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.605484 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2741162536487 # Time in different power states -system.physmem_0.memoryStateTime::REF 95897360000 # Time in different power states +system.physmem.writeRowHitRate 58.85 # Row buffer hit rate for writes +system.physmem.avgGap 8562540.52 # Average gap between requests +system.physmem.pageHitRate 73.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341273520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186210750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 814335600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 441495360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86023351485 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647608604750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1922985930585 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.614762 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740794855198 # Time in different power states +system.physmem_0.memoryStateTime::REF 95895020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34789668513 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35089613552 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 321579720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 175465125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 729183000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 425172240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84866434740 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648665489750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1922758560735 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.519251 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742561244982 # Time in different power states -system.physmem_1.memoryStateTime::REF 95897360000 # Time in different power states +system.physmem_1.actEnergy 320846400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 175065000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 727412400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 424621440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84787415640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648692759000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1922698779000 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.514771 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742610583350 # Time in different power states +system.physmem_1.memoryStateTime::REF 95895020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33391555518 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33276576650 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -394,56 +396,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 8830 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 8830 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1617 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7213 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 8830 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 8830 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 8830 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7312 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12253.145514 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11429.774492 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6252.045789 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7284 99.62% 99.62% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 24 0.33% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7312 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 8793 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 8793 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1631 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7162 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 8793 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 8793 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 8793 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7275 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12044.604811 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11100.960867 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5725.376750 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6764 92.98% 92.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 475 6.53% 99.51% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 28 0.38% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7275 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5742 78.53% 78.53% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1570 21.47% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7312 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8830 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5691 78.23% 78.23% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1584 21.77% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7275 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8793 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8830 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7312 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8793 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7275 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7312 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 16142 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7275 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 16068 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25809403 # DTB read hits -system.cpu0.dtb.read_misses 7606 # DTB read misses -system.cpu0.dtb.write_hits 19327142 # DTB write hits -system.cpu0.dtb.write_misses 1224 # DTB write misses +system.cpu0.dtb.read_hits 25747110 # DTB read hits +system.cpu0.dtb.read_misses 7587 # DTB read misses +system.cpu0.dtb.write_hits 19248161 # DTB write hits +system.cpu0.dtb.write_misses 1206 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3761 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3752 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1861 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1822 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25817009 # DTB read accesses -system.cpu0.dtb.write_accesses 19328366 # DTB write accesses +system.cpu0.dtb.read_accesses 25754697 # DTB read accesses +system.cpu0.dtb.write_accesses 19249367 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 45136545 # DTB hits -system.cpu0.dtb.misses 8830 # DTB misses -system.cpu0.dtb.accesses 45145375 # DTB accesses +system.cpu0.dtb.hits 44995271 # DTB hits +system.cpu0.dtb.misses 8793 # DTB misses +system.cpu0.dtb.accesses 45004064 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -481,15 +486,13 @@ system.cpu0.itb.walker.walkWaitTime::samples 3674 system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12688.276398 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11839.861434 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6240.244766 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2261 87.77% 87.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 282 10.95% 98.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 30 1.16% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12540.566770 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11604.890292 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7309.377161 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 2541 98.64% 98.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 33 1.28% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution @@ -504,7 +507,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 121850168 # ITB inst hits +system.cpu0.itb.inst_hits 121581439 # ITB inst hits system.cpu0.itb.inst_misses 3674 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -521,172 +524,172 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 121853842 # ITB inst accesses -system.cpu0.itb.hits 121850168 # DTB hits +system.cpu0.itb.inst_accesses 121585113 # ITB inst accesses +system.cpu0.itb.hits 121581439 # DTB hits system.cpu0.itb.misses 3674 # DTB misses -system.cpu0.itb.accesses 121853842 # DTB accesses -system.cpu0.numCycles 5743700612 # number of cpu cycles simulated +system.cpu0.itb.accesses 121585113 # DTB accesses +system.cpu0.numCycles 5743564684 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed -system.cpu0.committedInsts 118029542 # Number of instructions committed -system.cpu0.committedOps 142673635 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 126253590 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1899 # number of quiesce instructions executed +system.cpu0.committedInsts 117764996 # Number of instructions committed +system.cpu0.committedOps 142323546 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 125936873 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses -system.cpu0.num_func_calls 12792333 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16043976 # number of instructions that are conditional controls -system.cpu0.num_int_insts 126253590 # number of integer instructions +system.cpu0.num_func_calls 12772448 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 16008688 # number of instructions that are conditional controls +system.cpu0.num_int_insts 125936873 # number of integer instructions system.cpu0.num_fp_insts 11483 # number of float instructions -system.cpu0.num_int_register_reads 232324144 # number of times the integer registers were read -system.cpu0.num_int_register_writes 87654298 # number of times the integer registers were written +system.cpu0.num_int_register_reads 231719006 # number of times the integer registers were read +system.cpu0.num_int_register_writes 87450436 # number of times the integer registers were written system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 516734560 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 53610723 # number of times the CC registers were written -system.cpu0.num_mem_refs 46299073 # number of memory refs -system.cpu0.num_load_insts 26069844 # Number of load instructions -system.cpu0.num_store_insts 20229229 # Number of store instructions -system.cpu0.num_idle_cycles 5455076908.366100 # Number of idle cycles -system.cpu0.num_busy_cycles 288623703.633900 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050250 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949750 # Percentage of idle cycles -system.cpu0.Branches 29603215 # Number of branches fetched +system.cpu0.num_cc_register_reads 515468589 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 53496392 # number of times the CC registers were written +system.cpu0.num_mem_refs 46152180 # number of memory refs +system.cpu0.num_load_insts 26006060 # Number of load instructions +system.cpu0.num_store_insts 20146120 # Number of store instructions +system.cpu0.num_idle_cycles 5455990176.452100 # Number of idle cycles +system.cpu0.num_busy_cycles 287574507.547900 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050069 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949931 # Percentage of idle cycles +system.cpu0.Branches 29546529 # Number of branches fetched system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 100054313 68.31% 68.31% # Class of executed instruction -system.cpu0.op_class::IntMult 112340 0.08% 68.39% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8369 0.01% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::MemRead 26069844 17.80% 86.19% # Class of executed instruction -system.cpu0.op_class::MemWrite 20229229 13.81% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 99842345 68.33% 68.33% # Class of executed instruction +system.cpu0.op_class::IntMult 112141 0.08% 68.41% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8311 0.01% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::MemRead 26006060 17.80% 86.21% # Class of executed instruction +system.cpu0.op_class::MemWrite 20146120 13.79% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146476410 # Class of executed instruction -system.cpu0.dcache.tags.replacements 740882 # number of replacements -system.cpu0.dcache.tags.tagsinuse 488.760528 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 44216040 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 741394 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 59.639058 # Average number of references to valid blocks. +system.cpu0.op_class::total 146117292 # Class of executed instruction +system.cpu0.dcache.tags.replacements 732778 # number of replacements +system.cpu0.dcache.tags.tagsinuse 487.345221 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 44083181 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 733290 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 60.116981 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.760528 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954610 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.954610 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.345221 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951846 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.951846 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 90957934 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 90957934 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 24496228 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 24496228 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18570022 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18570022 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 327271 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 327271 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374846 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374846 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 372508 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 372508 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 43066250 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 43066250 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 43393521 # number of overall hits -system.cpu0.dcache.overall_hits::total 43393521 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 423502 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 423502 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 340254 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 340254 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133712 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 133712 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22535 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22535 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19849 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19849 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 763756 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 763756 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 897468 # number of overall misses -system.cpu0.dcache.overall_misses::total 897468 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5717292500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5717292500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6989183500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6989183500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 344979500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 344979500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 511150000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 511150000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1456500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1456500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 12706476000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 12706476000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 12706476000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 12706476000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24919730 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24919730 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18910276 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18910276 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 460983 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 460983 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397381 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 397381 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 392357 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 392357 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 43830006 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 43830006 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 44290989 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 44290989 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016995 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016995 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017993 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017993 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290058 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290058 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056709 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056709 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050589 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050589 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017425 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.017425 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020263 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.020263 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13500.036600 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13500.036600 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20541.076666 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20541.076666 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15308.608831 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15308.608831 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25751.927049 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25751.927049 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 90667478 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90667478 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 24441740 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 24441740 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18494582 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18494582 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326232 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 326232 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374079 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 374079 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371656 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 371656 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 42936322 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 42936322 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 43262554 # number of overall hits +system.cpu0.dcache.overall_hits::total 43262554 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 418013 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 418013 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 337667 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 337667 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133440 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 133440 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22337 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22337 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19808 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19808 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 755680 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 755680 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 889120 # number of overall misses +system.cpu0.dcache.overall_misses::total 889120 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5665137000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5665137000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6926542000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6926542000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 343483500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 343483500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 502731000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 502731000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1840500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1840500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 12591679000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 12591679000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 12591679000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 12591679000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24859753 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24859753 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18832249 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18832249 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459672 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 459672 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 396416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391464 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 391464 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 43692002 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 43692002 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 44151674 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 44151674 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016815 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016815 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017930 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017930 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290294 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290294 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056347 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056347 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050600 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050600 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017296 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.017296 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020138 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.020138 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13552.537840 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13552.537840 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20512.937302 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20512.937302 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15377.333572 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15377.333572 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25380.199919 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25380.199919 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16636.826421 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16636.826421 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14158.138229 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14158.138229 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16662.713053 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16662.713053 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14161.956766 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14161.956766 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -695,147 +698,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 740882 # number of writebacks -system.cpu0.dcache.writebacks::total 740882 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25304 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25304 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15852 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15852 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25304 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25304 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25304 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25304 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 398198 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 398198 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 340254 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 340254 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106613 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 106613 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6683 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6683 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19849 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19849 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 738452 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 738452 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 845065 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 845065 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31860 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60413 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4887280000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4887280000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6648929500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6648929500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1745313500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1745313500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102495000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102495000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 491343000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 491343000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1414500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1414500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11536209500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11536209500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13281523000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13281523000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6641550500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6641550500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5414724500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5414724500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12056275000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12056275000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015979 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015979 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017993 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017993 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231273 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231273 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016818 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016818 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050589 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050589 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016848 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016848 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019080 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019080 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12273.492082 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12273.492082 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19541.076666 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19541.076666 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16370.550496 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16370.550496 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15336.675146 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15336.675146 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24754.043025 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24754.043025 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 732778 # number of writebacks +system.cpu0.dcache.writebacks::total 732778 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25286 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25286 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15664 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15664 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25288 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25288 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25288 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25288 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 392727 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 392727 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337665 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 337665 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106338 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 106338 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6673 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6673 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19808 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19808 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 730392 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 730392 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 836730 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 836730 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31820 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60319 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4843447000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4843447000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6588824500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6588824500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1737105000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737105000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102846500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102846500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 482970000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 482970000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1793500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432271500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11432271500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13169376500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13169376500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629050000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629050000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400878000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400878000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029928000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029928000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015798 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015798 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017930 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017930 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231335 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231335 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016833 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016833 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050600 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050600 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016717 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016717 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018951 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018951 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12332.859722 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12332.859722 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19512.903321 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19512.903321 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16335.693731 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16335.693731 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15412.333283 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15412.333283 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24382.572698 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24382.572698 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15622.152151 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15622.152151 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15716.569731 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15716.569731 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208460.467671 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208460.467671 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189637.673800 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189637.673800 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199564.249417 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199564.249417 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15652.240851 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15652.240851 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15739.099232 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15739.099232 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208329.666876 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208329.666876 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189511.140742 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189511.140742 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199438.452229 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199438.452229 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1154605 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.321447 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 120695042 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1155117 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 104.487287 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1147265 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.321425 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 120433653 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1147777 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 104.927746 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321447 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321425 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 244855462 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 244855462 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 120695042 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 120695042 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 120695042 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 120695042 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 120695042 # number of overall hits -system.cpu0.icache.overall_hits::total 120695042 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1155126 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1155126 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1155126 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1155126 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1155126 # number of overall misses -system.cpu0.icache.overall_misses::total 1155126 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12352499000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12352499000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12352499000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12352499000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12352499000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12352499000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 121850168 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 121850168 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 121850168 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 121850168 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 121850168 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 121850168 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009480 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009480 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009480 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10693.637750 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10693.637750 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10693.637750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10693.637750 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 244310664 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 244310664 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 120433653 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 120433653 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 120433653 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 120433653 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 120433653 # number of overall hits +system.cpu0.icache.overall_hits::total 120433653 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1147786 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1147786 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1147786 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1147786 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1147786 # number of overall misses +system.cpu0.icache.overall_misses::total 1147786 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12247651500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12247651500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12247651500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12247651500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12247651500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12247651500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 121581439 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 121581439 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 121581439 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 121581439 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 121581439 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 121581439 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009440 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009440 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009440 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009440 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009440 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009440 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10670.675108 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10670.675108 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10670.675108 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10670.675108 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10670.675108 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10670.675108 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -844,330 +849,331 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1154605 # number of writebacks -system.cpu0.icache.writebacks::total 1154605 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1155126 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1155126 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1155126 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1155126 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1155126 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1155126 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1147265 # number of writebacks +system.cpu0.icache.writebacks::total 1147265 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147786 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1147786 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147786 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1147786 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147786 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1147786 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11774936000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11774936000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11774936000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11774936000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11774936000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11774936000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11673758500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11673758500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11673758500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11673758500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11673758500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11673758500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009480 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009480 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009480 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10193.637750 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10193.637750 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10193.637750 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009440 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009440 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009440 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10170.675108 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10170.675108 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10170.675108 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1946486 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1946511 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935691 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1935756 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 57 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 246425 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 273842 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16083.519419 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3089138 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 289977 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.653045 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 245684 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 272679 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16060.422672 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3064880 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 288783 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.613090 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14593.575431 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.644607 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.130850 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1489.168531 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.890721 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000039 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 14559.127845 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.514376 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.125186 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1500.655266 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.888619 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090892 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981660 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1031 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.091593 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.980250 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1021 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 282 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 325 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15080 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 262 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 312 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 434 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3285 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7655 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3857 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062927 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3313 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7651 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3839 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062317 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 63340451 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 63340451 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 11537 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4979 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 16516 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 507696 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 507696 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1358751 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1358751 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 241135 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 241135 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1108628 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1108628 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 416937 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 416937 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 11537 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4979 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1108628 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 658072 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1783216 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 11537 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4979 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1108628 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 658072 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1783216 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 155 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 97 # number of ReadReq misses +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 62824015 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 62824015 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10929 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4820 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 15749 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 500939 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 500939 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1350193 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1350193 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 238805 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 238805 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1101574 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1101574 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 411559 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 411559 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10929 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4820 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1101574 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 650364 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1767687 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10929 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4820 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1101574 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 650364 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1767687 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 174 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 78 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 252 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55316 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55316 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19844 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19844 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43803 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 43803 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46498 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 46498 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94557 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 94557 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 155 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 97 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 46498 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 138360 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 185110 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 155 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 97 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 46498 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 138360 # number of overall misses -system.cpu0.l2cache.overall_misses::total 185110 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4266000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2540500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 6806500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 172322000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 172322000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 43306000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 43306000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1349997 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1349997 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2802544000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2802544000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3338173500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3338173500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3246573500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3246573500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4266000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2540500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3338173500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6049117500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 9394097500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4266000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2540500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3338173500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6049117500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 9394097500 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11692 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5076 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 16768 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507696 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 507696 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1358751 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1358751 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55316 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55316 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19844 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19844 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 284938 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 284938 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1155126 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1155126 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 511494 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 511494 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11692 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5076 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1155126 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 796432 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1968326 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11692 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5076 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1155126 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 796432 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1968326 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.019110 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55084 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 55084 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19799 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19799 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 9 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43776 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 43776 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46212 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 46212 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94179 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 94179 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 174 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 78 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 46212 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 137955 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 184419 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 174 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 78 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 46212 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 137955 # number of overall misses +system.cpu0.l2cache.overall_misses::total 184419 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4564500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2175000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 6739500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 163061000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 163061000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 40358000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 40358000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1721497 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1721497 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2789761000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2789761000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3290416000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3290416000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3238432000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3238432000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4564500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2175000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3290416000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 6028193000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 9325348500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4564500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2175000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3290416000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 6028193000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 9325348500 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11103 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4898 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 16001 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 500939 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 500939 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1350193 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1350193 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55084 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55084 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19799 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19799 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 9 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 282581 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 282581 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1147786 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1147786 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 505738 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 505738 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11103 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4898 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1147786 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 788319 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1952106 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11103 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4898 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1147786 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 788319 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1952106 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.015671 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015925 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.015749 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.153728 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.153728 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040254 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040254 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.184864 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.184864 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.019110 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040254 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.173725 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.094044 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.019110 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040254 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.173725 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.094044 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26190.721649 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27009.920635 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3115.228867 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3115.228867 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2182.322112 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2182.322112 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 269999.400000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 269999.400000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63980.640595 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63980.640595 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71791.765237 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71791.765237 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34334.565394 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34334.565394 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26190.721649 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71791.765237 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43720.132264 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 50748.730485 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26190.721649 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71791.765237 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43720.132264 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 50748.730485 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154915 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154915 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040262 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040262 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186221 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186221 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.015671 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015925 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040262 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.174999 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.094472 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.015671 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015925 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040262 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.174999 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.094472 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26232.758621 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27884.615385 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26744.047619 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2960.224385 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2960.224385 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2038.385777 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2038.385777 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 191277.444444 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 191277.444444 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63728.093019 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63728.093019 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71202.631351 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71202.631351 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34385.924675 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34385.924675 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26232.758621 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27884.615385 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71202.631351 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43696.806930 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 50566.094058 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26232.758621 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27884.615385 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71202.631351 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43696.806930 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 50566.094058 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 232272 # number of writebacks -system.cpu0.l2cache.writebacks::total 232272 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1851 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1851 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 57 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 57 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1908 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1908 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1908 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1908 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 155 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 97 # number of ReadReq MSHR misses +system.cpu0.l2cache.writebacks::writebacks 231522 # number of writebacks +system.cpu0.l2cache.writebacks::total 231522 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1822 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1822 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 60 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1882 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1882 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1882 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1882 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 174 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 78 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264558 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 264558 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55316 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55316 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19844 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19844 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41952 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 41952 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46498 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46498 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94500 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94500 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 155 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 97 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46498 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136452 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 183202 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 155 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 97 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46498 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136452 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264558 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 447760 # number of overall MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264994 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 264994 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55084 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55084 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19799 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19799 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 9 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41954 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41954 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46212 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46212 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94119 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94119 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 174 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 78 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46212 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136073 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 182537 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 174 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 78 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46212 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136073 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264994 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 447531 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40882 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40842 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69435 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1958500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5294500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20402670222 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20402670222 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1434169000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1434169000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 342730000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 342730000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097997 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097997 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2366849000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2366849000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3059185500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3059185500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2673492000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2673492000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1958500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3059185500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5040341000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 8104821000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1958500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3059185500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5040341000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20402670222 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 28507491222 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69341 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3520500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1707000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5227500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20400229755 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20400229755 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1407285500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1407285500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 334701500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 334701500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1439497 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1439497 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2354527500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2354527500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3013144000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3013144000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2666489000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2666489000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3520500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1707000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3013144000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5021016500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 8039388000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3520500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1707000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3013144000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5021016500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20400229755 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 28439617755 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6386259500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7572471000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5200454500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5200454500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374077000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560288500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187014000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187014000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11586714000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12772925500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015029 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561091000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747302500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015749 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1176,117 +1182,117 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147232 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147232 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040254 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184753 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184753 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093075 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148467 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148467 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040262 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186102 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186102 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172612 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093508 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172612 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227483 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21009.920635 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77119.838455 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25926.838528 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25926.838528 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17271.215481 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17271.215481 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 219599.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 219599.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56418.025362 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56418.025362 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65791.765237 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28290.920635 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28290.920635 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44239.806334 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63666.900174 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229255 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20744.047619 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76983.742104 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25547.990342 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25547.990342 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16904.969948 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16904.969948 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 159944.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 159944.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56121.645135 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56121.645135 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65202.631351 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28331.038366 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28331.038366 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36899.432657 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44042.511929 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36899.432657 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63547.816252 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200447.567483 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185227.508439 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182133.383532 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182133.383532 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200316.687618 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185110.633661 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.877434 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.877434 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191791.733567 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183955.145100 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191665.826688 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183834.996611 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3935499 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1983981 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 29039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 320941 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317478 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3463 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 63971 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1779248 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28553 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28553 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 740475 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1358751 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 190136 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 311790 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 85728 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41989 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112642 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 304006 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 300714 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1155126 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 580591 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3461069 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2699694 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12104 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27735 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6200602 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146461624 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 102248167 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46768 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 248776863 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 987005 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2997932 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.122336 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.331180 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 3905249 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969182 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28911 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 320342 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316677 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3665 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 63843 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1765873 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 732965 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1379104 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 189043 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 312150 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85708 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41941 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112560 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 301555 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 298207 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147786 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575214 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3299 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460881 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2681738 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11926 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27058 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6181603 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146919352 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101652834 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44412 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 248636190 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 986669 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2981108 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.123159 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.332339 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2634639 87.88% 87.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 359830 12.00% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3463 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2617624 87.81% 87.81% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 359819 12.07% 99.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3665 0.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2997932 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3917122496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2981108 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3885976496 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115533329 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115188451 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1741711000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1730701000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1278424980 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1266054481 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 16050485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 15961487 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1317,57 +1323,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 2352 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2352 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 487 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1865 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2352 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2352 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2352 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1706 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11672.919109 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11010.748339 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5645.878722 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1558 91.32% 91.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 139 8.15% 99.47% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.18% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 2346 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2346 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 473 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1873 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2346 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2346 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2346 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1700 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11761.764706 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11073.675458 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5957.546231 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1554 91.41% 91.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.94% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 5 0.29% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1706 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1700 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1219 71.45% 71.45% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 487 28.55% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1706 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2352 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1227 72.18% 72.18% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 473 27.82% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1700 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2346 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2352 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1706 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2346 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1700 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1706 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 4058 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1700 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 4046 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3283088 # DTB read hits -system.cpu1.dtb.read_misses 1969 # DTB read misses -system.cpu1.dtb.write_hits 2849660 # DTB write hits -system.cpu1.dtb.write_misses 383 # DTB write misses +system.cpu1.dtb.read_hits 3334779 # DTB read hits +system.cpu1.dtb.read_misses 1954 # DTB read misses +system.cpu1.dtb.write_hits 2915242 # DTB write hits +system.cpu1.dtb.write_misses 392 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1653 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 218 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3285057 # DTB read accesses -system.cpu1.dtb.write_accesses 2850043 # DTB write accesses +system.cpu1.dtb.read_accesses 3336733 # DTB read accesses +system.cpu1.dtb.write_accesses 2915634 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6132748 # DTB hits -system.cpu1.dtb.misses 2352 # DTB misses -system.cpu1.dtb.accesses 6135100 # DTB accesses +system.cpu1.dtb.hits 6250021 # DTB hits +system.cpu1.dtb.misses 2346 # DTB misses +system.cpu1.dtb.accesses 6252367 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1405,21 +1411,20 @@ system.cpu1.itb.walker.walkWaitTime::samples 1376 system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11896.825397 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11258.920739 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5216.232861 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 112 13.68% 13.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 592 72.28% 85.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 66 8.06% 94.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 94.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11288.127256 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5150.797327 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 577 70.45% 84.62% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 76 9.28% 93.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 94.87% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 24 2.93% 98.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 5 0.61% 98.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.73% 99.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 98.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.24% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution @@ -1434,7 +1439,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 13713445 # ITB inst hits +system.cpu1.itb.inst_hits 13920333 # ITB inst hits system.cpu1.itb.inst_misses 1376 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1451,171 +1456,171 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 13714821 # ITB inst accesses -system.cpu1.itb.hits 13713445 # DTB hits +system.cpu1.itb.inst_accesses 13921709 # ITB inst accesses +system.cpu1.itb.hits 13920333 # DTB hits system.cpu1.itb.misses 1376 # DTB misses -system.cpu1.itb.accesses 13714821 # DTB accesses -system.cpu1.numCycles 5742759797 # number of cpu cycles simulated +system.cpu1.itb.accesses 13921709 # DTB accesses +system.cpu1.numCycles 5742623362 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2753 # number of quiesce instructions executed -system.cpu1.committedInsts 13517417 # Number of instructions committed -system.cpu1.committedOps 16437338 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14911378 # Number of integer alu accesses +system.cpu1.kern.inst.quiesce 2722 # number of quiesce instructions executed +system.cpu1.committedInsts 13721353 # Number of instructions committed +system.cpu1.committedOps 16716448 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 15155011 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 901174 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1468136 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14911378 # number of integer instructions +system.cpu1.num_func_calls 915079 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1497955 # number of instructions that are conditional controls +system.cpu1.num_int_insts 15155011 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 27063131 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10536793 # number of times the integer registers were written +system.cpu1.num_int_register_reads 27537464 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10698089 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 60344215 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 5099594 # number of times the CC registers were written -system.cpu1.num_mem_refs 6349896 # number of memory refs -system.cpu1.num_load_insts 3389045 # Number of load instructions -system.cpu1.num_store_insts 2960851 # Number of store instructions -system.cpu1.num_idle_cycles 5696813538.222876 # Number of idle cycles -system.cpu1.num_busy_cycles 45946258.777124 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008001 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991999 # Percentage of idle cycles -system.cpu1.Branches 2418797 # Number of branches fetched +system.cpu1.num_cc_register_reads 61338598 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 5194112 # number of times the CC registers were written +system.cpu1.num_mem_refs 6464162 # number of memory refs +system.cpu1.num_load_insts 3439477 # Number of load instructions +system.cpu1.num_store_insts 3024685 # Number of store instructions +system.cpu1.num_idle_cycles 5696031009.438875 # Number of idle cycles +system.cpu1.num_busy_cycles 46592352.561125 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008113 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991887 # Percentage of idle cycles +system.cpu1.Branches 2464329 # Number of branches fetched system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 10377527 61.94% 61.94% # Class of executed instruction -system.cpu1.op_class::IntMult 24492 0.15% 62.08% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3134 0.02% 62.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.10% # Class of executed instruction -system.cpu1.op_class::MemRead 3389045 20.23% 82.33% # Class of executed instruction -system.cpu1.op_class::MemWrite 2960851 17.67% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 10543721 61.89% 61.89% # Class of executed instruction +system.cpu1.op_class::IntMult 24250 0.14% 62.04% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction +system.cpu1.op_class::MemRead 3439477 20.19% 82.24% # Class of executed instruction +system.cpu1.op_class::MemWrite 3024685 17.76% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 16755073 # Class of executed instruction -system.cpu1.dcache.tags.replacements 144073 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.219627 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5912733 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 144418 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.941801 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106295131000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.219627 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924257 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.924257 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id +system.cpu1.op_class::total 17035345 # Class of executed instruction +system.cpu1.dcache.tags.replacements 148314 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.091453 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6019898 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 148666 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.492769 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106291978000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.091453 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916194 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.916194 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.673828 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12441829 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12441829 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3018165 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3018165 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2685196 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2685196 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41245 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 41245 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69563 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 69563 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61182 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61182 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5703361 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5703361 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5744606 # number of overall hits -system.cpu1.dcache.overall_hits::total 5744606 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 110713 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 110713 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 77621 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 77621 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23905 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 23905 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16417 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16417 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23076 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23076 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 188334 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 188334 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 212239 # number of overall misses -system.cpu1.dcache.overall_misses::total 212239 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1730591500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1730591500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2713528000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2713528000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316809000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 316809000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 632764000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 632764000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3307000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3307000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4444119500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4444119500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4444119500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4444119500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3128878 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3128878 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2762817 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2762817 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65150 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 65150 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 85980 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 85980 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84258 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 84258 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5891695 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5891695 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5956845 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5956845 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035384 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035384 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028095 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.028095 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.366922 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.366922 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190940 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190940 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273873 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273873 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031966 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031966 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035629 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035629 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15631.330557 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15631.330557 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34958.683861 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34958.683861 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19297.618322 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19297.618322 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27420.870168 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27420.870168 # average StoreCondReq miss latency +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 33 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12680697 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12680697 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3066133 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3066133 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2748576 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2748576 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41842 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 41842 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69851 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 69851 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61610 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61610 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5814709 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5814709 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5856551 # number of overall hits +system.cpu1.dcache.overall_hits::total 5856551 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 112800 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 112800 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 79377 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 79377 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24461 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 24461 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16636 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16636 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23088 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23088 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 192177 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 192177 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 216638 # number of overall misses +system.cpu1.dcache.overall_misses::total 216638 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1758096000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1758096000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2710284000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2710284000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320294000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 320294000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 628163500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 628163500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3848000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3848000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4468380000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4468380000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4468380000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4468380000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3178933 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3178933 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2827953 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2827953 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66303 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 66303 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86487 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 86487 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84698 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 84698 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6006886 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6006886 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6073189 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6073189 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035484 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035484 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028069 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028069 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.368927 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.368927 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192353 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192353 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272592 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272592 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031993 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031993 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035671 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035671 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.957447 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.957447 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34144.449904 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34144.449904 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19253.065641 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19253.065641 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27207.358801 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27207.358801 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23597.011161 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23597.011161 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20939.221821 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20939.221821 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23251.377636 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23251.377636 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20626.021289 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20626.021289 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1624,147 +1629,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 144073 # number of writebacks -system.cpu1.dcache.writebacks::total 144073 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11530 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11530 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 168 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 168 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 168 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110545 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 110545 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 77621 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 77621 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23508 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23508 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4887 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4887 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23076 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23076 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 188166 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 188166 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 211674 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 211674 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3107 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5537 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1611627000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1611627000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2635907000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2635907000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 421753500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 421753500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88480500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88480500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 609718000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 609718000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3277000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3277000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4247534000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4247534000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4669287500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4669287500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 430617000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 430617000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 292641500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 292641500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 723258500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 723258500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035331 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035331 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028095 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028095 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360829 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360829 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056839 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056839 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273873 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273873 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031937 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031937 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035535 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035535 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14578.922611 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14578.922611 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33958.683861 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33958.683861 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17940.849923 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17940.849923 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18105.279312 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18105.279312 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26422.170220 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26422.170220 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 148314 # number of writebacks +system.cpu1.dcache.writebacks::total 148314 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 199 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11732 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11732 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 199 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 199 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 199 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 199 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112601 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 112601 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79377 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 79377 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 24003 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 24003 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4904 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4904 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23088 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23088 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 191978 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 191978 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 215981 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 215981 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3083 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3083 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2425 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5508 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5508 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1635811500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1635811500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2630907000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2630907000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 431572500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 431572500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89921000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89921000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 605110500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 605110500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3813000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3813000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4266718500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4266718500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4698291000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4698291000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439541500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439541500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303268000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303268000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742809500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742809500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035421 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035421 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028069 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028069 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.362020 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362020 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056702 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056702 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272592 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272592 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031960 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031960 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035563 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035563 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14527.504196 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14527.504196 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33144.449904 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33144.449904 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17979.940007 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17979.940007 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18336.256117 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18336.256117 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26208.874740 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26208.874740 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22573.334184 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22573.334184 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22058.861740 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22058.861740 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138595.751529 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 138595.751529 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 120428.600823 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 120428.600823 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 130622.810186 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 130622.810186 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22225.038807 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22225.038807 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21753.260703 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21753.260703 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142569.412910 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142569.412910 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125058.969072 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125058.969072 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134860.112564 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134860.112564 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 461792 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.311266 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13251136 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 462304 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 28.663252 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 106195905000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.311266 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 463432 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.310833 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13456384 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463944 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 29.004328 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 106360036500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310833 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973263 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973263 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 27889184 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 27889184 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13251136 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13251136 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13251136 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13251136 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13251136 # number of overall hits -system.cpu1.icache.overall_hits::total 13251136 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 462304 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 462304 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 462304 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 462304 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 462304 # number of overall misses -system.cpu1.icache.overall_misses::total 462304 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4149723500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4149723500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4149723500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4149723500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4149723500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4149723500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13713440 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13713440 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13713440 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13713440 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13713440 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13713440 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033712 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.033712 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033712 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.033712 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033712 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.033712 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8976.179094 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8976.179094 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8976.179094 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8976.179094 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8976.179094 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8976.179094 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 28304600 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 28304600 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13456384 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13456384 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13456384 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13456384 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13456384 # number of overall hits +system.cpu1.icache.overall_hits::total 13456384 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 463944 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 463944 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 463944 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 463944 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 463944 # number of overall misses +system.cpu1.icache.overall_misses::total 463944 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4214272500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4214272500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4214272500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4214272500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4214272500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4214272500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13920328 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13920328 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13920328 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13920328 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13920328 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13920328 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033329 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.033329 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033329 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.033329 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033329 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.033329 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9083.580130 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9083.580130 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9083.580130 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9083.580130 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9083.580130 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9083.580130 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1773,437 +1778,448 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 461792 # number of writebacks -system.cpu1.icache.writebacks::total 461792 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 462304 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 462304 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 462304 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 462304 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 462304 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 462304 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 463432 # number of writebacks +system.cpu1.icache.writebacks::total 463432 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463944 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 463944 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 463944 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 463944 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 463944 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 463944 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3918571500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3918571500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3918571500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3918571500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3918571500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3918571500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3982300500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3982300500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3982300500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3982300500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3982300500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3982300500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033712 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.033712 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.033712 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8476.179094 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033329 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.033329 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.033329 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8583.580130 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8583.580130 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8583.580130 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 106104 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 106112 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 118303 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 118321 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 50448 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 30131 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14949.290291 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1034569 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 45193 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 22.892240 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 50079 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 31154 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14935.857031 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1041086 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 46286 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 22.492460 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14514.476865 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.312401 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.041451 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 430.459574 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.885893 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000141 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026273 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.912432 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 971 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14059 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 54 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 913 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14446.292104 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.202140 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.081939 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 484.280848 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.881732 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000195 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.029558 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.911612 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 981 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 38 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14113 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 47 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 926 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1365 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12304 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059265 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.858093 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 20957142 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 20957142 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2443 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1453 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 3896 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 89055 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 89055 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 506752 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 506752 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16650 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 16650 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 453968 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 453968 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 75407 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 75407 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2443 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1453 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 453968 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 92057 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 549921 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2443 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1453 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 453968 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 92057 # number of overall hits -system.cpu1.l2cache.overall_hits::total 549921 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 349 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 301 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 650 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28928 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28928 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23076 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23076 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32043 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32043 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8336 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 8336 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63533 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 63533 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 349 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 301 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 8336 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 95576 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 104562 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 349 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 301 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 8336 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 95576 # number of overall misses -system.cpu1.l2cache.overall_misses::total 104562 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7078500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6021500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 13100000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 62132500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 62132500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 59033500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 59033500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3231500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3231500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1646554500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1646554500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 475139500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 475139500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1418811000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1418811000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7078500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6021500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 475139500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3065365500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3553605000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7078500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6021500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 475139500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3065365500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3553605000 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2792 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1754 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 4546 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 89055 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 89055 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 506752 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 506752 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28928 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28928 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23076 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23076 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 48693 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 48693 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 462304 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 462304 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 138940 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 138940 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2792 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1754 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 462304 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 187633 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 654483 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2792 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1754 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 462304 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 187633 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 654483 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.171608 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.142983 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1668 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12049 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059875 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002319 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.861389 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 21151055 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 21151055 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2455 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1474 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 3929 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 92001 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 92001 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 509646 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 509646 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18183 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 18183 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 455037 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 455037 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77628 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 77628 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2455 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1474 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 455037 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 95811 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 554777 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2455 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1474 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 455037 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 95811 # number of overall hits +system.cpu1.l2cache.overall_hits::total 554777 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 300 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 648 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28973 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28973 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23087 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23087 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32221 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 32221 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8907 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 8907 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63880 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 63880 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 300 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 8907 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 96101 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 105656 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 300 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 8907 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 96101 # number of overall misses +system.cpu1.l2cache.overall_misses::total 105656 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7097500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5968000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 13065500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64302000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 64302000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 54899500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 54899500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3760000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3760000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1640601500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1640601500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 530446000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 530446000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1436061500 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1436061500 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7097500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5968000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 530446000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3076663000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3620174500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7097500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5968000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 530446000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3076663000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3620174500 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2803 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1774 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 4577 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 92001 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 92001 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 509646 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 509646 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28973 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28973 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23087 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23087 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50404 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 50404 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 463944 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 463944 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 141508 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 141508 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2803 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1774 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 463944 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 191912 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 660433 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2803 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1774 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 463944 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 191912 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 660433 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.124153 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.169109 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.141577 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.658062 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.658062 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018031 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018031 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.457269 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.457269 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.171608 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018031 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.509377 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.159763 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.171608 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018031 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.509377 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.159763 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20004.983389 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20153.846154 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2147.832550 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2147.832550 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2558.220662 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2558.220662 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51385.778485 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51385.778485 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 56998.500480 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 56998.500480 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22331.874774 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22331.874774 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20004.983389 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 56998.500480 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32072.544363 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 33985.625753 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20004.983389 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 56998.500480 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32072.544363 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 33985.625753 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.639255 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.639255 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.019198 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.019198 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.451423 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.451423 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.124153 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.169109 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.019198 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.500756 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.159980 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.124153 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.169109 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.019198 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.500756 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.159980 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20395.114943 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19893.333333 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20162.808642 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2219.376661 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2219.376661 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2377.939966 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2377.939966 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 3760000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 3760000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50917.150306 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50917.150306 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59553.834063 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59553.834063 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22480.612085 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22480.612085 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20395.114943 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19893.333333 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59553.834063 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32014.890584 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 34263.785303 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20395.114943 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19893.333333 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59553.834063 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32014.890584 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 34263.785303 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 25259 # number of writebacks -system.cpu1.l2cache.writebacks::total 25259 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 80 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 80 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 80 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 80 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 80 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 349 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 301 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 650 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 18771 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 18771 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28928 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28928 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23076 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23076 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31963 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 31963 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8336 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8336 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63533 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63533 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 349 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 301 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8336 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95496 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 104482 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 349 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 301 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8336 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95496 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 18771 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 123253 # number of overall MSHR misses +system.cpu1.l2cache.writebacks::writebacks 25848 # number of writebacks +system.cpu1.l2cache.writebacks::total 25848 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 72 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 72 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 72 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 72 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 348 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 300 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 648 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 21105 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 21105 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28973 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28973 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23087 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23087 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32149 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 32149 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8907 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8907 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63880 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63880 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 348 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 300 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8907 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 96029 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 105584 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 348 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 300 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8907 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 96029 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 21105 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 126689 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3284 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3083 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3260 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2425 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5714 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4215500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9200000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 917123117 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 917123117 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 588451500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 588451500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 436537000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 436537000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3051500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3051500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1446140000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1446140000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 425123500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 425123500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1037613000 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1037613000 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4215500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 425123500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2483753000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2918076500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4215500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 425123500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2483753000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 917123117 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3835199617 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5508 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5685 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5009500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4168000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9177500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 934365172 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 934365172 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 576596500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 576596500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 431875500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 431875500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3550000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3550000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1440609000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1440609000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 477004000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 477004000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1052781500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1052781500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5009500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4168000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 477004000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2493390500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2979572000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5009500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4168000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 477004000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2493390500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 934365172 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3913937172 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 405408000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 427627000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 274409000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 274409000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414529000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436748000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 285072000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 285072000 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 679817000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 702036000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.142983 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699601000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721820000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.141577 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.656419 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.656419 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018031 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.457269 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.457269 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159641 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637826 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637826 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019198 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451423 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451423 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159871 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.188321 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14153.846154 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48858.511374 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.935149 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.935149 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.360028 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18917.360028 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45244.188593 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45244.188593 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50998.500480 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16331.874774 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16331.874774 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27928.987768 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31116.480873 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191827 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14162.808642 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44272.218526 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19901.166603 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19901.166603 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18706.436523 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18706.436523 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3550000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3550000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44810.382905 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44810.382905 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53553.834063 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16480.612085 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16480.612085 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28219.919685 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30894.056879 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130482.137110 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130215.286236 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112925.514403 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 112925.514403 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134456.373662 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133971.779141 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117555.463918 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117555.463918 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 122777.135633 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 122862.443122 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127015.432099 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126969.217238 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1312846 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 662941 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10057 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 166384 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164278 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 10119 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 648543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2430 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2430 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 115438 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 506752 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 85166 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 22864 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 70245 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84598 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 55915 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 53326 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 462304 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 211564 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 31 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1378500 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707096 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4372 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7009 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2096977 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58614596 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 23813135 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7016 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 82445915 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 350196 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 987919 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.185835 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.394416 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1324645 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668824 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10099 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 169409 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166956 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2453 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 10097 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 652790 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2425 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2425 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 119017 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 519745 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 86537 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 25449 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70337 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40896 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57665 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55147 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463944 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215084 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391674 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722021 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4392 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7022 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2125109 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59352772 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24485096 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7096 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11212 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 83856176 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 356096 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 999531 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.187033 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.396182 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 806435 81.63% 81.63% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 179378 18.16% 99.79% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2106 0.21% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 815039 81.54% 81.54% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 182039 18.21% 99.75% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2453 0.25% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 987919 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1267256999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 999531 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1279051999 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79126203 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79434008 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 693633000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 696093000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 311803500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 318231000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 4217000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 4219000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31009 # Transaction distribution -system.iobus.trans_dist::ReadResp 31009 # Transaction distribution +system.iobus.trans_dist::ReadReq 31021 # Transaction distribution +system.iobus.trans_dist::ReadResp 31021 # Transaction distribution system.iobus.trans_dist::WriteReq 59425 # Transaction distribution system.iobus.trans_dist::WriteResp 59425 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) @@ -2226,9 +2242,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -2249,14 +2265,14 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48738000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48746500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -2264,7 +2280,7 @@ system.iobus.reqLayer4.occupancy 16000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 609000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2274,7 +2290,7 @@ system.iobus.reqLayer14.occupancy 11500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) @@ -2286,54 +2302,54 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6150500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6162500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186301036 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187117449 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36433 # number of replacements -system.iocache.tags.tagsinuse 1.018273 # Cycle average of tags in use +system.iocache.tags.replacements 36461 # number of replacements +system.iocache.tags.tagsinuse 14.380044 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290654223000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.018273 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.063642 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.063642 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290746348000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.380044 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898753 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898753 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses -system.iocache.demand_misses::total 243 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 243 # number of overall misses -system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31405376 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31405376 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4738596660 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4738596660 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31405376 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31405376 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31405376 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31405376 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32874877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32874877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4582462572 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4582462572 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32874877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32874877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32874877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32874877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2342,40 +2358,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129240.230453 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129240.230453 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130813.732884 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130813.732884 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129240.230453 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129240.230453 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 816 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128921.086275 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128921.086275 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126503.494148 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126503.494148 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128921.086275 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128921.086275 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128921.086275 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128921.086275 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 79 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.329114 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.333333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19255376 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19255376 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927396660 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2927396660 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19255376 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19255376 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19255376 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19255376 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20124877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20124877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2769551646 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2769551646 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20124877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20124877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20124877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20124877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2384,304 +2400,303 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79240.230453 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79240.230453 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80813.732884 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80813.732884 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78921.086275 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78921.086275 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76456.262312 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76456.262312 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78921.086275 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78921.086275 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78921.086275 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78921.086275 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 123618 # number of replacements -system.l2c.tags.tagsinuse 63093.840837 # Cycle average of tags in use -system.l2c.tags.total_refs 421259 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 187589 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.245649 # Average number of references to valid blocks. +system.l2c.tags.replacements 123661 # number of replacements +system.l2c.tags.tagsinuse 63058.402721 # Cycle average of tags in use +system.l2c.tags.total_refs 421257 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 187718 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.244095 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13244.114990 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.878668 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.996497 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7731.277102 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2849.874177 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36272.088123 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954483 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1120.568935 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 367.321258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1502.766604 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.202089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000059 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.117970 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.553468 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13491.325958 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.985555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.052859 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7361.006580 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2805.566875 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35728.682862 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1443.499308 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 410.819619 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1814.508588 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.205861 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.112320 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042810 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.545176 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.017099 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.005605 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022930 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.962736 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32107 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31859 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4716 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 27259 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2381 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29068 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.489914 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.486130 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5836461 # Number of tag accesses -system.l2c.tags.data_accesses 5836461 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 257531 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 257531 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32441 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1723 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34164 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2115 # number of SCUpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.022026 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.006269 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027687 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.962195 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 32044 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32009 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5120 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26618 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2325 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29253 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.488953 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.488419 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5830329 # Number of tag accesses +system.l2c.tags.data_accesses 5830329 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 257370 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 257370 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 32263 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1924 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34187 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2044 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 899 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3014 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4177 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1342 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5519 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 81 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 92 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28642 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 47295 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47544 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 6315 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 4707 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3005 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 137714 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 81 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 92 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28642 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51472 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47544 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 15 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6315 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 6049 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 3005 # number of demand (read+write) hits -system.l2c.demand_hits::total 143233 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 81 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 92 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28642 # number of overall hits -system.l2c.overall_hits::cpu0.data 51472 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47544 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 15 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6315 # number of overall hits -system.l2c.overall_hits::cpu1.data 6049 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 3005 # number of overall hits -system.l2c.overall_hits::total 143233 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9610 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2300 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11910 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1322 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1977 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11124 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7851 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 18975 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses +system.l2c.SCUpgradeReq_hits::total 2943 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4115 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1385 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5500 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 95 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 72 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 28709 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 46783 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47559 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 20 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 6543 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 5065 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3419 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 138278 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 95 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 72 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28709 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 50898 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47559 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 20 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6543 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 6450 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 3419 # number of demand (read+write) hits +system.l2c.demand_hits::total 143778 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 95 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 72 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28709 # number of overall hits +system.l2c.overall_hits::cpu0.data 50898 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47559 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 20 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6543 # number of overall hits +system.l2c.overall_hits::cpu1.data 6450 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 3419 # number of overall hits +system.l2c.overall_hits::total 143778 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9386 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2249 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11635 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 587 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1308 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1895 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11114 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7777 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 18891 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 5 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 17856 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 8887 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134682 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17503 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8876 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134571 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2021 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 752 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5338 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 169545 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2364 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 804 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5455 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 169581 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17856 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20011 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 134682 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17503 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19990 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 134571 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2021 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8603 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5338 # number of demand (read+write) misses -system.l2c.demand_misses::total 188520 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses +system.l2c.demand_misses::cpu1.inst 2364 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8581 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5455 # number of demand (read+write) misses +system.l2c.demand_misses::total 188472 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17856 # number of overall misses -system.l2c.overall_misses::cpu0.data 20011 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 134682 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17503 # number of overall misses +system.l2c.overall_misses::cpu0.data 19990 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 134571 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2021 # number of overall misses -system.l2c.overall_misses::cpu1.data 8603 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 5338 # number of overall misses -system.l2c.overall_misses::total 188520 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 34729000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 5015500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 39744500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3979500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2518000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 6497500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1612676500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1029832500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2642509000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 823500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 272000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2350559500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 1210448500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 132500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 268405000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 104648000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 24352402389 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 823500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 272000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 2350559500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 2823125000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 132500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 268405000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1134480500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 26994911389 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 823500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 272000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 2350559500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 2823125000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 132500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 268405000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1134480500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of overall miss cycles -system.l2c.overall_miss_latency::total 26994911389 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 257531 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 257531 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 42051 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4023 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 46074 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2770 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2221 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4991 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15301 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9193 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24494 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 87 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 94 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 46498 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 56182 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182226 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 16 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 18 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 8336 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 5459 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8343 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 307259 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 46498 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 71483 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182226 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 16 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 18 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 8336 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 14652 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8343 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 331753 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 46498 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 71483 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182226 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 16 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 18 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 8336 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 14652 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8343 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 331753 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.228532 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.571713 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.258497 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.236462 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.595227 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.396113 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.727011 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.854019 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.774680 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.021277 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.384017 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158182 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.242442 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.137754 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551798 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.021277 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.384017 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.279941 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.242442 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.587155 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.568254 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.021277 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.384017 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.279941 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.242442 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.587155 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.568254 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3613.839750 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2180.652174 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3337.069689 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6075.572519 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1904.689864 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3286.545271 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 144972.716649 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131172.143676 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 139262.661397 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 137250 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 136000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131639.756944 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136204.399685 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132500 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132808.015834 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139159.574468 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 143633.857613 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 131639.756944 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 141078.656739 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 132808.015834 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 131870.335929 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 143193.886001 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 131639.756944 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 141078.656739 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 132808.015834 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 131870.335929 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 143193.886001 # average overall miss latency +system.l2c.overall_misses::cpu1.inst 2364 # number of overall misses +system.l2c.overall_misses::cpu1.data 8581 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 5455 # number of overall misses +system.l2c.overall_misses::total 188472 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 30248000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 5203000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 35451000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3836500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2726000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 6562500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1620087000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1017624500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2637711500 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 677000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 362000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2302051000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 1209307000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19566804778 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 146500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 313582000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 113115000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 857081845 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 24363127123 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 677000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 362000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 2302051000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 2829394000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19566804778 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 146500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 313582000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1130739500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 857081845 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 27000838623 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 677000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 362000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 2302051000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 2829394000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19566804778 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 146500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 313582000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1130739500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 857081845 # number of overall miss cycles +system.l2c.overall_miss_latency::total 27000838623 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 257370 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 257370 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 41649 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4173 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 45822 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2631 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2207 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4838 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15229 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9162 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 24391 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 74 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 46212 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 55659 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182130 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 21 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 13 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 8907 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 5869 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8874 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 307859 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 74 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 46212 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 70888 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182130 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 21 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 13 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 8907 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 15031 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8874 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 332250 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 74 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 46212 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 70888 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182130 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 21 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 13 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 8907 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 15031 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8874 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 332250 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.225360 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.538941 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.253917 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.223109 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.592660 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.391691 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.729792 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.848832 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.774507 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.050000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027027 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.378754 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.159471 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738873 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.265409 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.136991 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.614717 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.550840 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.050000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.027027 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.378754 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.281994 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738873 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.265409 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.570887 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.614717 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.567260 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.050000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.027027 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.378754 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.281994 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738873 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.265409 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.570887 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.614717 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.567260 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3222.672065 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2313.472655 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3046.927374 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6535.775128 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2084.097859 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3463.060686 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145769.929818 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130850.520766 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 139627.944524 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 135400 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 181000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131523.224590 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136244.592159 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 146500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132648.900169 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140690.298507 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 143666.608423 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135400 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 181000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 131523.224590 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 141540.470235 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 146500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 132648.900169 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 131772.462417 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 143261.803467 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135400 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 181000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 131523.224590 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 141540.470235 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 146500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 132648.900169 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 131772.462417 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 143261.803467 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2690,274 +2705,270 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 97095 # number of writebacks -system.l2c.writebacks::total 97095 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 17 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 2818 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 2818 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 9610 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2300 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11910 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1322 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1977 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11124 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7851 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 18975 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadSharedReq MSHR misses +system.l2c.writebacks::writebacks 96987 # number of writebacks +system.l2c.writebacks::total 96987 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 7 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 2809 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 2809 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 9386 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2249 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11635 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 587 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1308 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1895 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11114 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7777 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 18891 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 5 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17851 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8886 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17501 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8876 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134571 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2010 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 752 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 169528 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2357 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 804 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5455 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 169572 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 5 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17851 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20010 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17501 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19990 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134571 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2010 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8603 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 188503 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2357 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8581 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5455 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 188463 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 5 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17851 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20010 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17501 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19990 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134571 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2010 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8603 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 188503 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2357 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8581 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5455 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 188463 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3104 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 44163 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30983 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3080 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 44099 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30924 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5534 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 75146 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 725072500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172861000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 897933500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 50674000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 101405500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 152079500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1501436500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 951322500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2452759000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 763500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2171508000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1121559000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 122500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 247283000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 97128000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 22655529389 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 763500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2171508000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2622995500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 122500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 247283000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1048450500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 25108288389 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 763500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2171508000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2622995500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 122500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 247283000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1048450500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 25108288389 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5505 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 75023 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 682643500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 162589000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 845232500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 43754500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 96726500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 140481000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1508944512 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 939851506 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2448796018 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 627000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 342000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2126838009 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1120542510 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18221057894 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 136500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 289400510 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 105072505 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 802516896 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 22666533824 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 627000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 342000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 2126838009 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2629487022 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18221057894 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 136500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 289400510 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1044924011 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 802516896 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 25115329842 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 627000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 342000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 2126838009 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2629487022 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18221057894 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 136500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 289400510 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1044924011 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 802516896 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 25115329842 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5812758500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801306000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 349483000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7205089000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4715021500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 233050000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4948071500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359044000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7203197500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702516500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243805501 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4946322001 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10527780000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503822500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 582533000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 12153160500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602849501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12149519501 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.228532 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.571713 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.258497 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.236462 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.595227 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.396113 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.727011 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854019 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.774680 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158165 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.137754 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.551743 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.279927 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.587155 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.568203 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.279927 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.587155 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.568203 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75449.791883 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75156.956522 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75393.240974 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77364.885496 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76706.127080 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76924.380374 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134972.716649 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121172.143676 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 129262.661397 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126216.407833 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129159.574468 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133638.864312 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131084.232884 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131084.232884 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225360 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.538941 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.253917 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.223109 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.592660 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.391691 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.729792 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.848832 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.774507 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.159471 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.136991 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.550811 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281994 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.570887 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.567233 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281994 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.570887 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.567233 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72729.970168 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72293.908404 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72645.681135 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74539.182283 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73949.923547 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.453826 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135769.705956 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120850.135785 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129627.654333 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126244.086300 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130687.195274 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133669.083481 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131540.121161 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121771.822748 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 133263.982012 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131540.121161 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121771.822748 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 133263.982012 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182446.908349 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182316.341923 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112591.172680 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163147.634898 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165132.262810 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95905.349794 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159702.788626 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116572.727273 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163341.515681 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.368645 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100538.350928 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159950.911945 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174263.486336 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174137.875296 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 105264.365739 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 161727.310835 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109509.446140 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 161943.930541 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44163 # Transaction distribution -system.membus.trans_dist::ReadResp 213934 # Transaction distribution -system.membus.trans_dist::WriteReq 30983 # Transaction distribution -system.membus.trans_dist::WriteResp 30983 # Transaction distribution -system.membus.trans_dist::WritebackDirty 133285 # Transaction distribution -system.membus.trans_dist::CleanEvict 14406 # Transaction distribution -system.membus.trans_dist::UpgradeReq 73490 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39839 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13966 # Transaction distribution +system.membus.trans_dist::ReadReq 44099 # Transaction distribution +system.membus.trans_dist::ReadResp 213926 # Transaction distribution +system.membus.trans_dist::WriteReq 30924 # Transaction distribution +system.membus.trans_dist::WriteResp 30924 # Transaction distribution +system.membus.trans_dist::WritebackDirty 133193 # Transaction distribution +system.membus.trans_dist::CleanEvict 14771 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73670 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39871 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 39499 # Transaction distribution -system.membus.trans_dist::ReadExResp 18896 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 169771 # Transaction distribution +system.membus.trans_dist::ReadExReq 39385 # Transaction distribution +system.membus.trans_dist::ReadExResp 18791 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 169827 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 786162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108909 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108909 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 895071 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650336 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 772080 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 845035 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28044 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18307596 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18498522 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20815642 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 120564 # Total snoops (count) -system.membus.snoop_fanout::samples 581920 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18297804 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18488238 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20806382 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 121083 # Total snoops (count) +system.membus.snoop_fanout::samples 581994 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 581920 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 581994 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 581920 # Request fanout histogram -system.membus.reqLayer0.occupancy 88268000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 581994 # Request fanout histogram +system.membus.reqLayer0.occupancy 88286500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11611500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11391000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 967762037 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 968108262 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1134685490 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1106274782 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64105002 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1388877 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3000,52 +3011,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 959770 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 518663 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 138023 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20272 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 44166 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 467162 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30983 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30983 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 390842 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 84262 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 107575 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 150428 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50605 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50605 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 423011 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 960339 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 518534 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 139328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20435 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19626 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 809 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44102 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 468032 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30924 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30924 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 390589 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 105128 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 107757 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42814 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 150571 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 82 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50426 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50426 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 423945 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1226424 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 245800 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1472224 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34332563 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3643847 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37976410 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 437847 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 895583 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.335708 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.474219 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1240075 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253445 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1493520 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34222158 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3776032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 37998190 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 438746 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 896439 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.337268 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.474682 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 595769 66.52% 66.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 298974 33.38% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 840 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 594908 66.36% 66.36% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 300722 33.55% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 809 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 895583 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 863469481 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 896439 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 863728414 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342622 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 647119226 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 645946273 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 200312901 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 202615858 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index b6b1f5126..913ae877a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909596 # Number of seconds simulated -sim_ticks 2909596171500 # Number of ticks simulated -final_tick 2909596171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909587 # Number of seconds simulated +sim_ticks 2909586837500 # Number of ticks simulated +final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 322522 # Simulator instruction rate (inst/s) -host_op_rate 388861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8344730622 # Simulator tick rate (ticks/s) -host_mem_usage 560756 # Number of bytes of host memory used -host_seconds 348.67 # Real time elapsed on the host -sim_insts 112455206 # Number of instructions simulated -sim_ops 135585876 # Number of ops (including micro ops) simulated +host_inst_rate 929184 # Simulator instruction rate (inst/s) +host_op_rate 1120306 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24040663881 # Simulator tick rate (ticks/s) +host_mem_usage 581600 # Number of bytes of host memory used +host_seconds 121.03 # Real time elapsed on the host +sim_insts 112457033 # Number of instructions simulated +sim_ops 135588117 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1186404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8901796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10089736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1186404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1186404 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7511872 # Number of bytes written to this memory +system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7529396 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139611 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166625 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117373 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166628 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121754 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 407756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3059461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059493 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 407756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2581758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581810 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2587780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2581758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2587833 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581810 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 407756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3065484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 407801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065516 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6055525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166625 # Number of read requests accepted -system.physmem.writeReqs 121754 # Number of write requests accepted -system.physmem.readBursts 166625 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121754 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10656448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue -system.physmem.bytesWritten 7541952 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10089736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7529396 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166628 # Number of read requests accepted +system.physmem.writeReqs 121756 # Number of write requests accepted +system.physmem.readBursts 166628 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10657408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 7542016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10077 # Per bank write bursts system.physmem.perBankRdBursts::1 9979 # Per bank write bursts system.physmem.perBankRdBursts::2 10695 # Per bank write bursts -system.physmem.perBankRdBursts::3 10661 # Per bank write bursts +system.physmem.perBankRdBursts::3 10660 # Per bank write bursts system.physmem.perBankRdBursts::4 18797 # Per bank write bursts -system.physmem.perBankRdBursts::5 9659 # Per bank write bursts -system.physmem.perBankRdBursts::6 9663 # Per bank write bursts -system.physmem.perBankRdBursts::7 10485 # Per bank write bursts +system.physmem.perBankRdBursts::5 9664 # Per bank write bursts +system.physmem.perBankRdBursts::6 9666 # Per bank write bursts +system.physmem.perBankRdBursts::7 10487 # Per bank write bursts system.physmem.perBankRdBursts::8 9276 # Per bank write bursts system.physmem.perBankRdBursts::9 9973 # Per bank write bursts system.physmem.perBankRdBursts::10 9232 # Per bank write bursts system.physmem.perBankRdBursts::11 8679 # Per bank write bursts -system.physmem.perBankRdBursts::12 9817 # Per bank write bursts +system.physmem.perBankRdBursts::12 9822 # Per bank write bursts system.physmem.perBankRdBursts::13 10379 # Per bank write bursts -system.physmem.perBankRdBursts::14 9722 # Per bank write bursts +system.physmem.perBankRdBursts::14 9723 # Per bank write bursts system.physmem.perBankRdBursts::15 9413 # Per bank write bursts system.physmem.perBankWrBursts::0 7393 # Per bank write bursts system.physmem.perBankWrBursts::1 7263 # Per bank write bursts @@ -86,35 +86,35 @@ system.physmem.perBankWrBursts::3 8171 # Pe system.physmem.perBankWrBursts::4 7489 # Per bank write bursts system.physmem.perBankWrBursts::5 7265 # Per bank write bursts system.physmem.perBankWrBursts::6 7108 # Per bank write bursts -system.physmem.perBankWrBursts::7 7659 # Per bank write bursts +system.physmem.perBankWrBursts::7 7661 # Per bank write bursts system.physmem.perBankWrBursts::8 7080 # Per bank write bursts system.physmem.perBankWrBursts::9 7523 # Per bank write bursts system.physmem.perBankWrBursts::10 6695 # Per bank write bursts system.physmem.perBankWrBursts::11 6470 # Per bank write bursts -system.physmem.perBankWrBursts::12 7534 # Per bank write bursts +system.physmem.perBankWrBursts::12 7533 # Per bank write bursts system.physmem.perBankWrBursts::13 7859 # Per bank write bursts system.physmem.perBankWrBursts::14 7264 # Per bank write bursts system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 2909595814500 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 2909586480500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157053 # Read request sizes (log2) +system.physmem.readPktSize::6 157056 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117373 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117375 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,117 +159,114 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58778 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 309.611351 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.749688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.493771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21450 36.49% 36.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14701 25.01% 61.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6086 10.35% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3214 5.47% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2550 4.34% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1476 2.51% 84.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1054 1.79% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1089 1.85% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7158 12.18% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58778 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5758 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.915596 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 590.311059 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5757 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.818528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.858167 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.750191 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21399 36.43% 36.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14737 25.09% 61.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6061 10.32% 71.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3228 5.50% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2535 4.32% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1458 2.48% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1057 1.80% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1079 1.84% 87.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7188 12.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58742 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5615 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.654497 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 597.763680 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5614 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5758 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5758 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.465960 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.711564 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.116644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4961 86.16% 86.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 87 1.51% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.57% 88.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 172 2.99% 91.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 23 0.40% 91.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 160 2.78% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 50 0.87% 95.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.10% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.12% 95.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 22 0.38% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.03% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.10% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.83% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.17% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.35% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.28% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5758 # Writes before turning the bus around for reads -system.physmem.totQLat 1616458000 # Total ticks spent queuing -system.physmem.totMemAccLat 4738464250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9708.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5615 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5615 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.987355 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.791633 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.100649 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4949 88.14% 88.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 78 1.39% 89.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 32 0.57% 90.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.82% 90.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 24 0.43% 91.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.36% 91.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.82% 92.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.07% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 153 2.72% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.20% 95.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.23% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 63 1.12% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.46% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 103 1.83% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.14% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.12% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads +system.physmem.totQLat 1624802000 # Total ticks spent queuing +system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28458.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -280,39 +277,39 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing -system.physmem.readRowHits 136072 # Number of row buffer hits during reads -system.physmem.writeRowHits 89499 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes -system.physmem.avgGap 10089485.76 # Average gap between requests -system.physmem.pageHitRate 79.32 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 230958000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126018750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702124800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392882400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90366604425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666484751750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948343566605 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.628332 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772164122000 # Time in different power states -system.physmem_0.memoryStateTime::REF 97157580000 # Time in different power states +system.physmem.readRowHits 136095 # Number of row buffer hits during reads +system.physmem.writeRowHits 89528 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes +system.physmem.avgGap 10089278.46 # Average gap between requests +system.physmem.pageHitRate 79.34 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230829480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125948625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702195000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392895360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90325761075 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666515907500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948333254960 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.626580 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772215900000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97157320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40267816750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40208512500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213403680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116440500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 596622000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370740240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88072375230 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668497233500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947907041630 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.478302 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775541834250 # Time in different power states -system.physmem_1.memoryStateTime::REF 97157580000 # Time in different power states +system.physmem_1.actEnergy 213260040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116362125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.477277 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states +system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36896609250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -370,9 +367,9 @@ system.cpu.dtb.walker.walkWaitTime::samples 9546 # system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 13161.947982 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10924.263330 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8540.848722 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 13159.035492 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10920.963738 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8541.710442 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency @@ -392,9 +389,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24520178 # DTB read hits +system.cpu.dtb.read_hits 24520655 # DTB read hits system.cpu.dtb.read_misses 8124 # DTB read misses -system.cpu.dtb.write_hits 19606457 # DTB write hits +system.cpu.dtb.write_hits 19606816 # DTB write hits system.cpu.dtb.write_misses 1422 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -405,12 +402,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24528302 # DTB read accesses -system.cpu.dtb.write_accesses 19607879 # DTB write accesses +system.cpu.dtb.read_accesses 24528779 # DTB read accesses +system.cpu.dtb.write_accesses 19608238 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44126635 # DTB hits +system.cpu.dtb.hits 44127471 # DTB hits system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 44136181 # DTB accesses +system.cpu.dtb.accesses 44137017 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,7 +465,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115552414 # ITB inst hits +system.cpu.itb.inst_hits 115554258 # ITB inst hits system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -485,40 +482,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115557177 # ITB inst accesses -system.cpu.itb.hits 115552414 # DTB hits +system.cpu.itb.inst_accesses 115559021 # ITB inst accesses +system.cpu.itb.hits 115554258 # DTB hits system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115557177 # DTB accesses -system.cpu.numCycles 5819192343 # number of cpu cycles simulated +system.cpu.itb.accesses 115559021 # DTB accesses +system.cpu.numCycles 5819173675 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.committedInsts 112455206 # Number of instructions committed -system.cpu.committedOps 135585876 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119891340 # Number of integer alu accesses +system.cpu.committedInsts 112457033 # Number of instructions committed +system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9892021 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15230391 # number of instructions that are conditional controls -system.cpu.num_int_insts 119891340 # number of integer instructions +system.cpu.num_func_calls 9892146 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls +system.cpu.num_int_insts 119893391 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218059811 # number of times the integer registers were read -system.cpu.num_int_register_writes 82644916 # number of times the integer registers were written +system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read +system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489735153 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51893214 # number of times the CC registers were written -system.cpu.num_mem_refs 45407055 # number of memory refs -system.cpu.num_load_insts 24842618 # Number of load instructions -system.cpu.num_store_insts 20564437 # Number of store instructions -system.cpu.num_idle_cycles 5379072985.844151 # Number of idle cycles -system.cpu.num_busy_cycles 440119357.155849 # Number of busy cycles -system.cpu.not_idle_fraction 0.075632 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.924368 # Percentage of idle cycles -system.cpu.Branches 25916470 # Number of branches fetched +system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written +system.cpu.num_mem_refs 45407924 # number of memory refs +system.cpu.num_load_insts 24843119 # Number of load instructions +system.cpu.num_store_insts 20564805 # Number of store instructions +system.cpu.num_idle_cycles 5379054575.844151 # Number of idle cycles +system.cpu.num_busy_cycles 440119099.155849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075633 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924367 # Percentage of idle cycles +system.cpu.Branches 25916787 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93173703 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114388 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93175095 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114406 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -546,18 +543,18 @@ system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24842618 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24843119 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20564805 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138705936 # Class of executed instruction -system.cpu.dcache.tags.replacements 819217 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43235406 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819729 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.743536 # Average number of references to valid blocks. +system.cpu.op_class::total 138708215 # Class of executed instruction +system.cpu.dcache.tags.replacements 819223 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -566,152 +563,152 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177109321 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177109321 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23112521 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112521 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18823879 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18823879 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392783 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392783 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443242 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443242 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460216 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460216 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41936400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41936400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42329183 # number of overall hits -system.cpu.dcache.overall_hits::total 42329183 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 399911 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 399911 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298704 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298704 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118377 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118377 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits +system.cpu.dcache.overall_hits::total 42329995 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298709 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118381 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118381 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22756 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22756 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 698615 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 698615 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 816992 # number of overall misses -system.cpu.dcache.overall_misses::total 816992 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6486417000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6486417000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19109109000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19109109000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294489000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 294489000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 698621 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 698621 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 817002 # number of overall misses +system.cpu.dcache.overall_misses::total 817002 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6488404500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6488404500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100944000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19100944000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293896000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 293896000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25595526000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25595526000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25595526000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25595526000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23512432 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23512432 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511160 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511160 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465999 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465999 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460218 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460218 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42635015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42635015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43146175 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43146175 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_latency::cpu.data 25589348500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015620 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231585 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.231585 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048835 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048835 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231590 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.231590 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048832 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048832 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016386 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016386 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.018935 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.018935 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.651372 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.651372 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63973.395067 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63973.395067 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12940.589709 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12940.589709 # average LoadLockedReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16224.580658 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16224.580658 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63944.989940 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63944.989940 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12915.099314 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12915.099314 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36637.527107 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36637.527107 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31328.979966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31328.979966 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36628.370032 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36628.370032 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31321.035322 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31321.035322 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 683842 # number of writebacks -system.cpu.dcache.writebacks::total 683842 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 930 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 930 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14247 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14247 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398981 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 398981 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298704 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298704 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116321 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 116321 # number of SoftPFReq MSHR misses +system.cpu.dcache.writebacks::writebacks 683846 # number of writebacks +system.cpu.dcache.writebacks::total 683846 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 929 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14246 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14246 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 929 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 929 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 929 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 929 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398983 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 398983 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298709 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298709 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116322 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 116322 # number of SoftPFReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8510 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 8510 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 697685 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 697685 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 814006 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 814006 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 697692 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 697692 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 814014 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 814014 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6058107000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6058107000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18810405000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18810405000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1614233500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1614233500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6058749500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6058749500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18802235000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18802235000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1616519000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1616519000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115353500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115353500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24868512000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24868512000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26482745500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26482745500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278172000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278172000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089977500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089977500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368149500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368149500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24860984500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24860984500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26477503500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26477503500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278149500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278149500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089976500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089976500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368126000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368126000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227563 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227563 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227562 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227562 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses @@ -720,34 +717,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016364 system.cpu.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018866 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.018866 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15183.948609 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15183.948609 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62973.395067 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62973.395067 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.403908 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.403908 # average SoftPFReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15185.482840 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15185.482840 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62944.989940 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62944.989940 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13896.932652 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13896.932652 # average SoftPFReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13555.052879 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13555.052879 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35644.326594 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35644.326594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32533.845574 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32533.845574 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201624.124864 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201624.124864 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.004458 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.004458 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193576.200044 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193576.200044 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1695565 # number of replacements -system.cpu.icache.tags.tagsinuse 510.436866 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113856331 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1696077 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.129223 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1695721 # number of replacements +system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1696233 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.124044 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.436866 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.436852 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -756,44 +753,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 195 system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117248497 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117248497 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113856331 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113856331 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113856331 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113856331 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113856331 # number of overall hits -system.cpu.icache.overall_hits::total 113856331 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1696083 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1696083 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1696083 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1696083 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1696083 # number of overall misses -system.cpu.icache.overall_misses::total 1696083 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24267960000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24267960000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24267960000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24267960000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24267960000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24267960000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115552414 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115552414 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115552414 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115552414 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115552414 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115552414 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014678 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014678 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014678 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014678 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014678 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014678 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14308.238453 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14308.238453 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14308.238453 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14308.238453 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14308.238453 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14308.238453 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117250497 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117250497 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113858019 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113858019 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113858019 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113858019 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113858019 # number of overall hits +system.cpu.icache.overall_hits::total 113858019 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1696239 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1696239 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1696239 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1696239 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1696239 # number of overall misses +system.cpu.icache.overall_misses::total 1696239 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272134000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24272134000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24272134000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24272134000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24272134000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24272134000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115554258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115554258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115554258 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115554258 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115554258 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115554258 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014679 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014679 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014679 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014679 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,218 +799,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1695565 # number of writebacks -system.cpu.icache.writebacks::total 1695565 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696083 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1696083 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1696083 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1696083 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1696083 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1696083 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks +system.cpu.icache.writebacks::total 1695721 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1696239 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1696239 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1696239 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1696239 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1696239 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22571877000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22571877000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22571877000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22571877000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22571877000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22571877000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575895000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22575895000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575895000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22575895000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575895000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22575895000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014678 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014678 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014678 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13308.238453 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13308.238453 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13308.238453 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13308.238453 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13308.238453 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13308.238453 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87562 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64865.195753 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4544223 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 152797 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 29.740263 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87565 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 29.741728 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50196.671494 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 50196.713333 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799338 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012652 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.731977 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.980293 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.765940 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012649 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.721355 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.976923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.765941 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.148037 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.075729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56201 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6851 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56199 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40509810 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40509810 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7810 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 40512344 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40512344 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7807 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11849 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 683842 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 683842 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1664795 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1664795 # number of WritebackClean hits +system.cpu.l2cache.ReadReq_hits::total 11846 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 683846 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 683846 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1664945 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1664945 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 167026 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 167026 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678074 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1678074 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511640 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 511640 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7810 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 167031 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 167031 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678228 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1678228 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511642 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 511642 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7807 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 4039 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1678074 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 678666 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2368589 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7810 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 1678228 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 678673 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2368747 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7807 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 4039 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1678074 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 678666 # number of overall hits -system.cpu.l2cache.overall_hits::total 2368589 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1678228 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 678673 # number of overall hits +system.cpu.l2cache.overall_hits::total 2368747 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2740 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2740 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2742 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2742 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 128915 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 128915 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17976 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 17976 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12172 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 12172 # number of ReadSharedReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 128913 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 128913 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17978 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 17978 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12173 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 12173 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 17976 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141087 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 159072 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 17978 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141086 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 159073 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 17976 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141087 # number of overall misses -system.cpu.l2cache.overall_misses::total 159072 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 17978 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141086 # number of overall misses +system.cpu.l2cache.overall_misses::total 159073 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 957500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1223500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1857500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1857500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1793500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1793500 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16383348000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16383348000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2349142000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2349142000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1612524000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1612524000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382558000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16382558000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351294500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351294500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1615422500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1615422500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2349142000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17995872000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20346237500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2351294500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17997980500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20350498500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2349142000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17995872000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20346237500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7817 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 2351294500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17997980500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20350498500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11858 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 683842 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 683842 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1664795 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1664795 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2763 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 683846 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 683846 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1664945 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1664945 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2765 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2765 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 295941 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 295941 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696050 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1696050 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523812 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 523812 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7817 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 295944 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295944 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696206 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1696206 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523815 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 523815 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7814 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 4041 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1696050 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819753 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2527661 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7817 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1696206 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819759 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2527820 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 4041 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1696050 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819753 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2527661 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000895 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1696206 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819759 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2527820 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000896 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000495 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.000759 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991676 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991676 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991682 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991682 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435610 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.435610 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435599 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.435599 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010599 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023237 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023237 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000895 # miss rate for demand accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023239 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023239 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000896 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000495 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010599 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.172109 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062932 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000895 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.172107 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062929 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000896 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000495 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010599 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.172109 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062932 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.172107 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062929 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 677.919708 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 677.919708 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 654.084610 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 654.084610 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127086.436799 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127086.436799 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130682.131731 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130682.131731 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132478.146566 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132478.146566 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127082.280298 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127082.280298 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.323395 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130682.131731 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127551.595824 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 127905.838237 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130682.131731 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127551.595824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 127905.838237 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1022,31 +1019,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 81183 # number of writebacks -system.cpu.l2cache.writebacks::total 81183 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks +system.cpu.l2cache.writebacks::total 81185 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2740 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2740 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2742 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128915 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 128915 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17976 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17976 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12172 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12172 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128913 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 128913 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17978 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17978 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12173 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12173 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 17976 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141087 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 159072 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 17978 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141086 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 159073 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 17976 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141087 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 159072 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 17978 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141086 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 159073 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable @@ -1058,139 +1055,139 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 887500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1133500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 194003500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 194003500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186544500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186544500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15094198000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15094198000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2169382000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2169382000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1490804000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1490804000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093428000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093428000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171514500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171514500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1493692500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1493692500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2169382000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16585002000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18755517500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16587120500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18759768500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2169382000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16585002000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18755517500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888826500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918592500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772574000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772574000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772572500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772572500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661400500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691166500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661376500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691142500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991676 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991682 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435610 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435610 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435599 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435599 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023237 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023237 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023239 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023239 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062932 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172107 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172107 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.197080 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.197080 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68032.275711 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68032.275711 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117086.436799 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117086.436799 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120682.131731 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120682.131731 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122478.146566 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122478.146566 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.254994 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.709661 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.292435 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.292435 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.718460 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.890271 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5052537 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536723 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2287321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2287480 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801217 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1664795 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 134627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1695721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 141985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 524040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295944 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295944 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 524043 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574565 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5106210 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581942 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25654 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7688448 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215130168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96426845 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25651 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7727060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217119416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96427485 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31268 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311604445 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 175875 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2773837 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.020867 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.142939 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313594321 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175889 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2774012 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.020868 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.142944 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2715955 97.91% 97.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 57882 2.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2716123 97.91% 97.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 57889 2.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2773837 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4957294000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2774012 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4957617000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 380876 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2553146500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2553380500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1275944500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1275954500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1246,7 +1243,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46336500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1280,25 +1277,25 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186221548 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187058527 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084130 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084082 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313812613000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084130 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313812610000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084082 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067755 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067755 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1312,14 +1309,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28228376 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28228376 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4717653172 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4717653172 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28228376 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28228376 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28228376 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28228376 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4549133150 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4549133150 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1336,19 +1333,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123808.666667 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123808.666667 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130235.566807 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130235.566807 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123808.666667 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123808.666667 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 910 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.234568 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1362,14 +1359,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16828376 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16828376 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906453172 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2906453172 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16828376 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16828376 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16828376 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16828376 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736521626 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2736521626 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1378,68 +1375,67 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73808.666667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73808.666667 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.566807 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.566807 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70545 # Transaction distribution +system.membus.trans_dist::ReadResp 70548 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117373 # Transaction distribution -system.membus.trans_dist::CleanEvict 6392 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution +system.membus.trans_dist::CleanEvict 6608 # Transaction distribution system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 127158 # Transaction distribution system.membus.trans_dist::ReadExResp 127158 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30385 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546409 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655303 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 434329 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 541921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 614806 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465365 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302332 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465685 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17782485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782805 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 389997 # Request fanout histogram +system.membus.snoop_fanout::samples 390011 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 389997 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390011 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 389997 # Request fanout histogram -system.membus.reqLayer0.occupancy 90470000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390011 # Request fanout histogram +system.membus.reqLayer0.occupancy 90460500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1730500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 823068661 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823136860 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952238748 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 943248500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64113741 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1186623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index db18bd84f..e0084d588 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867052000 # Number of ticks simulated -final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783855 # Number of seconds simulated +sim_ticks 2783854535000 # Number of ticks simulated +final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 540105 # Simulator instruction rate (inst/s) -host_op_rate 657491 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10531274508 # Simulator tick rate (ticks/s) -host_mem_usage 560892 # Number of bytes of host memory used -host_seconds 264.34 # Real time elapsed on the host -sim_insts 142772879 # Number of instructions simulated -sim_ops 173803124 # Number of ops (including micro ops) simulated +host_inst_rate 1278958 # Simulator instruction rate (inst/s) +host_op_rate 1556926 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24937950041 # Simulator tick rate (ticks/s) +host_mem_usage 579412 # Number of bytes of host memory used +host_seconds 111.63 # Real time elapsed on the host +sim_insts 142771651 # Number of instructions simulated +sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 725796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4660896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 724196 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4660000 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 481216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5663620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 482816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5664516 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 11533000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 725796 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 481216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 724196 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 482816 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840512 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840576 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858036 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858100 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19769 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73331 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7544 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88509 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 189176 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138133 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 138134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142514 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142515 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 260715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1674252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 260141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1673938 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 172859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2034443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 173434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2034774 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260715 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 172859 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 173434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175660 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181918 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181955 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175660 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1680544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1680230 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 172859 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2034446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 173434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2034777 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7324772 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -116,45 +116,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5683 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5683 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5683 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5683 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5683 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 5703 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5703 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5703 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5703 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5703 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.40% 65.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1613 34.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4662 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5683 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 3075 65.68% 65.68% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1607 34.32% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4682 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5703 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5683 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4662 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5703 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4682 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4662 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10345 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10385 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15994593 # DTB read hits -system.cpu0.dtb.read_misses 4788 # DTB read misses -system.cpu0.dtb.write_hits 11285810 # DTB write hits -system.cpu0.dtb.write_misses 895 # DTB write misses +system.cpu0.dtb.read_hits 15997085 # DTB read hits +system.cpu0.dtb.read_misses 4809 # DTB read misses +system.cpu0.dtb.write_hits 11281852 # DTB write hits +system.cpu0.dtb.write_misses 894 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 394 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3234 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3232 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 773 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 770 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 200 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 15999381 # DTB read accesses -system.cpu0.dtb.write_accesses 11286705 # DTB write accesses +system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 16001894 # DTB read accesses +system.cpu0.dtb.write_accesses 11282746 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27280403 # DTB hits -system.cpu0.dtb.misses 5683 # DTB misses -system.cpu0.dtb.accesses 27286086 # DTB accesses +system.cpu0.dtb.hits 27278937 # DTB hits +system.cpu0.dtb.misses 5703 # DTB misses +system.cpu0.dtb.accesses 27284640 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -184,206 +184,206 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2611 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2611 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2611 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2611 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 2590 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2590 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2590 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2590 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2590 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1374 72.85% 72.85% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 512 27.15% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1886 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1366 72.81% 72.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 510 27.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1876 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2611 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2590 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2590 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74779098 # ITB inst hits -system.cpu0.itb.inst_misses 2611 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1876 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1876 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4466 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 74797685 # ITB inst hits +system.cpu0.itb.inst_misses 2590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2813 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 394 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1917 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1907 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74781709 # ITB inst accesses -system.cpu0.itb.hits 74779098 # DTB hits -system.cpu0.itb.misses 2611 # DTB misses -system.cpu0.itb.accesses 74781709 # DTB accesses -system.cpu0.numCycles 5536444792 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 74800275 # ITB inst accesses +system.cpu0.itb.hits 74797685 # DTB hits +system.cpu0.itb.misses 2590 # DTB misses +system.cpu0.itb.accesses 74800275 # DTB accesses +system.cpu0.numCycles 5536444787 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu0.committedInsts 72626333 # Number of instructions committed -system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5256 # Number of float alu accesses -system.cpu0.num_func_calls 8692525 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9458276 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77485858 # number of integer instructions -system.cpu0.num_fp_insts 5256 # number of float instructions -system.cpu0.num_int_register_reads 144065688 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54441738 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4098 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1160 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268855171 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31825079 # number of times the CC registers were written -system.cpu0.num_mem_refs 27911721 # number of memory refs -system.cpu0.num_load_insts 16162181 # Number of load instructions -system.cpu0.num_store_insts 11749540 # Number of store instructions -system.cpu0.num_idle_cycles 5353607317.458248 # Number of idle cycles -system.cpu0.num_busy_cycles 182837474.541752 # Number of busy cycles -system.cpu0.not_idle_fraction 0.033024 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.966976 # Percentage of idle cycles -system.cpu0.Branches 18597106 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2189 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61764727 68.82% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59660 0.07% 68.89% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4403 0.00% 68.90% # Class of executed instruction +system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed +system.cpu0.committedInsts 72639178 # Number of instructions committed +system.cpu0.committedOps 87981810 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77492203 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5289 # Number of float alu accesses +system.cpu0.num_func_calls 8694463 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9459638 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77492203 # number of integer instructions +system.cpu0.num_fp_insts 5289 # number of float instructions +system.cpu0.num_int_register_reads 144072055 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54447583 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4067 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 268879809 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31833575 # number of times the CC registers were written +system.cpu0.num_mem_refs 27909868 # number of memory refs +system.cpu0.num_load_insts 16164638 # Number of load instructions +system.cpu0.num_store_insts 11745230 # Number of store instructions +system.cpu0.num_idle_cycles 5353616276.220466 # Number of idle cycles +system.cpu0.num_busy_cycles 182828510.779535 # Number of busy cycles +system.cpu0.not_idle_fraction 0.033023 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.966977 # Percentage of idle cycles +system.cpu0.Branches 18600800 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 61776579 68.83% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59680 0.07% 68.90% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4414 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16162181 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16164638 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11745230 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89742700 # Class of executed instruction -system.cpu0.dcache.tags.replacements 819402 # number of replacements +system.cpu0.op_class::total 89752729 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819392 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597629 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53783791 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597669 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821817 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175357 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929339 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070655 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830580 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166594 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929357 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070638 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219237306 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219237306 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15302738 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14826284 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30129022 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10898497 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11441613 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186051 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209007 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395058 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235059 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222271 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 457330 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236765 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223371 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26201235 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26267897 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52469132 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26387286 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26476904 # number of overall hits -system.cpu0.dcache.overall_hits::total 52864190 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197065 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 199241 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396306 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137741 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 163937 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301678 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54401 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61672 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116073 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4662 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3967 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 219234764 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219234764 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15305281 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14823482 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30128763 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10894769 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11445022 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185755 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209286 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395041 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234992 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222324 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 457316 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236691 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223431 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 26200050 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26268504 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52468554 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26385805 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26477790 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863595 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197438 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 198880 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396318 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137575 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 164088 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54345 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61721 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 116066 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4663 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334806 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 363178 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697984 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389207 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424850 # number of overall misses -system.cpu0.dcache.overall_misses::total 814057 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15499803 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15025525 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11036238 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11605550 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240452 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270679 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511131 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239721 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226238 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236765 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223373 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26536041 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631075 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26776493 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26901754 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53678247 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012714 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013260 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 335013 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 362968 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697981 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389358 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424689 # number of overall misses +system.cpu0.dcache.overall_misses::total 814047 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502719 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15022362 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11032344 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609110 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240100 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271007 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511107 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239655 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226290 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236691 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223433 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 26535063 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631472 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26775163 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26902479 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677642 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012736 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013239 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012481 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014126 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226245 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227842 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227091 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019448 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017535 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012470 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014134 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226343 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227747 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227087 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019457 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017526 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012617 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013637 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014535 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015793 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014542 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015786 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.015165 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -393,19 +393,19 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682264 # number of writebacks -system.cpu0.dcache.writebacks::total 682264 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks +system.cpu0.dcache.writebacks::total 682241 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1699214 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145342721 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1698998 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 145341757 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127325 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536356 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888921 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110423 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121661 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542018 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id @@ -413,44 +413,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148742185 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148742185 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73936444 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71406277 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145342721 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73936444 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71406277 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145342721 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73936444 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71406277 # number of overall hits -system.cpu0.icache.overall_hits::total 145342721 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844540 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855192 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699732 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844540 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855192 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699732 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844540 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855192 # number of overall misses -system.cpu0.icache.overall_misses::total 1699732 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74780984 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261469 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74780984 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72261469 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74780984 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72261469 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011294 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011835 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011294 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011835 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011294 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011835 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 148740789 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148740789 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73955506 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71386251 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145341757 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73955506 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71386251 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145341757 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73955506 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71386251 # number of overall hits +system.cpu0.icache.overall_hits::total 145341757 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844055 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855461 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699516 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844055 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855461 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699516 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844055 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855461 # number of overall misses +system.cpu0.icache.overall_misses::total 1699516 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74799561 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72241712 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74799561 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72241712 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74799561 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72241712 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011284 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011842 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011284 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -459,8 +459,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1699214 # number of writebacks -system.cpu0.icache.writebacks::total 1699214 # number of writebacks +system.cpu0.icache.writebacks::writebacks 1698998 # number of writebacks +system.cpu0.icache.writebacks::total 1698998 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -491,45 +491,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6203 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6203 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 6203 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6203 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 6189 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6189 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 6189 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6189 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6189 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3703 73.18% 73.18% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1357 26.82% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5060 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 3697 73.27% 73.27% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1349 26.73% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5046 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6189 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6203 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6189 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5046 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5046 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11235 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15529940 # DTB read hits -system.cpu1.dtb.read_misses 5414 # DTB read misses -system.cpu1.dtb.write_hits 11838406 # DTB write hits -system.cpu1.dtb.write_misses 789 # DTB write misses +system.cpu1.dtb.read_hits 15527164 # DTB read hits +system.cpu1.dtb.read_misses 5392 # DTB read misses +system.cpu1.dtb.write_hits 11842009 # DTB write hits +system.cpu1.dtb.write_misses 797 # DTB write misses system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3183 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3188 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 909 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 922 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15535354 # DTB read accesses -system.cpu1.dtb.write_accesses 11839195 # DTB write accesses +system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 15532556 # DTB read accesses +system.cpu1.dtb.write_accesses 11842806 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27368346 # DTB hits -system.cpu1.dtb.misses 6203 # DTB misses -system.cpu1.dtb.accesses 27374549 # DTB accesses +system.cpu1.dtb.hits 27369173 # DTB hits +system.cpu1.dtb.misses 6189 # DTB misses +system.cpu1.dtb.accesses 27375362 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -559,107 +559,107 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3041 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3041 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walkWaitTime::samples 3041 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3041 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3041 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 3051 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3051 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 3051 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3051 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3051 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1721 81.53% 81.53% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 390 18.47% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2111 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1721 81.56% 81.56% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 389 18.44% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3041 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3041 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3051 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3051 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2111 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2111 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5152 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 72259358 # ITB inst hits -system.cpu1.itb.inst_misses 3041 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5161 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 72239602 # ITB inst hits +system.cpu1.itb.inst_misses 3051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2817 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2022 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72262399 # ITB inst accesses -system.cpu1.itb.hits 72259358 # DTB hits -system.cpu1.itb.misses 3041 # DTB misses -system.cpu1.itb.accesses 72262399 # DTB accesses -system.cpu1.numCycles 88040649 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 72242653 # ITB inst accesses +system.cpu1.itb.hits 72239602 # DTB hits +system.cpu1.itb.misses 3051 # DTB misses +system.cpu1.itb.accesses 72242653 # DTB accesses +system.cpu1.numCycles 88015617 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 70146546 # Number of instructions committed -system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6228 # Number of float alu accesses -system.cpu1.num_func_calls 8181374 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9272054 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75676825 # number of integer instructions -system.cpu1.num_fp_insts 6228 # number of float instructions -system.cpu1.num_int_register_reads 140994115 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52737742 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4674 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1556 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261998832 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30539220 # number of times the CC registers were written -system.cpu1.num_mem_refs 28027555 # number of memory refs -system.cpu1.num_load_insts 15693703 # Number of load instructions -system.cpu1.num_store_insts 12333852 # Number of store instructions -system.cpu1.num_idle_cycles 85384966.713327 # Number of idle cycles -system.cpu1.num_busy_cycles 2655682.286673 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030164 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969836 # Percentage of idle cycles -system.cpu1.Branches 17799875 # Number of branches fetched -system.cpu1.op_class::No_OpClass 148 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59388111 67.89% 67.89% # Class of executed instruction -system.cpu1.op_class::IntMult 57232 0.07% 67.96% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4166 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::MemRead 15693703 17.94% 85.90% # Class of executed instruction -system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Class of executed instruction +system.cpu1.committedInsts 70132473 # Number of instructions committed +system.cpu1.committedOps 85819782 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75669076 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6195 # Number of float alu accesses +system.cpu1.num_func_calls 8179499 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9270637 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75669076 # number of integer instructions +system.cpu1.num_fp_insts 6195 # number of float instructions +system.cpu1.num_int_register_reads 140985520 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52730881 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4705 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 261969734 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30530329 # number of times the CC registers were written +system.cpu1.num_mem_refs 28028748 # number of memory refs +system.cpu1.num_load_insts 15690947 # Number of load instructions +system.cpu1.num_store_insts 12337801 # Number of store instructions +system.cpu1.num_idle_cycles 85360941.513009 # Number of idle cycles +system.cpu1.num_busy_cycles 2654675.486991 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles +system.cpu1.Branches 17796178 # Number of branches fetched +system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 59375458 67.88% 67.88% # Class of executed instruction +system.cpu1.op_class::IntMult 57193 0.07% 67.95% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4155 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::MemRead 15690947 17.94% 85.89% # Class of executed instruction +system.cpu1.op_class::MemWrite 12337801 14.11% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87477212 # Class of executed instruction +system.cpu1.op_class::total 87465703 # Class of executed instruction system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -711,14 +711,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -760,27 +760,27 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 109907 # number of replacements -system.l2c.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.l2c.tags.total_refs 4528496 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65155.314985 # Cycle average of tags in use +system.l2c.tags.total_refs 4528037 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 175188 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 25.849350 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 25.846730 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48764.072075 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48764.087166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5143.224775 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4734.504525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5143.112513 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4734.411223 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4025.377664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2484.226979 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4025.485555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2484.315404 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.078479 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.072243 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.078478 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.072241 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061422 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037906 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061424 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037908 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65277 # Occupied blocks per task id @@ -792,156 +792,156 @@ system.l2c.tags.age_task_id_blocks_1024::3 10699 # system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40608233 # Number of tag accesses -system.l2c.tags.data_accesses 40608233 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4700 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits -system.l2c.ReadReq_hits::total 14441 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 682264 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 682264 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1667206 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits +system.l2c.tags.tag_accesses 40604434 # Number of tag accesses +system.l2c.tags.data_accesses 40604434 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4715 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2284 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4980 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2427 # number of ReadReq hits +system.l2c.ReadReq_hits::total 14406 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 682241 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 682241 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1666999 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72515 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78631 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151146 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 833751 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 847665 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 246350 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 259095 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4700 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2287 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833751 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 318865 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5001 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2453 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847665 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337726 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352448 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4700 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2287 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833751 # number of overall hits -system.l2c.overall_hits::cpu0.data 318865 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5001 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2453 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847665 # number of overall hits -system.l2c.overall_hits::cpu1.data 337726 # number of overall hits -system.l2c.overall_hits::total 2352448 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 72343 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78788 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151131 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 833292 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 847909 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 246688 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 258762 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 505450 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4715 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2284 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833292 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 319031 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4980 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2427 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 847909 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337550 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352188 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4715 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2284 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833292 # number of overall hits +system.l2c.overall_hits::cpu0.data 319031 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4980 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2427 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847909 # number of overall hits +system.l2c.overall_hits::cpu1.data 337550 # number of overall hits +system.l2c.overall_hits::total 2352188 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1250 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1478 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63964 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83812 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 63970 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83806 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 147776 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 10779 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 7519 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 10754 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 7544 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9778 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 5785 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9758 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 5805 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 15563 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10779 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73742 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10754 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73728 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7519 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89597 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7544 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89611 # number of demand (read+write) misses system.l2c.demand_misses::total 181645 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10779 # number of overall misses -system.l2c.overall_misses::cpu0.data 73742 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10754 # number of overall misses +system.l2c.overall_misses::cpu0.data 73728 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7519 # number of overall misses -system.l2c.overall_misses::cpu1.data 89597 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7544 # number of overall misses +system.l2c.overall_misses::cpu1.data 89611 # number of overall misses system.l2c.overall_misses::total 181645 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4705 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2288 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5003 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 14449 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 682264 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 682264 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4720 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2285 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4982 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 14414 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 682241 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 682241 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136479 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162443 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 844530 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 855184 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 256128 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 264880 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4705 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2288 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844530 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392607 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5003 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2453 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855184 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427323 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2534093 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4705 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2288 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844530 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392607 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5003 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2453 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855184 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427323 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2534093 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000554 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989699 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989960 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 136313 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162594 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 844046 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 855453 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 256446 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 264567 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4720 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2285 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844046 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392759 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4982 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855453 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427161 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2533833 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4720 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2285 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844046 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392759 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4982 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855453 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427161 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2533833 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000438 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000555 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990491 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989290 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.468673 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515947 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012763 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008792 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038176 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021840 # miss rate for ReadSharedReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.469288 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.515431 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012741 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008819 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038051 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021942 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.029871 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012763 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187827 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008792 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209670 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.071680 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012763 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187827 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008792 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209670 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.071680 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000438 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012741 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187718 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209783 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.071688 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000438 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012741 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187718 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209783 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.071688 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -950,15 +950,15 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101943 # number of writebacks -system.l2c.writebacks::total 101943 # number of writebacks +system.l2c.writebacks::writebacks 101944 # number of writebacks +system.l2c.writebacks::total 101944 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution -system.membus.trans_dist::CleanEvict 7977 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138134 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -972,17 +972,17 @@ system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506563 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 613923 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723054 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723281 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091644 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18254617 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091708 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18254681 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586201 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 434809 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram @@ -1036,47 +1036,47 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5060706 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2541063 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5060329 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540912 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 71244 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 71251 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291780 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 682264 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 129872 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 682241 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 137151 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5084714 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2574734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 311967917 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 182968 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.134877 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116074 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581970 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20766 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41562 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7760372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96321057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41532 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83124 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313986697 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 182969 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5322182 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018547 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.134917 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5223970 98.15% 98.15% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 98657 1.85% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5223474 98.15% 98.15% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 98708 1.85% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5322627 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5322182 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 5188d100d..cd3a72dfc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909671 # Number of seconds simulated -sim_ticks 2909670971500 # Number of ticks simulated -final_tick 2909670971500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909645 # Number of seconds simulated +sim_ticks 2909644861500 # Number of ticks simulated +final_tick 2909644861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 317481 # Simulator instruction rate (inst/s) -host_op_rate 382781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8214526706 # Simulator tick rate (ticks/s) -host_mem_usage 561408 # Number of bytes of host memory used -host_seconds 354.21 # Real time elapsed on the host -sim_insts 112454909 # Number of instructions simulated -sim_ops 135585028 # Number of ops (including micro ops) simulated +host_inst_rate 955579 # Simulator instruction rate (inst/s) +host_op_rate 1152126 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24724694945 # Simulator tick rate (ticks/s) +host_mem_usage 580436 # Number of bytes of host memory used +host_seconds 117.68 # Real time elapsed on the host +sim_insts 112454211 # Number of instructions simulated +sim_ops 135584166 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 523360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4648320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 522464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4660352 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 663236 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4253220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 664132 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4241316 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10089608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 523360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 663236 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10089736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 522464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 664132 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7511936 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7511872 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 8852 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7529460 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529396 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13465 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73321 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 13529 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 66473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 13543 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66287 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166623 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117374 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166625 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117373 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2213 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2168 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121755 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121754 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 179869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1597541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 179563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1601691 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 227942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1461753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 228252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1457675 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 179869 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 227942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2581713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 179563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 228252 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581714 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 3042 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 2980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2587736 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2581713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2587737 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581714 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 179869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1600584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 179563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1604733 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 227942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1464733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 228252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1460655 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6055347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166623 # Number of read requests accepted -system.physmem.writeReqs 121755 # Number of write requests accepted -system.physmem.readBursts 166623 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121755 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10657728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 7541440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10089608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7529460 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166625 # Number of read requests accepted +system.physmem.writeReqs 121754 # Number of write requests accepted +system.physmem.readBursts 166625 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121754 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10658176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5824 # Total number of bytes read from write queue +system.physmem.bytesWritten 7541376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529396 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 91 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 47111 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10080 # Per bank write bursts system.physmem.perBankRdBursts::1 9979 # Per bank write bursts system.physmem.perBankRdBursts::2 10697 # Per bank write bursts -system.physmem.perBankRdBursts::3 10654 # Per bank write bursts +system.physmem.perBankRdBursts::3 10657 # Per bank write bursts system.physmem.perBankRdBursts::4 18793 # Per bank write bursts system.physmem.perBankRdBursts::5 9662 # Per bank write bursts system.physmem.perBankRdBursts::6 9670 # Per bank write bursts -system.physmem.perBankRdBursts::7 10489 # Per bank write bursts -system.physmem.perBankRdBursts::8 9276 # Per bank write bursts +system.physmem.perBankRdBursts::7 10491 # Per bank write bursts +system.physmem.perBankRdBursts::8 9280 # Per bank write bursts system.physmem.perBankRdBursts::9 9982 # Per bank write bursts system.physmem.perBankRdBursts::10 9231 # Per bank write bursts -system.physmem.perBankRdBursts::11 8676 # Per bank write bursts +system.physmem.perBankRdBursts::11 8678 # Per bank write bursts system.physmem.perBankRdBursts::12 9823 # Per bank write bursts system.physmem.perBankRdBursts::13 10380 # Per bank write bursts -system.physmem.perBankRdBursts::14 9722 # Per bank write bursts +system.physmem.perBankRdBursts::14 9718 # Per bank write bursts system.physmem.perBankRdBursts::15 9413 # Per bank write bursts system.physmem.perBankWrBursts::0 7393 # Per bank write bursts system.physmem.perBankWrBursts::1 7263 # Per bank write bursts system.physmem.perBankWrBursts::2 8284 # Per bank write bursts -system.physmem.perBankWrBursts::3 8167 # Per bank write bursts +system.physmem.perBankWrBursts::3 8168 # Per bank write bursts system.physmem.perBankWrBursts::4 7485 # Per bank write bursts system.physmem.perBankWrBursts::5 7265 # Per bank write bursts system.physmem.perBankWrBursts::6 7108 # Per bank write bursts @@ -107,30 +107,30 @@ system.physmem.perBankWrBursts::7 7667 # Pe system.physmem.perBankWrBursts::8 7080 # Per bank write bursts system.physmem.perBankWrBursts::9 7523 # Per bank write bursts system.physmem.perBankWrBursts::10 6694 # Per bank write bursts -system.physmem.perBankWrBursts::11 6468 # Per bank write bursts +system.physmem.perBankWrBursts::11 6470 # Per bank write bursts system.physmem.perBankWrBursts::12 7527 # Per bank write bursts system.physmem.perBankWrBursts::13 7859 # Per bank write bursts -system.physmem.perBankWrBursts::14 7264 # Per bank write bursts +system.physmem.perBankWrBursts::14 7260 # Per bank write bursts system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 2909670614500 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 2909644504500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157051 # Read request sizes (log2) +system.physmem.readPktSize::6 157053 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117374 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 611 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117373 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 613 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -163,129 +163,134 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 189 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 184 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 181 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 175 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 172 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 170 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 169 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.549016 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.176876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.004841 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21372 36.47% 36.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14638 24.98% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6011 10.26% 71.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3214 5.48% 77.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2514 4.29% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1548 2.64% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1052 1.80% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1122 1.91% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7132 12.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58603 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5730 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.058290 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.635756 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5727 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.672197 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.145957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.231527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21388 36.51% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14603 24.93% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5975 10.20% 71.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3225 5.51% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2561 4.37% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1528 2.61% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1012 1.73% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1135 1.94% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7154 12.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58581 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.894255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 552.382236 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5567 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5730 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5730 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.564572 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.725438 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.838937 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 17 0.30% 0.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 9 0.16% 0.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.14% 0.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 11 0.19% 0.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4763 83.12% 83.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 132 2.30% 86.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 73 1.27% 87.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 203 3.54% 91.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 27 0.47% 91.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 153 2.67% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 54 0.94% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.03% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.23% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.40% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 95.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.12% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 171 2.98% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.10% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.42% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.05% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.19% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5730 # Writes before turning the bus around for reads -system.physmem.totQLat 1612014000 # Total ticks spent queuing -system.physmem.totMemAccLat 4734395250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832635000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9680.20 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5570 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5570 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.155117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.796345 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.496905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 17 0.31% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.16% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 8 0.14% 0.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 13 0.23% 0.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4758 85.42% 86.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 105 1.89% 88.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 66 1.18% 89.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 70 1.26% 90.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 40 0.72% 91.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.31% 91.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 48 0.86% 92.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.18% 92.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 152 2.73% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.14% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.18% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 62 1.11% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.16% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 97.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.48% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 105 1.89% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.13% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.09% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5570 # Writes before turning the bus around for reads +system.physmem.totQLat 1610742500 # Total ticks spent queuing +system.physmem.totMemAccLat 4733255000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832670000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9672.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28430.20 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28422.15 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -295,40 +300,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.26 # Average write queue length when enqueuing -system.physmem.readRowHits 136241 # Number of row buffer hits during reads -system.physmem.writeRowHits 89517 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.81 # Row buffer hit rate for reads +system.physmem.avgWrQLen 12.25 # Average write queue length when enqueuing +system.physmem.readRowHits 136266 # Number of row buffer hits during reads +system.physmem.writeRowHits 89520 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes -system.physmem.avgGap 10089780.13 # Average gap between requests -system.physmem.pageHitRate 79.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 230746320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125903250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702187200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392895360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190045312080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90312406830 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666579011000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948388462040 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.625842 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772320056250 # Time in different power states -system.physmem_0.memoryStateTime::REF 97160180000 # Time in different power states +system.physmem.avgGap 10089654.60 # Average gap between requests +system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230678280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125866125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702226200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190043786400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90291916755 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666582969500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948370345100 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.624992 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772326098500 # Time in different power states +system.physmem_0.memoryStateTime::REF 97159400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40187145000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40158524000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 212292360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 115834125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 596715600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370675440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190045312080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88507788255 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668162009750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1948010627610 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.495988 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2774979616000 # Time in different power states -system.physmem_1.memoryStateTime::REF 97160180000 # Time in different power states +system.physmem_1.actEnergy 212194080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 115780500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596731200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370662480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190043786400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88418921265 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668225948000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947984023925 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.492219 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775082980250 # Time in different power states +system.physmem_1.memoryStateTime::REF 97159400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37531027500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37402333250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -378,59 +383,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6370 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6370 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1827 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4542 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walks 6403 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6403 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1830 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4572 # Level at which table walker walks with short descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6369 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6369 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6369 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5319 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 13473.303252 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11679.114902 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7408.984019 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 3974 74.71% 74.71% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1341 25.21% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::samples 6402 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6402 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6402 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5332 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13399.287322 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11603.034588 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7407.871184 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 4008 75.17% 75.17% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1320 24.76% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5319 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5332 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 2989035968 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::mean 0.330748 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::stdev 0.470482 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 2000419000 66.93% 66.93% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::1 988616968 33.07% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 2989035968 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3517 66.13% 66.13% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1801 33.87% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5318 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6370 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 3528 66.18% 66.18% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1803 33.82% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5331 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6403 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6370 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5318 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6403 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5331 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5318 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 11688 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5331 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 11734 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12041748 # DTB read hits -system.cpu0.dtb.read_misses 5569 # DTB read misses -system.cpu0.dtb.write_hits 9609883 # DTB write hits -system.cpu0.dtb.write_misses 801 # DTB write misses +system.cpu0.dtb.read_hits 12042048 # DTB read hits +system.cpu0.dtb.read_misses 5594 # DTB read misses +system.cpu0.dtb.write_hits 9609454 # DTB write hits +system.cpu0.dtb.write_misses 809 # DTB write misses system.cpu0.dtb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 437 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3992 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3984 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 859 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 860 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12047317 # DTB read accesses -system.cpu0.dtb.write_accesses 9610684 # DTB write accesses +system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12047642 # DTB read accesses +system.cpu0.dtb.write_accesses 9610263 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21651631 # DTB hits -system.cpu0.dtb.misses 6370 # DTB misses -system.cpu0.dtb.accesses 21658001 # DTB accesses +system.cpu0.dtb.hits 21651502 # DTB hits +system.cpu0.dtb.misses 6403 # DTB misses +system.cpu0.dtb.accesses 21657905 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,131 +465,131 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3218 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3218 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 687 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2531 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3218 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3218 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3218 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2361 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 13277.424820 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11544.822386 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6544.721859 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::4096-6143 607 25.71% 25.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::10240-12287 660 27.95% 53.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::12288-14335 188 7.96% 61.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.39% 78.02% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.14% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::22528-24575 510 21.60% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-26623 6 0.25% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2361 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3203 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3203 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 686 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2517 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3203 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3203 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3203 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2349 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13262.452107 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11543.567684 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6519.168051 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::4096-6143 600 25.54% 25.54% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::10240-12287 662 28.18% 53.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::12288-14335 191 8.13% 61.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.48% 78.33% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.46% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::22528-24575 498 21.20% 99.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-26623 8 0.34% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2349 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1674 70.90% 70.90% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 687 29.10% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2361 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1663 70.80% 70.80% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 686 29.20% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2349 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3218 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3218 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3203 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3203 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2361 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2361 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5579 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56731893 # ITB inst hits -system.cpu0.itb.inst_misses 3218 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2349 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2349 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5552 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56738612 # ITB inst hits +system.cpu0.itb.inst_misses 3203 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 437 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2380 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56735111 # ITB inst accesses -system.cpu0.itb.hits 56731893 # DTB hits -system.cpu0.itb.misses 3218 # DTB misses -system.cpu0.itb.accesses 56735111 # DTB accesses -system.cpu0.numCycles 2910044257 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56741815 # ITB inst accesses +system.cpu0.itb.hits 56738612 # DTB hits +system.cpu0.itb.misses 3203 # DTB misses +system.cpu0.itb.accesses 56741815 # DTB accesses +system.cpu0.numCycles 2910043779 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3034 # number of quiesce instructions executed -system.cpu0.committedInsts 55192175 # Number of instructions committed -system.cpu0.committedOps 66601030 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58838667 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5226 # Number of float alu accesses -system.cpu0.num_func_calls 4816070 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7555391 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58838667 # number of integer instructions -system.cpu0.num_fp_insts 5226 # number of float instructions -system.cpu0.num_int_register_reads 106920418 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40489001 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3747 # number of times the floating registers were read +system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu0.committedInsts 55199902 # Number of instructions committed +system.cpu0.committedOps 66610456 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58846956 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5257 # Number of float alu accesses +system.cpu0.num_func_calls 4818664 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7556613 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58846956 # number of integer instructions +system.cpu0.num_fp_insts 5257 # number of float instructions +system.cpu0.num_int_register_reads 106933232 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40497320 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3778 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1482 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 240444662 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25665883 # number of times the CC registers were written -system.cpu0.num_mem_refs 22275144 # number of memory refs -system.cpu0.num_load_insts 12196401 # Number of load instructions -system.cpu0.num_store_insts 10078743 # Number of store instructions -system.cpu0.num_idle_cycles 2694612539.353109 # Number of idle cycles -system.cpu0.num_busy_cycles 215431717.646891 # Number of busy cycles -system.cpu0.not_idle_fraction 0.074030 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.925970 # Percentage of idle cycles -system.cpu0.Branches 12738975 # Number of branches fetched -system.cpu0.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 45781986 67.21% 67.21% # Class of executed instruction -system.cpu0.op_class::IntMult 56167 0.08% 67.29% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3968 0.01% 67.30% # Class of executed instruction +system.cpu0.num_cc_register_reads 240479401 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25666284 # number of times the CC registers were written +system.cpu0.num_mem_refs 22274939 # number of memory refs +system.cpu0.num_load_insts 12196843 # Number of load instructions +system.cpu0.num_store_insts 10078096 # Number of store instructions +system.cpu0.num_idle_cycles 2694635007.442764 # Number of idle cycles +system.cpu0.num_busy_cycles 215408771.557236 # Number of busy cycles +system.cpu0.not_idle_fraction 0.074023 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.925977 # Percentage of idle cycles +system.cpu0.Branches 12742817 # Number of branches fetched +system.cpu0.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 45792240 67.22% 67.22% # Class of executed instruction +system.cpu0.op_class::IntMult 56099 0.08% 67.30% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3963 0.01% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::MemRead 12196401 17.90% 85.20% # Class of executed instruction -system.cpu0.op_class::MemWrite 10078743 14.80% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12196843 17.90% 85.21% # Class of executed instruction +system.cpu0.op_class::MemWrite 10078096 14.79% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68117399 # Class of executed instruction -system.cpu0.dcache.tags.replacements 819062 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.702235 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43234880 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819574 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.752869 # Average number of references to valid blocks. +system.cpu0.op_class::total 68127374 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819099 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.702232 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43234609 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819611 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.750157 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.309006 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.393230 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084588 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914831 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.298558 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.403674 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084567 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914851 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id @@ -592,264 +597,264 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177106290 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177106290 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11353905 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11758208 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23112113 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9226963 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9596855 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18823818 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190234 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202489 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392723 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 213697 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 229550 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443247 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 221754 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 238460 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460214 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20580868 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21355063 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41935931 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20771102 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21557552 # number of overall hits -system.cpu0.dcache.overall_hits::total 42328654 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 199783 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 200066 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 399849 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 149794 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 148846 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298640 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58818 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59499 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118317 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10855 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11895 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22750 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 177105423 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177105423 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11354436 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11757578 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23112014 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9226475 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9597217 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18823692 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190286 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202415 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392701 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 213920 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 229309 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 221967 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 238239 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460206 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20580911 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21354795 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41935706 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20771197 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21557210 # number of overall hits +system.cpu0.dcache.overall_hits::total 42328407 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 199328 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 200534 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 399862 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 149618 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 149039 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298657 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58774 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59550 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 118324 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10841 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11919 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22760 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 349577 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 348912 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 698489 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 408395 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 408411 # number of overall misses -system.cpu0.dcache.overall_misses::total 816806 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3309369500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3172445000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6481814500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9848447000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9257158000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19105605000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 137223000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 156952000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 294175000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 348946 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 349573 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 698519 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 407720 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 409123 # number of overall misses +system.cpu0.dcache.overall_misses::total 816843 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3302461000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3180866500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6483327500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9863039500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9227377000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19090416500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 137120000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 157150000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 294270000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 164000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 13157816500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 12429603000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25587419500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 13157816500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 12429603000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25587419500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11553688 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11958274 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23511962 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9376757 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9745701 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19122458 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 249052 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 261988 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511040 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 224552 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 241445 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 465997 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 221754 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 238462 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460216 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20930445 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21703975 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42634420 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21179497 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21965963 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43145460 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017292 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016730 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017006 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015975 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015273 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.236168 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227106 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231522 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048341 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049266 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048820 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_latency::cpu0.data 13165500500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 12408243500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 25573744000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 13165500500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 12408243500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 25573744000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11553764 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11958112 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23511876 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9376093 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9746256 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19122349 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 249060 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 261965 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511025 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 224761 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 241228 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 465989 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 221967 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 238241 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460208 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 20929857 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21704368 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42634225 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21178917 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21966333 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43145250 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017252 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016770 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.017007 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015957 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015292 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015618 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235983 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227320 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231542 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048233 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049410 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048842 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000008 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016702 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016076 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016383 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019283 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.018593 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018931 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16564.820330 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15856.992193 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16210.655773 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65746.605338 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 62192.857047 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 63975.371685 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12641.455550 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13194.787726 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12930.769231 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016672 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016106 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016384 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019251 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.018625 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018932 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16567.973391 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15861.981011 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16213.912550 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65921.476694 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 61912.499413 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 63920.874113 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12648.279679 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13184.830942 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12929.261863 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37639.251152 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35623.890838 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36632.530362 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32218.358452 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30434.055400 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31326.189450 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37729.334911 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35495.428709 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36611.379218 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32290.543756 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30328.882757 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31308.028593 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 148 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6.727273 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 683867 # number of writebacks -system.cpu0.dcache.writebacks::total 683867 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 471 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 454 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 925 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7013 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7211 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14224 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 471 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 454 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 925 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 471 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 454 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 925 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 199312 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199612 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 398924 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 149794 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 148846 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298640 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57717 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58554 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 116271 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3842 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4684 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 683901 # number of writebacks +system.cpu0.dcache.writebacks::total 683901 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 477 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 439 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 916 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7004 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7232 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14236 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 477 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 916 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 477 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 439 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 916 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 198851 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 200095 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 398946 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 149618 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 149039 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298657 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57662 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58611 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116273 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3837 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4687 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8524 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 349106 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 348458 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 697564 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 406823 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 407012 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 813835 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14993 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16145 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.demand_mshr_misses::cpu0.data 348469 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 349134 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 697603 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 406131 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 407745 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 813876 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15000 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16138 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 13371 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14218 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 13390 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14199 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 28364 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30363 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 28390 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30337 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3093759000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2959743000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6053502000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9698653000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9108312000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18806965000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 795616000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 818334500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1613950500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 52173500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63283500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 115457000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3086715500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2967879500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6054595000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9713421500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9078338000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18791759500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 797262500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 818412000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615674500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 52113500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63305500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 115419000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 162000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12792412000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 12068055000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24860467000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13588028000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12886389500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26474417500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3047137000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3231000000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278137000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2491876500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2598064000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089940500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5539013500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5829064000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368077500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017251 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016692 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016967 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015975 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015273 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231747 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223499 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227518 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017110 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019400 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018296 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12800137000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 12046217500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24846354500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13597399500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12864629500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26462029000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3048418500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3229696000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278114500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2495078000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2594854500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089932500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5543496500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5824550500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368047000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017211 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016733 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016968 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015292 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015618 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231519 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223736 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227529 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017071 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019430 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018292 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016679 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016055 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016362 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019208 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018529 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.191338 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14827.480312 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15174.574606 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64746.605338 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61192.857047 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62975.371685 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13784.777449 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13975.723264 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13880.937637 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13579.776158 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13510.567891 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.754633 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016649 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016086 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016363 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019176 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018562 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018864 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.755732 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14832.352133 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15176.477518 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64921.476694 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60912.499413 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62920.874113 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13826.480178 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13963.453959 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13895.526046 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13581.834767 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13506.614039 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.473956 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36643.346147 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34632.739096 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.976495 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33400.343638 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31660.957171 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.448432 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203237.310745 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200123.877361 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.000835 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186364.258470 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182730.623154 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.663344 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195283.228741 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191979.185193 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.974032 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36732.498443 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34503.134899 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35616.754085 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33480.329007 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31550.673828 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32513.588065 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203227.900000 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200129.879787 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.278245 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186338.909634 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182749.102049 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.373373 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195262.293061 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191994.940172 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.454680 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1695832 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.436658 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113855734 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1696344 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.118305 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1695677 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.436645 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113855199 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1696189 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.124123 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 29075840500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 60.007721 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.428938 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117203 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879744 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 59.966796 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.469848 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117123 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879824 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id @@ -857,62 +862,62 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117248434 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117248434 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 55890585 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 57965149 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113855734 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 55890585 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 57965149 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113855734 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 55890585 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 57965149 # number of overall hits -system.cpu0.icache.overall_hits::total 113855734 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 841308 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855042 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1696350 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 841308 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855042 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1696350 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 841308 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855042 # number of overall misses -system.cpu0.icache.overall_misses::total 1696350 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11907607000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12366012000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 24273619000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11907607000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 12366012000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 24273619000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11907607000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 12366012000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 24273619000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 56731893 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 58820191 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115552084 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 56731893 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 58820191 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115552084 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 56731893 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 58820191 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115552084 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014830 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014537 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014680 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014830 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014537 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014680 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014830 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014537 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014680 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14153.683312 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14462.461493 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.322369 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14153.683312 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14462.461493 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14309.322369 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14153.683312 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14462.461493 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14309.322369 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117247589 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117247589 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 55898438 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 57956761 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113855199 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 55898438 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 57956761 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113855199 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 55898438 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 57956761 # number of overall hits +system.cpu0.icache.overall_hits::total 113855199 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 840174 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 856021 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1696195 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 840174 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 856021 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1696195 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 840174 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 856021 # number of overall misses +system.cpu0.icache.overall_misses::total 1696195 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11888847500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12382350500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 24271198000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11888847500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 12382350500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 24271198000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11888847500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 12382350500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 24271198000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 56738612 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 58812782 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115551394 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 56738612 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 58812782 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115551394 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 56738612 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 58812782 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115551394 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014808 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014555 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014679 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014808 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014555 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014808 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014555 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14150.458715 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14465.007868 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.202657 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14150.458715 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14465.007868 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14309.202657 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14150.458715 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14465.007868 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14309.202657 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -921,56 +926,56 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1695832 # number of writebacks -system.cpu0.icache.writebacks::total 1695832 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 841308 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 855042 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1696350 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 841308 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 855042 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1696350 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 841308 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 855042 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1696350 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1695677 # number of writebacks +system.cpu0.icache.writebacks::total 1695677 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 840174 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 856021 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1696195 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 840174 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 856021 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1696195 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 840174 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 856021 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1696195 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11066299000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11510970000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22577269000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11066299000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11510970000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22577269000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11066299000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11510970000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22577269000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11048673500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11526329500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22575003000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11048673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11526329500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22575003000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11048673500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11526329500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22575003000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 713903000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 428990000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1142893000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 713903000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 428990000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1142893000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014830 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014537 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014680 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014830 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014537 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014680 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014830 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014537 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014680 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.322369 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.322369 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.322369 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014808 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014555 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014808 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014555 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014808 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014555 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13150.458715 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13465.007868 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.202657 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13150.458715 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13465.007868 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.202657 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13150.458715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13465.007868 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.202657 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency @@ -1007,54 +1012,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6967 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6967 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2209 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4758 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6967 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6967 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6967 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5854 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13310.386061 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11595.564813 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7355.876792 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 5853 99.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 6953 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6953 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2221 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4731 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 6952 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6952 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6952 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5860 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13274.317406 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11562.470731 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7349.012526 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 5859 99.98% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5854 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1639416500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1639416500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1639416500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3666 62.62% 62.62% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 2188 37.38% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5854 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6967 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 5860 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 292297068 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean -4.609996 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1639785500 561.00% 561.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1347488432 -461.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 292297068 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3658 62.43% 62.43% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 2201 37.57% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5859 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6953 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6967 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6953 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5859 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5854 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12821 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5859 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12812 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12477838 # DTB read hits -system.cpu1.dtb.read_misses 5947 # DTB read misses -system.cpu1.dtb.write_hits 9996447 # DTB write hits -system.cpu1.dtb.write_misses 1020 # DTB write misses +system.cpu1.dtb.read_hits 12477429 # DTB read hits +system.cpu1.dtb.read_misses 5926 # DTB read misses +system.cpu1.dtb.write_hits 9996759 # DTB write hits +system.cpu1.dtb.write_misses 1027 # DTB write misses system.cpu1.dtb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 480 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4688 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4677 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 911 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 918 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12483785 # DTB read accesses -system.cpu1.dtb.write_accesses 9997467 # DTB write accesses +system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12483355 # DTB read accesses +system.cpu1.dtb.write_accesses 9997786 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22474285 # DTB hits -system.cpu1.dtb.misses 6967 # DTB misses -system.cpu1.dtb.accesses 22481252 # DTB accesses +system.cpu1.dtb.hits 22474188 # DTB hits +system.cpu1.dtb.misses 6953 # DTB misses +system.cpu1.dtb.accesses 22481141 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1084,85 +1092,85 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3507 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3507 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 840 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2667 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3507 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3507 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3507 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2709 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13994.462901 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12131.377414 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7198.145608 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1959 72.31% 72.31% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 749 27.65% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 3501 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3501 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 842 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2659 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3501 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3501 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3501 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2700 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13966.111111 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12105.021463 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7193.126612 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1956 72.44% 72.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 743 27.52% 99.96% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2709 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2700 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1869 68.99% 68.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 840 31.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2709 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1858 68.81% 68.81% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 842 31.19% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2700 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3507 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3507 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3501 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3501 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2709 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2709 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 6216 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 58820191 # ITB inst hits -system.cpu1.itb.inst_misses 3507 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2700 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2700 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6201 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58812782 # ITB inst hits +system.cpu1.itb.inst_misses 3501 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 480 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2713 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2701 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 58823698 # ITB inst accesses -system.cpu1.itb.hits 58820191 # DTB hits -system.cpu1.itb.misses 3507 # DTB misses -system.cpu1.itb.accesses 58823698 # DTB accesses -system.cpu1.numCycles 2909297686 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58816283 # ITB inst accesses +system.cpu1.itb.hits 58812782 # DTB hits +system.cpu1.itb.misses 3501 # DTB misses +system.cpu1.itb.accesses 58816283 # DTB accesses +system.cpu1.numCycles 2909245944 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 57262734 # Number of instructions committed -system.cpu1.committedOps 68983998 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 61052130 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5870 # Number of float alu accesses -system.cpu1.num_func_calls 5075478 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7674901 # number of instructions that are conditional controls -system.cpu1.num_int_insts 61052130 # number of integer instructions -system.cpu1.num_fp_insts 5870 # number of float instructions -system.cpu1.num_int_register_reads 111137302 # number of times the integer registers were read -system.cpu1.num_int_register_writes 42154976 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4637 # number of times the floating registers were read +system.cpu1.committedInsts 57254309 # Number of instructions committed +system.cpu1.committedOps 68973710 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 61043070 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5904 # Number of float alu accesses +system.cpu1.num_func_calls 5072826 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7673629 # number of instructions that are conditional controls +system.cpu1.num_int_insts 61043070 # number of integer instructions +system.cpu1.num_fp_insts 5904 # number of float instructions +system.cpu1.num_int_register_reads 111123439 # number of times the integer registers were read +system.cpu1.num_int_register_writes 42146017 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4671 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1234 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 249286409 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26228170 # number of times the CC registers were written -system.cpu1.num_mem_refs 23131429 # number of memory refs -system.cpu1.num_load_insts 12645834 # Number of load instructions -system.cpu1.num_store_insts 10485595 # Number of store instructions -system.cpu1.num_idle_cycles 2689887383.006891 # Number of idle cycles -system.cpu1.num_busy_cycles 219410302.993109 # Number of busy cycles -system.cpu1.not_idle_fraction 0.075417 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.924583 # Percentage of idle cycles -system.cpu1.Branches 13176890 # Number of branches fetched -system.cpu1.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 47391308 67.14% 67.14% # Class of executed instruction -system.cpu1.op_class::IntMult 58256 0.08% 67.22% # Class of executed instruction +system.cpu1.num_cc_register_reads 249248543 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26227592 # number of times the CC registers were written +system.cpu1.num_mem_refs 23131346 # number of memory refs +system.cpu1.num_load_insts 12645224 # Number of load instructions +system.cpu1.num_store_insts 10486122 # Number of store instructions +system.cpu1.num_idle_cycles 2689856281.302534 # Number of idle cycles +system.cpu1.num_busy_cycles 219389662.697466 # Number of busy cycles +system.cpu1.not_idle_fraction 0.075411 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.924589 # Percentage of idle cycles +system.cpu1.Branches 13172935 # Number of branches fetched +system.cpu1.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 47380499 67.13% 67.14% # Class of executed instruction +system.cpu1.op_class::IntMult 58319 0.08% 67.22% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction @@ -1186,15 +1194,15 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4483 0.01% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4490 0.01% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::MemRead 12645834 17.92% 85.15% # Class of executed instruction -system.cpu1.op_class::MemWrite 10485595 14.85% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12645224 17.92% 85.14% # Class of executed instruction +system.cpu1.op_class::MemWrite 10486122 14.86% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 70587679 # Class of executed instruction +system.cpu1.op_class::total 70576858 # Class of executed instruction system.iobus.trans_dist::ReadReq 30177 # Transaction distribution system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1245,7 +1253,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46333000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1279,25 +1287,25 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6288000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36457000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186225545 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187070020 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084397 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084263 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313834390000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084397 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067775 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067775 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313834387000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084263 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067766 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067766 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1311,14 +1319,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28184876 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28184876 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4715128669 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4715128669 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28184876 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28184876 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28184876 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28184876 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28181877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28181877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4548907143 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4548907143 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28181877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28181877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28181877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28181877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1335,19 +1343,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123617.877193 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123617.877193 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130165.875359 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130165.875359 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123617.877193 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123617.877193 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123617.877193 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123617.877193 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 572 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123604.723684 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123604.723684 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125577.162737 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125577.162737 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123604.723684 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123604.723684 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123604.723684 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123604.723684 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 60 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.533333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1361,14 +1369,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16784876 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16784876 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2903928669 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2903928669 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16784876 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16784876 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16784876 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16784876 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16781877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16781877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736290629 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2736290629 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16781877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16781877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16781877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16781877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1377,266 +1385,266 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73617.877193 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73617.877193 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80165.875359 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80165.875359 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73617.877193 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73617.877193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73617.877193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73617.877193 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73604.723684 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73604.723684 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75538.058442 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75538.058442 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73604.723684 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73604.723684 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73604.723684 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73604.723684 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 87560 # number of replacements -system.l2c.tags.tagsinuse 64865.201521 # Cycle average of tags in use -system.l2c.tags.total_refs 4551354 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 152795 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.787323 # Average number of references to valid blocks. +system.l2c.tags.replacements 87562 # number of replacements +system.l2c.tags.tagsinuse 64865.213908 # Cycle average of tags in use +system.l2c.tags.total_refs 4551019 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 152797 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.784741 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50199.128097 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905025 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4090.007642 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2504.647366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838092 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 50199.163746 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905024 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4089.871618 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2504.674114 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838098 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000605 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5610.818089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2455.856604 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5610.944787 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2455.815915 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062409 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062406 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.038218 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.085614 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.085616 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.037473 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65231 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6852 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56199 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56202 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.995346 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40566832 # Number of tag accesses -system.l2c.tags.data_accesses 40566832 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5848 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3044 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6379 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3501 # number of ReadReq hits -system.l2c.ReadReq_hits::total 18772 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 683867 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 683867 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1665046 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1665046 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 10 # number of UpgradeReq hits +system.l2c.tags.tag_accesses 40564313 # Number of tag accesses +system.l2c.tags.data_accesses 40564313 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5816 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6360 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3489 # number of ReadReq hits +system.l2c.ReadReq_hits::total 18690 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 683901 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 683901 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1664900 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1664900 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 81302 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 85662 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166964 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 833466 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 844870 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1678336 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 254311 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 257239 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 511550 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5848 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3044 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833466 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 335613 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6379 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3501 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 844870 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 342901 # number of demand (read+write) hits -system.l2c.demand_hits::total 2375622 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5848 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3044 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833466 # number of overall hits -system.l2c.overall_hits::cpu0.data 335613 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6379 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3501 # number of overall hits -system.l2c.overall_hits::cpu1.inst 844870 # number of overall hits -system.l2c.overall_hits::cpu1.data 342901 # number of overall hits -system.l2c.overall_hits::total 2375622 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 80918 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 86062 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 166980 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 832345 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 845838 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1678183 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 253790 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 257782 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 511572 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5816 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3025 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 832345 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 334708 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6360 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3489 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 845838 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 343844 # number of demand (read+write) hits +system.l2c.demand_hits::total 2375425 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5816 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3025 # number of overall hits +system.l2c.overall_hits::cpu0.inst 832345 # number of overall hits +system.l2c.overall_hits::cpu0.data 334708 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6360 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3489 # number of overall hits +system.l2c.overall_hits::cpu1.inst 845838 # number of overall hits +system.l2c.overall_hits::cpu1.data 343844 # number of overall hits +system.l2c.overall_hits::total 2375425 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1368 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1372 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2740 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1389 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1353 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67111 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 61802 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128913 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 7825 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 10154 # number of ReadCleanReq misses +system.l2c.ReadExReq_misses::cpu0.data 67296 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 61616 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 128912 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 7811 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 10168 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 17979 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 6560 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 5611 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 12171 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7825 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73671 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7811 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73856 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10154 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 67413 # number of demand (read+write) misses -system.l2c.demand_misses::total 159071 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 10168 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 67227 # number of demand (read+write) misses +system.l2c.demand_misses::total 159070 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7825 # number of overall misses -system.l2c.overall_misses::cpu0.data 73671 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7811 # number of overall misses +system.l2c.overall_misses::cpu0.data 73856 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 10154 # number of overall misses -system.l2c.overall_misses::cpu1.data 67413 # number of overall misses -system.l2c.overall_misses::total 159071 # number of overall misses +system.l2c.overall_misses::cpu1.inst 10168 # number of overall misses +system.l2c.overall_misses::cpu1.data 67227 # number of overall misses +system.l2c.overall_misses::total 159070 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 530500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 398500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 133000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 1062000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1048500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 808500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1857000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1012500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 780000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1792500 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8507840500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 7872807000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 16380647500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1024152500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 1327263000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 2351415500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 871431000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 737412500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1608843500 # number of ReadSharedReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8529037500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 7843663000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 16372700500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1020054500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 1330939500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 2350994000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 872232500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 739124500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1611357000 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 530500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1024152500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 9379271500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1020054500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 9401270000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 398500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 133000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1327263000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 8610219500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20341968500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 1330939500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 8582787500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20336113500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 530500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1024152500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 9379271500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1020054500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 9401270000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 398500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 133000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1327263000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 8610219500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20341968500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 5852 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3044 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 6382 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3502 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 18780 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 683867 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 683867 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1665046 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1665046 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1381 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1382 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 1330939500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 8582787500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20336113500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5820 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3025 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 6363 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3490 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 18698 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 683901 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 683901 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1664900 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1664900 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1404 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1361 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2765 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 148413 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 147464 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295877 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 841291 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 855024 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1696315 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 260871 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 262850 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 523721 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 5852 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3044 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 841291 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 409284 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 6382 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3502 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855024 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 410314 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2534693 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 5852 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3044 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 841291 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 409284 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 6382 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3502 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855024 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 410314 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2534693 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000684 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000470 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000286 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990587 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992764 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991676 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 148214 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 147678 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295892 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 840156 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 856006 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1696162 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 260350 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 263393 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 523743 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5820 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3025 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 840156 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 408564 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 6363 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3490 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 856006 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 411071 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2534495 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5820 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3025 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 840156 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 408564 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 6363 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3490 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 856006 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 411071 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2534495 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000687 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000287 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000428 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989316 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.994122 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991682 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.452191 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.419099 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.435698 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009301 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011876 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010599 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.025147 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021347 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.023239 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000684 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009301 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.180000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000470 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000286 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011876 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.164296 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.062758 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000684 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009301 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.180000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000470 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000286 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011876 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.164296 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.062758 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.454046 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.417232 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.435672 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009297 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011878 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010600 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.025197 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021303 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.023238 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000687 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009297 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.180770 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000287 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011878 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.163541 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.062762 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000687 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009297 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.180770 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000287 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011878 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.163541 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.062762 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 132625 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 133000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 132750 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 766.447368 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 589.285714 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 677.737226 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 728.941685 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 576.496674 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 653.719912 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126772.667670 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127387.576454 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 127067.460225 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130882.108626 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130713.314950 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 130786.779020 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132840.091463 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131422.651934 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 132186.632158 # average ReadSharedReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126739.144971 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127299.126850 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 127006.799212 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130592.049674 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130894.915421 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 130763.335002 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132962.271341 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131727.766886 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 132393.147646 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 132625 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 130882.108626 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 127312.938605 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 130592.049674 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 127291.892331 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 130713.314950 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 127723.428716 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 127879.805244 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 130894.915421 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 127668.756601 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 127843.801471 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 132625 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 130882.108626 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 127312.938605 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 130592.049674 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 127291.892331 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 130713.314950 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 127723.428716 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 127879.805244 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 130894.915421 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 127668.756601 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 127843.801471 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1645,237 +1653,236 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81184 # number of writebacks -system.l2c.writebacks::total 81184 # number of writebacks +system.l2c.writebacks::writebacks 81183 # number of writebacks +system.l2c.writebacks::total 81183 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 8 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1368 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1372 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2740 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1389 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1353 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67111 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 61802 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 128913 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 7825 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10154 # number of ReadCleanReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 67296 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 61616 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 128912 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 7811 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10168 # number of ReadCleanReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::total 17979 # number of ReadCleanReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.data 6560 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.data 5611 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::total 12171 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7825 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 73671 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7811 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 73856 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 10154 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 67413 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 159071 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 10168 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 67227 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 159070 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7825 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 73671 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 7811 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 73856 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 10154 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 67413 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 159071 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 10168 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 67227 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 159070 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14993 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15000 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16145 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16138 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 13371 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14218 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 13390 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14199 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 28364 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 28390 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 30363 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 30337 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 490500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 368500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 123000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 982000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 96874500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 97146000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 194020500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 94515000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 92030500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 186545500 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 139000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7836730500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 7254787000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 15091517500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 945902500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 1225723000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 2171625500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 805831000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 681302500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 1487133500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7856077500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 7227503000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 15083580500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 941944500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 1229259500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 2171204000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 806632500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 683014500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1489647000 # number of ReadSharedReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 490500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 945902500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 8642561500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 941944500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 8662710000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 368500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 123000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 1225723000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 7936089500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 18751258500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 1229259500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 7910517500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 18745413500 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 490500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 945902500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 8642561500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 941944500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 8662710000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 368500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 123000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 1225723000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 7936089500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 18751258500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 1229259500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 7910517500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 18745413500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 643340500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2859676500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2860870000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 386777500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3029132000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6918926500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2338041000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2434495500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4772536500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3027916000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6918904000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2341022000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2431506500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4772528500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 643340500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5197717500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5201892000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 386777500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5463627500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11691463000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.000426 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990587 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992764 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5459422500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11691432500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000428 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989316 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.994122 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.452191 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.419099 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.435698 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025147 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021347 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023239 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.180000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.164296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062758 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.180000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.164296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062758 # mshr miss rate for overall accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.454046 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.417232 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.435672 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011878 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010600 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025197 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021303 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023238 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.180770 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011878 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.163541 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062762 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.180770 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011878 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.163541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062762 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 122750 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70814.692982 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70806.122449 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70810.401460 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68045.356371 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68019.586105 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68032.640408 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116772.667670 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117387.576454 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117067.460225 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120786.779020 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122840.091463 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121422.651934 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122186.632158 # average ReadSharedReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116739.144971 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117299.126850 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117006.799212 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120763.335002 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122962.271341 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121727.766886 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122393.147646 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117312.938605 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117291.892331 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117723.428716 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 117879.805244 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117668.756601 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 117843.801471 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117312.938605 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117291.892331 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117723.428716 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 117879.805244 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117668.756601 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 117843.801471 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190734.109251 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190724.666667 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187620.439765 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172284.026394 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174859.098048 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171226.297651 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.933198 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187626.471682 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172283.466135 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174833.607170 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171244.911613 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.643227 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183250.511211 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183229.728778 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179943.599117 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 172570.266720 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179959.208228 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 172569.816529 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution system.membus.trans_dist::ReadResp 70546 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117374 # Transaction distribution -system.membus.trans_dist::CleanEvict 6389 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4498 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117373 # Transaction distribution +system.membus.trans_dist::CleanEvict 6607 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4500 # Transaction distribution -system.membus.trans_dist::ReadExReq 127155 # Transaction distribution -system.membus.trans_dist::ReadExResp 127155 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 127157 # Transaction distribution +system.membus.trans_dist::ReadExResp 127157 # Transaction distribution system.membus.trans_dist::ReadSharedReq 30386 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438813 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 546405 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655299 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 434320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 541912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 614797 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15301948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15465301 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15302012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15465365 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17782421 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782485 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 389996 # Request fanout histogram +system.membus.snoop_fanout::samples 390010 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 389996 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390010 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 389996 # Request fanout histogram -system.membus.reqLayer0.occupancy 90452500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390010 # Request fanout histogram +system.membus.reqLayer0.occupancy 90443000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1723000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1721000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 823109916 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823181865 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952195249 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 943214000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64063181 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1187123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -1918,60 +1925,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5053996 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2538070 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 38133 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5053855 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2538047 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 74719 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2295003 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 74697 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2294848 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 801245 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1665046 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 134452 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 801289 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1695677 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 141805 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295877 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295877 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1696350 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 523949 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295892 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295892 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1696195 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 523971 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5075755 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2574108 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18469 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34870 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7703202 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215163192 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96418525 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 311656837 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 176461 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2781455 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021257 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144239 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5106078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581570 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18395 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34840 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7740883 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217113784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96423069 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26060 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48732 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313611645 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176532 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2781330 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021292 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144357 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2722330 97.87% 97.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 59125 2.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2722109 97.87% 97.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 59221 2.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2781455 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4961451000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2781330 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4961202000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 380876 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2553547000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2553314500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1275712000 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1275768500 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11923000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11880000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22636000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22657000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |