diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
5 files changed, 1530 insertions, 1530 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 5fe42fc21..839e0acab 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -215,7 +215,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index bc1e2b029..9811be55f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -198,7 +198,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index ebe1b98fa..13c85b6d1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.182882 # Number of seconds simulated -sim_ticks 1182882156500 # Number of ticks simulated -final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.183003 # Number of seconds simulated +sim_ticks 1183003114000 # Number of ticks simulated +final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 497131 # Simulator instruction rate (inst/s) -host_op_rate 633435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9569364300 # Simulator tick rate (ticks/s) -host_mem_usage 452888 # Number of bytes of host memory used -host_seconds 123.61 # Real time elapsed on the host -sim_insts 61450993 # Number of instructions simulated -sim_ops 78299715 # Number of ops (including micro ops) simulated +host_inst_rate 673901 # Simulator instruction rate (inst/s) +host_op_rate 858757 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12970235901 # Simulator tick rate (ticks/s) +host_mem_usage 408748 # Number of bytes of host memory used +host_seconds 91.21 # Real time elapsed on the host +sim_insts 61465824 # Number of instructions simulated +sim_ops 78326377 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory -system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory +system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory +system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654451 # Total number of read requests seen -system.physmem.writeReqs 821128 # Total number of write requests seen -system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425884864 # Total number of bytes read from memory -system.physmem.bytesWritten 52552192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654023 # Total number of read requests seen +system.physmem.writeReqs 820738 # Total number of write requests seen +system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425857472 # Total number of bytes read from memory +system.physmem.bytesWritten 52527232 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182877668000 # Total gap between requests +system.physmem.totGap 1182998675500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159562 # Categorize read packet sizes +system.physmem.readPktSize::6 159134 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,7 +125,7 @@ system.physmem.writePktSize::2 756836 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 64292 # categorize write packet sizes +system.physmem.writePktSize::6 63902 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,26 +134,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 574129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 411417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 411845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 427327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1182593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1193140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2312606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 14611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 14622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 14563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2767 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -170,60 +170,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35701 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044095 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019755 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017528 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.761692 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.885452 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.827456 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.713750 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.855288 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770724 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573338 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.546627 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.558553 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106316 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106316 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40610.018244 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48571.194566 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42133.820428 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.341055 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.735761 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.114496 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.758319 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -656,27 +656,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070111 # DTB read hits -system.cpu0.dtb.read_misses 3764 # DTB read misses -system.cpu0.dtb.write_hits 5656042 # DTB write hits -system.cpu0.dtb.write_misses 804 # DTB write misses +system.cpu0.dtb.read_hits 5883553 # DTB read hits +system.cpu0.dtb.read_misses 2148 # DTB read misses +system.cpu0.dtb.write_hits 4842455 # DTB write hits +system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073875 # DTB read accesses -system.cpu0.dtb.write_accesses 5656846 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 5885701 # DTB read accesses +system.cpu0.dtb.write_accesses 4842860 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12726153 # DTB hits -system.cpu0.dtb.misses 4568 # DTB misses -system.cpu0.dtb.accesses 12730721 # DTB accesses -system.cpu0.itb.inst_hits 29570310 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.dtb.hits 10726008 # DTB hits +system.cpu0.dtb.misses 2553 # DTB misses +system.cpu0.dtb.accesses 10728561 # DTB accesses +system.cpu0.itb.inst_hits 24779849 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -685,86 +685,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses -system.cpu0.itb.hits 29570310 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29572515 # DTB accesses -system.cpu0.numCycles 2365764313 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses +system.cpu0.itb.hits 24779849 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 24781199 # DTB accesses +system.cpu0.numCycles 2364565551 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28872367 # Number of instructions committed -system.cpu0.committedOps 37211047 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33098187 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241715 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373222 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33098187 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190047206 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36225366 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13394441 # number of memory refs -system.cpu0.num_load_insts 7407672 # Number of load instructions -system.cpu0.num_store_insts 5986769 # Number of store instructions -system.cpu0.num_idle_cycles 2224997657.358119 # Number of idle cycles -system.cpu0.num_busy_cycles 140766655.641881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059502 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940498 # Percentage of idle cycles +system.cpu0.committedInsts 24381823 # Number of instructions committed +system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28075203 # 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Number of idle cycles +system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed -system.cpu0.icache.replacements 425445 # number of replacements -system.cpu0.icache.tagsinuse 509.616014 # Cycle average of tags in use -system.cpu0.icache.total_refs 29144335 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 425957 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.420838 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.616014 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995344 # 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Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.889934 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 452.516720 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.883822 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.883822 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5477555 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5477555 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4571792 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4571792 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129360 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 129360 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130225 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 130225 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10049347 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10049347 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10049347 # number of overall hits +system.cpu0.dcache.overall_hits::total 10049347 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 191756 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 191756 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 126522 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 126522 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8645 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8645 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7703 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7703 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 318278 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 318278 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 318278 # number of overall misses +system.cpu0.dcache.overall_misses::total 318278 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2678719000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 2678719000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3810145000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 3810145000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 78655500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 78655500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45606000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45606000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 6488864000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 6488864000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 6488864000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 6488864000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5669311 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5669311 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4698314 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4698314 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138005 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 138005 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137928 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 137928 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10367625 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10367625 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10367625 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10367625 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033824 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033824 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062643 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062643 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.055848 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.055848 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030699 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030699 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030699 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030699 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13969.414256 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13969.414256 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30114.486018 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30114.486018 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9098.380567 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9098.380567 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5920.550435 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5920.550435 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20387.409749 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 20387.409749 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,66 +895,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306206 # number of writebacks -system.cpu0.dcache.writebacks::total 306206 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227863 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227863 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141515 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141515 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9301 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9301 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369378 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369378 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369378 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369378 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2674386000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2674386000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3820765500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3820765500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69382000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69382000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29532500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks +system.cpu0.dcache.writebacks::total 257540 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6495151500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6495151500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6495151500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6495151500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13561363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13561363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128479500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128479500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14689842500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059151 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059151 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047654 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047654 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029981 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029981 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -964,27 +964,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8310545 # DTB read hits -system.cpu1.dtb.read_misses 3643 # DTB read misses -system.cpu1.dtb.write_hits 5827351 # DTB write hits -system.cpu1.dtb.write_misses 1434 # DTB write misses +system.cpu1.dtb.read_hits 9504194 # DTB read hits +system.cpu1.dtb.read_misses 5263 # DTB read misses +system.cpu1.dtb.write_hits 6646220 # DTB write hits +system.cpu1.dtb.write_misses 1833 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8314188 # DTB read accesses -system.cpu1.dtb.write_accesses 5828785 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 9509457 # DTB read accesses +system.cpu1.dtb.write_accesses 6648053 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14137896 # DTB hits -system.cpu1.dtb.misses 5077 # DTB misses -system.cpu1.dtb.accesses 14142973 # DTB accesses -system.cpu1.itb.inst_hits 33189113 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.dtb.hits 16150414 # DTB hits +system.cpu1.dtb.misses 7096 # DTB misses +system.cpu1.dtb.accesses 16157510 # DTB accesses +system.cpu1.itb.inst_hits 37994467 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -993,86 +993,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses -system.cpu1.itb.hits 33189113 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33191284 # DTB accesses -system.cpu1.numCycles 2364318212 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses +system.cpu1.itb.hits 37994467 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 37997484 # DTB accesses +system.cpu1.numCycles 2366006228 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32578626 # Number of instructions committed -system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962009 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732639 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37313171 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213663418 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39454743 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14675641 # number of memory refs -system.cpu1.num_load_insts 8632449 # Number of load instructions -system.cpu1.num_store_insts 6043192 # Number of store instructions -system.cpu1.num_idle_cycles 1868258895.232782 # Number of idle cycles -system.cpu1.num_busy_cycles 496059316.767218 # Number of busy cycles -system.cpu1.not_idle_fraction 0.209811 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.790189 # Percentage of idle cycles +system.cpu1.committedInsts 37084001 # Number of instructions committed +system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1133542 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls +system.cpu1.num_int_insts 42360540 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read +system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 16764021 # number of memory refs +system.cpu1.num_load_insts 9884261 # Number of load instructions +system.cpu1.num_store_insts 6879760 # Number of store instructions +system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles +system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles +system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed -system.cpu1.icache.replacements 469194 # number of replacements -system.cpu1.icache.tagsinuse 478.783096 # Cycle average of tags in use -system.cpu1.icache.total_refs 32719403 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469706 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.659325 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92023963500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.783096 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32719403 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32719403 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32719403 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32719403 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32719403 # number of overall hits -system.cpu1.icache.overall_hits::total 32719403 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469706 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469706 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469706 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469706 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469706 # number of overall misses -system.cpu1.icache.overall_misses::total 469706 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6343605000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6343605000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6343605000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6343605000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6343605000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6343605000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189109 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33189109 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33189109 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33189109 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33189109 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33189109 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014152 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014152 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014152 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014152 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014152 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014152 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.480024 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.480024 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13505.480024 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13505.480024 # average overall miss latency +system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed +system.cpu1.icache.replacements 540342 # number of replacements +system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use +system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits +system.cpu1.icache.overall_hits::total 37453609 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses +system.cpu1.icache.overall_misses::total 540854 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 37994463 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 37994463 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 37994463 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014235 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014235 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014235 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014235 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014235 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014235 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13500.045299 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13500.045299 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13500.045299 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13500.045299 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1081,120 +1081,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469706 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 469706 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 469706 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 469706 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 469706 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 469706 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5404193000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5404193000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5404193000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5404193000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5404193000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5404193000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014152 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014152 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014152 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11505.480024 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 540854 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 540854 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 540854 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 540854 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 540854 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 540854 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6219845500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6219845500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6219845500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6219845500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6219845500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6219845500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4396000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4396000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4396000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 4396000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014235 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014235 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014235 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11500.045299 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 292054 # number of replacements -system.cpu1.dcache.tagsinuse 471.972808 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11961234 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 292426 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.903456 # 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number of cycles access was blocked @@ -1203,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265102 # number of writebacks -system.cpu1.dcache.writebacks::total 265102 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170515 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170515 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149924 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149924 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11068 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11068 # 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average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1284,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index b72126c20..73585121b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603635 # Number of seconds simulated -sim_ticks 2603634694000 # Number of ticks simulated -final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603665 # Number of seconds simulated +sim_ticks 2603664815000 # Number of ticks simulated +final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 413538 # Simulator instruction rate (inst/s) -host_op_rate 526220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17886148072 # Simulator tick rate (ticks/s) -host_mem_usage 448796 # Number of bytes of host memory used -host_seconds 145.57 # Real time elapsed on the host -sim_insts 60197457 # Number of instructions simulated -sim_ops 76600355 # Number of ops (including micro ops) simulated +host_inst_rate 536000 # Simulator instruction rate (inst/s) +host_op_rate 682052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23183028791 # Simulator tick rate (ticks/s) +host_mem_usage 404656 # Number of bytes of host memory used +host_seconds 112.31 # Real time elapsed on the host +sim_insts 60197643 # Number of instructions simulated +sim_ops 76600583 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory -system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory +system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494095 # Total number of read requests seen -system.physmem.writeReqs 811481 # Total number of write requests seen -system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991622080 # Total number of bytes read from memory -system.physmem.bytesWritten 51934784 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494089 # Total number of read requests seen +system.physmem.writeReqs 811479 # Total number of write requests seen +system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991621696 # Total number of bytes read from memory +system.physmem.bytesWritten 51934656 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603630334000 # Total gap between requests +system.physmem.totGap 2603660455000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152019 # Categorize read packet sizes +system.physmem.readPktSize::6 152013 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -108,7 +108,7 @@ system.physmem.writePktSize::2 754018 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57463 # categorize write packet sizes +system.physmem.writePktSize::6 57461 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -120,23 +120,23 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -153,14 +153,14 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see @@ -169,44 +169,44 @@ system.physmem.wrQLenPdf::12 35282 # Wh system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests -system.physmem.totBusLat 61975036000 # Total cycles spent in databus access -system.physmem.totBankLat 16863224000 # Total cycles spent in bank access -system.physmem.avgQLat 18619.82 # Average queueing delay per request -system.physmem.avgBankLat 1088.39 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23708.21 # Average memory access latency +system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests +system.physmem.totBusLat 77468765000 # Total cycles spent in databus access +system.physmem.totBankLat 17445216250 # Total cycles spent in bank access +system.physmem.avgQLat 22041.64 # Average queueing delay per request +system.physmem.avgBankLat 1125.95 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28167.59 # Average memory access latency system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.51 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 12.40 # Average write queue length over time -system.physmem.readRowHits 15451886 # Number of row buffer hits during reads -system.physmem.writeRowHits 785061 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes -system.physmem.avgGap 159677.30 # Average gap between requests +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 12.39 # Average write queue length over time +system.physmem.readRowHits 15418905 # Number of row buffer hits during reads +system.physmem.writeRowHits 794060 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes +system.physmem.avgGap 159679.22 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995645 # DTB read hits -system.cpu.dtb.read_misses 7331 # DTB read misses -system.cpu.dtb.write_hits 11230857 # DTB write hits +system.cpu.dtb.read_hits 14995667 # DTB read hits +system.cpu.dtb.read_misses 7332 # DTB read misses +system.cpu.dtb.write_hits 11230865 # DTB write hits system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002976 # DTB read accesses -system.cpu.dtb.write_accesses 11233060 # DTB write accesses +system.cpu.dtb.read_accesses 15002999 # DTB read accesses +system.cpu.dtb.write_accesses 11233068 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226502 # DTB hits -system.cpu.dtb.misses 9534 # DTB misses -system.cpu.dtb.accesses 26236036 # DTB accesses -system.cpu.itb.inst_hits 61491397 # ITB inst hits +system.cpu.dtb.hits 26226532 # DTB hits +system.cpu.dtb.misses 9535 # DTB misses +system.cpu.dtb.accesses 26236067 # DTB accesses +system.cpu.itb.inst_hits 61491584 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -263,79 +263,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495868 # ITB inst accesses -system.cpu.itb.hits 61491397 # DTB hits +system.cpu.itb.inst_accesses 61496055 # ITB inst accesses +system.cpu.itb.hits 61491584 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495868 # DTB accesses -system.cpu.numCycles 5207269388 # number of cpu cycles simulated +system.cpu.itb.accesses 61496055 # DTB accesses +system.cpu.numCycles 5207329630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197457 # Number of instructions committed -system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses +system.cpu.committedInsts 60197643 # Number of instructions committed +system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139722 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls -system.cpu.num_int_insts 68868122 # number of integer instructions +system.cpu.num_func_calls 2139730 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls +system.cpu.num_int_insts 68868344 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read -system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written +system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read +system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393871 # number of memory refs -system.cpu.num_load_insts 15659652 # Number of load instructions -system.cpu.num_store_insts 11734219 # Number of store instructions -system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879373 # Percentage of idle cycles +system.cpu.num_mem_refs 27393912 # number of memory refs +system.cpu.num_load_insts 15659685 # Number of load instructions +system.cpu.num_store_insts 11734227 # Number of store instructions +system.cpu.num_idle_cycles 4579092870.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628236759.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879355 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855485 # number of replacements -system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use -system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635400 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635400 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635400 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635400 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635400 # number of overall hits -system.cpu.icache.overall_hits::total 60635400 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855997 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855997 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855997 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855997 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855997 # number of overall misses -system.cpu.icache.overall_misses::total 855997 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11539684000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11539684000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11539684000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11539684000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11539684000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11539684000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses +system.cpu.icache.replacements 855486 # number of replacements +system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use +system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635586 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits +system.cpu.icache.overall_hits::total 60635586 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855998 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855998 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855998 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855998 # number of overall misses +system.cpu.icache.overall_misses::total 855998 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11569304000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11569304000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11569304000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11569304000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11569304000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11569304000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491584 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491584 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491584 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491584 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13480.986499 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13480.986499 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13480.986499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13480.986499 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13515.573635 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13515.573635 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13515.573635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13515.573635 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,174 +344,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855997 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855997 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 855997 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 855997 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 855997 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 855997 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9827690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9827690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9827690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9827690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9827690000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9827690000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 288141500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855998 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 855998 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 855998 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 855998 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 855998 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 855998 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9857308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9857308000 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9173753597 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9173753597 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209122550 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175862199412 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176071321962 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016419 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025929 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537876 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537876 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537874 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537874 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227849 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.102819 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37229.212939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39014.310681 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38090.111817 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10035.241391 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10035.241391 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32707.824249 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32707.824249 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37229.212939 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -615,79 +615,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # 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number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973048 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits +system.cpu.dcache.replacements 627291 # number of replacements +system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use +system.cpu.dcache.total_refs 23655046 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627803 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.679090 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195134 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195134 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236278 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236278 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168170 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168170 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168170 # number of overall hits -system.cpu.dcache.overall_hits::total 23168170 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368781 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368781 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619291 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619291 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619291 # number of overall misses -system.cpu.dcache.overall_misses::total 619291 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201704000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5201704000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8045775500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8045775500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154787000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 154787000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13247479500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13247479500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13247479500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13247479500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 23168189 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168189 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168189 # number of overall hits +system.cpu.dcache.overall_hits::total 23168189 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368792 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250511 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250511 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11401 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11401 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619303 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619303 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619303 # number of overall misses +system.cpu.dcache.overall_misses::total 619303 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222508000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5222508000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8035214500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8035214500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155940000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 155940000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13257722500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13257722500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13257722500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13257722500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223566 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223566 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027188 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027188 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026034 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026034 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026034 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026034 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.130145 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.130145 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32117.582132 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32117.582132 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.425364 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.425364 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21391.364480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21391.364480 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,54 +696,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596029 # number of writebacks -system.cpu.dcache.writebacks::total 596029 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368781 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368781 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619291 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619291 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619291 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619291 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4464142000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4464142000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7544755500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7544755500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12008897500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12008897500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12008897500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12008897500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182078406500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182078406500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18714752000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18714752000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200793158500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 200793158500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027188 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027188 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks +system.cpu.dcache.writebacks::total 596039 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.130145 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.130145 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30117.582132 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30117.582132 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11575.425364 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11575.425364 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -765,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1130504893187 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1130504893187 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 21a80bd51..9d3d17a68 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -211,7 +211,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time |