diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
12 files changed, 518 insertions, 138 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index b18e2b725..31269f9bd 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -299,9 +300,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -360,10 +360,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -775,9 +774,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 17a6394ef..be4dcf157 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:25:17 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 911653589000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 96669edc4..002831edb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,32 +4,90 @@ sim_seconds 0.911654 # Nu sim_ticks 911653589000 # Number of ticks simulated final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1682178 # Simulator instruction rate (inst/s) -host_op_rate 2174115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25299801897 # Simulator tick rate (ticks/s) -host_mem_usage 379752 # Number of bytes of host memory used -host_seconds 36.03 # Real time elapsed on the host +host_inst_rate 1520101 # Simulator instruction rate (inst/s) +host_op_rate 1964640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22862175544 # Simulator tick rate (ticks/s) +host_mem_usage 382804 # Number of bytes of host memory used +host_seconds 39.88 # Real time elapsed on the host sim_insts 60615585 # Number of instructions simulated sim_ops 78342060 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 50963556 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1003776 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10224784 # Number of bytes written to this memory -system.physmem.num_reads 5103504 # Number of read requests responded to by this memory -system.physmem.num_writes 869236 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 55902326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1101050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 11215646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 67117972 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 75 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 75 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 75 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 661924 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6760756 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 341852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3873968 # Number of bytes read from this memory +system.physmem.bytes_read::total 50963556 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 661924 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 341852 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1003776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7197696 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory +system.physmem.bytes_written::total 10224784 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16561 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 105709 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 60557 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5103504 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 112464 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory +system.physmem.num_writes::total 869236 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 726070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7415926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 374980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4249386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 55902326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 726070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 374980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1101050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7895209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11215646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7895209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 726070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 7434574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 374980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7551175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67117972 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 127935 # number of replacements system.l2c.tagsinuse 26245.835103 # Cycle average of tags in use system.l2c.total_refs 1477463 # Total number of references to valid blocks. @@ -175,12 +233,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003715 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011465 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.014612 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.073080 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.027957 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.882345 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805848 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.855220 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.845087 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.655949 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.765972 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.590549 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.604811 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.595343 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.003625 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.020038 # miss rate for demand accesses @@ -189,6 +251,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003715 system.l2c.demand_miss_rate::cpu1.itb.walker 0.011465 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.014612 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.274157 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.123526 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.003625 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.020038 # miss rate for overall accesses @@ -197,6 +260,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003715 system.l2c.overall_miss_rate::cpu1.itb.walker 0.011465 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.014612 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.274157 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.123526 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,8 +372,11 @@ system.cpu0.icache.demand_accesses::total 34685670 # n system.cpu0.icache.overall_accesses::cpu0.inst 34685670 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 34685670 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014349 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014349 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014349 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014349 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014349 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014349 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,11 +434,17 @@ system.cpu0.dcache.demand_accesses::total 14721592 # n system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.030010 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.027741 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054599 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040342 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028976 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028976 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,8 +550,11 @@ system.cpu1.icache.demand_accesses::total 26945412 # n system.cpu1.icache.overall_accesses::cpu1.inst 26945412 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 26945412 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013596 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013596 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013596 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013596 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -536,11 +612,17 @@ system.cpu1.dcache.demand_accesses::total 9644704 # n system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027294 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029093 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158141 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.149298 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027992 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027992 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 720edf3cb..99dc32f6e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -184,9 +185,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -245,10 +245,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -660,9 +659,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 4b3b38463..f08c091ef 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:24:24 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2332330037000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e1058fc4f..154c8ff44 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.332330 # Nu sim_ticks 2332330037000 # Number of ticks simulated final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1538399 # Simulator instruction rate (inst/s) -host_op_rate 1985816 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60412799239 # Simulator tick rate (ticks/s) -host_mem_usage 379756 # Number of bytes of host memory used -host_seconds 38.61 # Real time elapsed on the host +host_inst_rate 1412842 # Simulator instruction rate (inst/s) +host_op_rate 1823742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55482154888 # Simulator tick rate (ticks/s) +host_mem_usage 382804 # Number of bytes of host memory used +host_seconds 42.04 # Real time elapsed on the host sim_insts 59392246 # Number of instructions simulated sim_ops 76665494 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 122661296 # Number of bytes read from this memory -system.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9590216 # Number of bytes written to this memory -system.physmem.num_reads 14137091 # Number of read requests responded to by this memory -system.physmem.num_writes 856679 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 941920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10043536 # Number of bytes read from this memory +system.physmem.bytes_read::total 122661296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 941920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 941920 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6574400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory +system.physmem.bytes_written::total 9590216 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 24 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 20920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156964 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14137091 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102725 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856679 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 403854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4306224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52591740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 403854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 403854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2818812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4111861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2818812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 403854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5599273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 56703601 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 117012 # number of replacements system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use system.l2c.total_refs 1527554 # Total number of references to valid blocks. @@ -112,16 +143,21 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.570577 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.116613 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.116613 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -233,8 +269,11 @@ system.cpu.icache.demand_accesses::total 60406063 # nu system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,10 +329,15 @@ system.cpu.dcache.demand_accesses::total 23757776 # nu system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index e58e54e5c..08257cec9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -291,9 +292,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -352,10 +352,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -767,9 +766,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index d6c8fa18c..dc9f6d387 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:26:08 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1169707043000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 4dc707863..c1f17df29 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,32 +4,90 @@ sim_seconds 1.169707 # Nu sim_ticks 1169707043000 # Number of ticks simulated final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 754175 # Simulator instruction rate (inst/s) -host_op_rate 964493 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14598169556 # Simulator tick rate (ticks/s) -host_mem_usage 379804 # Number of bytes of host memory used -host_seconds 80.13 # Real time elapsed on the host +host_inst_rate 657704 # Simulator instruction rate (inst/s) +host_op_rate 841119 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12730829062 # Simulator tick rate (ticks/s) +host_mem_usage 382856 # Number of bytes of host memory used +host_seconds 91.88 # Real time elapsed on the host sim_insts 60429704 # Number of instructions simulated sim_ops 77281862 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 61898788 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10078928 # Number of bytes written to this memory -system.physmem.num_reads 6478591 # Number of read requests responded to by this memory -system.physmem.num_writes 867017 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 534756 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5211316 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 470236 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5348464 # Number of bytes read from this memory +system.physmem.bytes_read::total 61898788 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 534756 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 470236 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1004992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7051584 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 10078928 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14574 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 81499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 83596 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6478591 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 110181 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 867017 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43029277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 547 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 457171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4455232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 402012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4572482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52918197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 457171 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 402012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 859183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6028504 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14534 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2573588 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8616626 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6028504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43029277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 457171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4469765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 402012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7146070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 61534823 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 125934 # number of replacements system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use system.l2c.total_refs 1500548 # Total number of references to valid blocks. @@ -211,12 +269,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002559 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.016188 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.055681 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028163 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797203 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.868377 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.826789 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.717722 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.700775 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.710105 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.569136 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.605340 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.587311 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.002264 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.019500 # miss rate for demand accesses @@ -225,6 +287,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.demand_miss_rate::cpu1.itb.walker 0.002559 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.016188 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.307390 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.122213 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.002264 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.019500 # miss rate for overall accesses @@ -233,6 +296,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.overall_miss_rate::cpu1.itb.walker 0.002559 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.016188 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.307390 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.122213 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52125 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010 # average ReadReq miss latency @@ -241,12 +305,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52152.561534 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6548.352589 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8411.374931 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 7361.740598 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7160.493827 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 8935.230618 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52082.720239 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency @@ -255,6 +323,7 @@ system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52096.107637 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency @@ -263,6 +332,7 @@ system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52096.107637 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -372,12 +442,16 @@ system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.028163 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.826789 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710105 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.587311 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses @@ -386,6 +460,7 @@ system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.122213 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses @@ -394,6 +469,7 @@ system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.122213 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency @@ -402,12 +478,16 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40153.009531 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40051.711668 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40039.254171 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40082.720239 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency @@ -416,6 +496,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency @@ -424,16 +505,20 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -541,11 +626,17 @@ system.cpu0.icache.demand_accesses::total 29439615 # n system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013882 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013882 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013882 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14826.735750 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14826.735750 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14826.735750 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,13 +664,21 @@ system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013882 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013882 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013882 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11823.686947 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 335831 # number of replacements system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use @@ -639,17 +738,29 @@ system.cpu0.dcache.demand_accesses::total 12319714 # n system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033860 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025969 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060456 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047493 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030342 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030342 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15320.382890 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35592.072418 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.558127 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9145.766345 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23054.541807 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23054.541807 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,20 +802,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033860 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025969 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060456 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047474 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030342 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030342 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.946018 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32591.360717 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.558127 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6149.443774 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -806,11 +932,17 @@ system.cpu1.icache.demand_accesses::total 32286236 # n system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14686.743809 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14686.743809 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14686.743809 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,13 +970,21 @@ system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014087 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014087 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11684.088965 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 294642 # number of replacements system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use @@ -904,17 +1044,29 @@ system.cpu1.dcache.demand_accesses::total 12098117 # n system.cpu1.dcache.overall_accesses::cpu1.data 12098117 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 12098117 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024175 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.024175 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030209 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030209 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119732 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119732 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104658 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026659 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026659 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14503.858110 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 35153.999575 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11199.721298 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7579.207411 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24134.585035 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24134.585035 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -956,20 +1108,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024175 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030209 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119732 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104604 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026659 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026659 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11503.175387 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32153.756914 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.721298 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4583.110196 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -990,7 +1157,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index bdfa88421..6a942652a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -180,9 +181,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -241,10 +241,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -656,9 +655,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index db3a98367..b6cf436ae 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:25:42 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2591419000000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index c192aecc6..20ffbfc50 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.591419 # Nu sim_ticks 2591419000000 # Number of ticks simulated final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 632591 # Simulator instruction rate (inst/s) -host_op_rate 807921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27699122939 # Simulator tick rate (ticks/s) -host_mem_usage 380048 # Number of bytes of host memory used -host_seconds 93.56 # Real time elapsed on the host +host_inst_rate 555808 # Simulator instruction rate (inst/s) +host_op_rate 709857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24337050134 # Simulator tick rate (ticks/s) +host_mem_usage 383104 # Number of bytes of host memory used +host_seconds 106.48 # Real time elapsed on the host sim_insts 59182652 # Number of instructions simulated sim_ops 75585847 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 133632176 # Number of bytes read from this memory -system.physmem.bytes_inst_read 955744 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9600072 # Number of bytes written to this memory -system.physmem.num_reads 15512735 # Number of read requests responded to by this memory -system.physmem.num_writes 856893 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51567182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 368811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3704562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55271744 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 955744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9990864 # Number of bytes read from this memory +system.physmem.bytes_read::total 133632176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 955744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 955744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6584000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 9600072 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 21136 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15512735 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102875 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856893 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47342167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 368811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3855364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51567182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 368811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 368811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2540693 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1163869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3704562 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2540693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47342167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 368811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5019233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55271744 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 117210 # number of replacements system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use system.l2c.total_refs 1536782 # Total number of references to valid blocks. @@ -131,30 +162,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002518 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003377 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016996 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.044928 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.025341 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.991025 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991025 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.568473 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.568473 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.002518 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.003377 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.016996 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.252085 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.115451 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.002518 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.003377 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.016996 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.252085 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.115451 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52203.925620 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52113.632350 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52155.074026 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 362.243121 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 362.243121 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52071.302204 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52071.302204 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52086.639310 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52086.639310 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,35 +256,48 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002518 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.044928 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.025341 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991025 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.568473 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.568473 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.115451 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.115451 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40203.512397 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40113.602920 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40154.867958 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.684779 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40054.684779 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40071.298651 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40071.298651 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -351,11 +405,17 @@ system.cpu.icache.demand_accesses::total 60464458 # nu system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14703.491239 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14703.491239 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14703.491239 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,13 +443,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.697734 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 627094 # number of replacements system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use @@ -445,15 +513,25 @@ system.cpu.dcache.demand_accesses::total 23787844 # nu system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027178 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024500 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045914 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026027 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15831.273549 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38111.071410 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16292.930625 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24845.068079 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24845.068079 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -491,18 +569,31 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027178 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024500 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045914 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026027 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12830.916839 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35110.897746 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13292.930625 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -523,7 +614,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |