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-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini41
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt370
2 files changed, 213 insertions, 198 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index e3b4a020a..7bfde3940 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -10,23 +10,25 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
-dtb_filename=
+dtb_filename=False
early_kernel_symbols=false
enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
readfile=tests/halt.sh
symbolfile=
work_begin_ckpt_count=0
@@ -65,7 +67,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
@@ -92,6 +94,10 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
@@ -219,6 +225,10 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=true
@@ -338,6 +348,7 @@ children=badaddr_responder
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
@@ -363,25 +374,28 @@ pio=system.membus.default
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=true
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
@@ -511,7 +525,7 @@ warn_access=
pio=system.iobus.master[24]
[system.realview.gic]
-type=Gic
+type=Pl390
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
@@ -790,6 +804,7 @@ type=CoherentBus
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index 8816091ac..1dc10f98b 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -1,16 +1,28 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.332810 # Number of seconds simulated
-sim_ticks 2332810256000 # Number of ticks simulated
-final_tick 2332810256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2332810264000 # Number of ticks simulated
+final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 685945 # Simulator instruction rate (inst/s)
-host_op_rate 882083 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26489224850 # Simulator tick rate (ticks/s)
-host_mem_usage 391216 # Number of bytes of host memory used
-host_seconds 88.07 # Real time elapsed on the host
+host_inst_rate 1307768 # Simulator instruction rate (inst/s)
+host_op_rate 1681709 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50502250863 # Simulator tick rate (ticks/s)
+host_mem_usage 395644 # Number of bytes of host memory used
+host_seconds 46.19 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
@@ -205,31 +217,19 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 62242 # number of replacements
-system.l2c.tagsinuse 50006.300216 # Cycle average of tags in use
-system.l2c.total_refs 1678484 # Total number of references to valid blocks.
+system.l2c.tagsinuse 50006.300222 # Cycle average of tags in use
+system.l2c.total_refs 1678485 # Total number of references to valid blocks.
system.l2c.sampled_refs 127627 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.151480 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 2316901485000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 36900.571426 # Average occupied blocks per requestor
+system.l2c.avg_refs 13.151488 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4917.298425 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 3152.525316 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 2097.421528 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 2936.495766 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
@@ -240,13 +240,13 @@ system.l2c.occ_percent::cpu1.data 0.044807 # Av
system.l2c.occ_percent::total 0.763036 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 473131 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 196969 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 196972 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 4875 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 2050 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 365740 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 169794 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1224841 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 365737 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 169792 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1224842 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 592682 # number of Writeback hits
system.l2c.Writeback_hits::total 592682 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits
@@ -257,22 +257,22 @@ system.l2c.ReadExReq_hits::cpu1.data 50403 # nu
system.l2c.ReadExReq_hits::total 113738 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 9005 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3277 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 473131 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 260304 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 473134 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 260307 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 4875 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 2050 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 365740 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 220197 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1338579 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 365737 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 220195 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1338580 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 9005 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3277 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 473131 # number of overall hits
-system.l2c.overall_hits::cpu0.data 260304 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 473134 # number of overall hits
+system.l2c.overall_hits::cpu0.data 260307 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 4875 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 2050 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 365740 # number of overall hits
-system.l2c.overall_hits::cpu1.data 220197 # number of overall hits
-system.l2c.overall_hits::total 1338579 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 365737 # number of overall hits
+system.l2c.overall_hits::cpu1.data 220195 # number of overall hits
+system.l2c.overall_hits::total 1338580 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7285 # number of ReadReq misses
@@ -302,13 +302,13 @@ system.l2c.overall_misses::cpu1.data 41049 # nu
system.l2c.overall_misses::total 153953 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker 9007 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3280 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 480416 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 202776 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 480419 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 202779 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4875 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 2050 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 369059 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 173859 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1245322 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 369056 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 173857 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1245323 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 592682 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 592682 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1532 # number of UpgradeReq accesses(hits+misses)
@@ -319,26 +319,26 @@ system.l2c.ReadExReq_accesses::cpu1.data 87387 # nu
system.l2c.ReadExReq_accesses::total 247210 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 9007 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3280 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 480416 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 362599 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 480419 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 362602 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 4875 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 2050 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 369059 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 261246 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1492532 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 369056 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 261244 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1492533 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 9007 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3280 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 480416 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 362599 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 480419 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 362602 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 4875 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 2050 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 369059 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 261246 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1492532 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 369056 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 261244 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1492533 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000915 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015164 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.028638 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.028637 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.008993 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.023381 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses
@@ -351,16 +351,16 @@ system.l2c.ReadExReq_miss_rate::total 0.539913 # mi
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000915 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.015164 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.282116 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.282114 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.008993 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.157128 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.157129 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.103149 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000915 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.015164 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.282116 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.282114 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.008993 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.157128 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.157129 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.103149 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
@@ -381,10 +381,10 @@ system.cf0.dma_write_bytes 0 # Nu
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7929195 # DTB read hits
-system.cpu0.dtb.read_misses 6442 # DTB read misses
-system.cpu0.dtb.write_hits 6437090 # DTB write hits
-system.cpu0.dtb.write_misses 1931 # DTB write misses
+system.cpu0.dtb.read_hits 7929205 # DTB read hits
+system.cpu0.dtb.read_misses 6441 # DTB read misses
+system.cpu0.dtb.write_hits 6437098 # DTB write hits
+system.cpu0.dtb.write_misses 1932 # DTB write misses
system.cpu0.dtb.flush_tlb 1168 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID
@@ -394,13 +394,13 @@ system.cpu0.dtb.align_faults 0 # Nu
system.cpu0.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7935637 # DTB read accesses
-system.cpu0.dtb.write_accesses 6439021 # DTB write accesses
+system.cpu0.dtb.read_accesses 7935646 # DTB read accesses
+system.cpu0.dtb.write_accesses 6439030 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14366285 # DTB hits
+system.cpu0.dtb.hits 14366303 # DTB hits
system.cpu0.dtb.misses 8373 # DTB misses
-system.cpu0.dtb.accesses 14374658 # DTB accesses
-system.cpu0.itb.inst_hits 32543252 # ITB inst hits
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system.cpu0.itb.inst_misses 3703 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
@@ -417,30 +417,30 @@ system.cpu0.itb.domain_faults 0 # Nu
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 32546955 # ITB inst accesses
-system.cpu0.itb.hits 32543252 # DTB hits
+system.cpu0.itb.inst_accesses 32546956 # ITB inst accesses
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system.cpu0.itb.misses 3703 # DTB misses
-system.cpu0.itb.accesses 32546955 # DTB accesses
-system.cpu0.numCycles 4633589645 # number of cpu cycles simulated
+system.cpu0.itb.accesses 32546956 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 31998088 # Number of instructions committed
-system.cpu0.committedOps 41901559 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 37065460 # Number of integer alu accesses
+system.cpu0.committedInsts 31998091 # Number of instructions committed
+system.cpu0.committedOps 41901593 # Number of ops (including micro ops) committed
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system.cpu0.num_fp_alu_accesses 5364 # Number of float alu accesses
-system.cpu0.num_func_calls 1207172 # number of times a function call or return occured
+system.cpu0.num_func_calls 1207173 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4285544 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 37065460 # number of integer instructions
+system.cpu0.num_int_insts 37065495 # number of integer instructions
system.cpu0.num_fp_insts 5364 # number of float instructions
-system.cpu0.num_int_register_reads 188704130 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 39536951 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 188704279 # number of times the integer registers were read
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system.cpu0.num_fp_register_reads 3938 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1428 # number of times the floating registers were written
-system.cpu0.num_mem_refs 15013039 # number of memory refs
-system.cpu0.num_load_insts 8304652 # Number of load instructions
-system.cpu0.num_store_insts 6708387 # Number of store instructions
-system.cpu0.num_idle_cycles 186586242.606667 # Number of idle cycles
-system.cpu0.num_busy_cycles 4447003402.393333 # Number of busy cycles
+system.cpu0.num_mem_refs 15013057 # number of memory refs
+system.cpu0.num_load_insts 8304661 # Number of load instructions
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+system.cpu0.num_busy_cycles 4447003463.939495 # Number of busy cycles
system.cpu0.not_idle_fraction 0.959732 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
@@ -450,38 +450,38 @@ system.cpu0.icache.tagsinuse 511.678593 # Cy
system.cpu0.icache.total_refs 60583498 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 851102 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 71.182418 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 5709380500 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
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system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
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system.cpu0.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses
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system.cpu0.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014788 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012801 # miss rate for ReadReq accesses
@@ -501,68 +501,68 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 623333 # number of replacements
+system.cpu0.dcache.replacements 623334 # number of replacements
system.cpu0.dcache.tagsinuse 511.997031 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 23628287 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 623845 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 37.875253 # Average number of references to valid blocks.
+system.cpu0.dcache.total_refs 23628284 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 623846 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 37.875187 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 451.298859 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu1.data 60.698172 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor
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system.cpu0.dcache.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
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system.cpu0.dcache.WriteReq_hits::total 9962065 # number of WriteReq hits
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system.cpu0.dcache.LoadLockedReq_hits::total 236036 # number of LoadLockedReq hits
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system.cpu0.dcache.WriteReq_misses::cpu0.data 161355 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 250155 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6647 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4536 # number of LoadLockedReq misses
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system.cpu0.dcache.WriteReq_accesses::total 10212220 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.LoadLockedReq_accesses::total 247219 # number of LoadLockedReq accesses(hits+misses)
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system.cpu0.dcache.StoreCondReq_accesses::total 247218 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027272 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026649 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
@@ -570,13 +570,13 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027172
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020777 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.024496 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045547 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044786 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044785 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027227 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024288 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024287 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027227 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024288 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024287 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
@@ -591,26 +591,26 @@ system.cpu0.dcache.writebacks::total 592682 # nu
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 7038607 # DTB read hits
-system.cpu1.dtb.read_misses 4222 # DTB read misses
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-system.cpu1.dtb.write_misses 1250 # DTB write misses
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+system.cpu1.dtb.write_misses 1249 # DTB write misses
system.cpu1.dtb.flush_tlb 1166 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2949 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 80 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 82 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 7042829 # DTB read accesses
-system.cpu1.dtb.write_accesses 4780164 # DTB write accesses
+system.cpu1.dtb.read_accesses 7042818 # DTB read accesses
+system.cpu1.dtb.write_accesses 4780155 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 11817521 # DTB hits
+system.cpu1.dtb.hits 11817501 # DTB hits
system.cpu1.dtb.misses 5472 # DTB misses
-system.cpu1.dtb.accesses 11822993 # DTB accesses
-system.cpu1.itb.inst_hits 28886893 # ITB inst hits
+system.cpu1.dtb.accesses 11822973 # DTB accesses
+system.cpu1.itb.inst_hits 28886892 # ITB inst hits
system.cpu1.itb.inst_misses 2463 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
@@ -627,30 +627,30 @@ system.cpu1.itb.domain_faults 0 # Nu
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 28889356 # ITB inst accesses
-system.cpu1.itb.hits 28886893 # DTB hits
+system.cpu1.itb.inst_accesses 28889355 # ITB inst accesses
+system.cpu1.itb.hits 28886892 # DTB hits
system.cpu1.itb.misses 2463 # DTB misses
-system.cpu1.itb.accesses 28889356 # DTB accesses
-system.cpu1.numCycles 4279954910 # number of cpu cycles simulated
+system.cpu1.itb.accesses 28889355 # DTB accesses
+system.cpu1.numCycles 4279954879 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 28410551 # Number of instructions committed
-system.cpu1.committedOps 35780260 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 31730145 # Number of integer alu accesses
+system.cpu1.committedInsts 28410548 # Number of instructions committed
+system.cpu1.committedOps 35780226 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 31730110 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 4905 # Number of float alu accesses
-system.cpu1.num_func_calls 928836 # number of times a function call or return occured
+system.cpu1.num_func_calls 928835 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3656569 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 31730145 # number of integer instructions
+system.cpu1.num_int_insts 31730110 # number of integer instructions
system.cpu1.num_fp_insts 4905 # number of float instructions
-system.cpu1.num_int_register_reads 160620144 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 34566657 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 160619995 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 34566633 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3555 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1352 # number of times the floating registers were written
-system.cpu1.num_mem_refs 12348598 # number of memory refs
-system.cpu1.num_load_insts 7334875 # Number of load instructions
-system.cpu1.num_store_insts 5013723 # Number of store instructions
-system.cpu1.num_idle_cycles 8315278953.102118 # Number of idle cycles
-system.cpu1.num_busy_cycles -4035324043.102118 # Number of busy cycles
+system.cpu1.num_mem_refs 12348580 # number of memory refs
+system.cpu1.num_load_insts 7334866 # Number of load instructions
+system.cpu1.num_store_insts 5013714 # Number of store instructions
+system.cpu1.num_idle_cycles 8315278901.051629 # Number of idle cycles
+system.cpu1.num_busy_cycles -4035324022.051629 # Number of busy cycles
system.cpu1.not_idle_fraction -0.942843 # Percentage of non-idle cycles
system.cpu1.idle_fraction 1.942843 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed