diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
5 files changed, 4844 insertions, 3286 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index df149be6e..2e680c93e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,69 +1,18 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.900855 # Number of seconds simulated -sim_ticks 900854787500 # Number of ticks simulated -final_tick 900854787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.900830 # Number of seconds simulated +sim_ticks 900829868000 # Number of ticks simulated +final_tick 900829868000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 875862 # Simulator instruction rate (inst/s) -host_op_rate 1055198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12821864647 # Simulator tick rate (ticks/s) -host_mem_usage 433912 # Number of bytes of host memory used -host_seconds 70.26 # Real time elapsed on the host -sim_insts 61537412 # Number of instructions simulated -sim_ops 74137396 # Number of ops (including micro ops) simulated +host_inst_rate 1355321 # Simulator instruction rate (inst/s) +host_op_rate 1632835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19839612971 # Simulator tick rate (ticks/s) +host_mem_usage 467260 # Number of bytes of host memory used +host_seconds 45.41 # Real time elapsed on the host +sim_insts 61539136 # Number of instructions simulated +sim_ops 74139862 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 460108 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6580092 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 258564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2992120 # Number of bytes read from this memory -system.physmem.bytes_read::total 49612932 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 460108 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 258564 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 718672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4174784 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7201872 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 102873 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 46770 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5082398 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65231 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 822003 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43649210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 510746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7304276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 287021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3321423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 55073173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 510746 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 287021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 797767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4634247 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 3360195 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7994487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4634247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43649210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 510746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10664471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 287021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3321468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 63067661 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -82,180 +31,270 @@ system.realview.nvmem.bw_inst_read::total 75 # I system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 65740815 # Throughput (bytes/s) -system.membus.data_through_bus 59222928 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 468620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6508860 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 266564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2938616 # Number of bytes read from this memory +system.physmem.bytes_read::total 49504452 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 468620 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 266564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 735184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3365568 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 6392656 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 101760 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45934 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5080703 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 52587 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 809359 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43650418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 71 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 520209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7225404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 295909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3262121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54954275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 520209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 295909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 816119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3736075 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 3360288 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7096408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3736075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43650418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 71 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 520209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10585693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 295909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3262165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62050682 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 6129610 # Transaction distribution +system.membus.trans_dist::ReadResp 6129610 # Transaction distribution +system.membus.trans_dist::WriteReq 767040 # Transaction distribution +system.membus.trans_dist::WriteResp 767040 # Transaction distribution +system.membus.trans_dist::Writeback 52587 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37380 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 20039 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14449 # Transaction distribution +system.membus.trans_dist::ReadExReq 163617 # Transaction distribution +system.membus.trans_dist::ReadExResp 136674 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 682 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1995948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4387646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 9830400 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 9830400 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14218046 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2389580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 17128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1364 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16575508 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18983656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 39321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 39321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 58305256 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 295628 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 295628 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 295628 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 70256 # number of replacements -system.l2c.tags.tagsinuse 51491.506872 # Cycle average of tags in use -system.l2c.tags.total_refs 1633923 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 135467 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.061410 # Average number of references to valid blocks. +system.l2c.tags.replacements 60014 # number of replacements +system.l2c.tags.tagsinuse 50124.590156 # Cycle average of tags in use +system.l2c.tags.total_refs 136044 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 120331 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.130581 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39155.338647 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.673377 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4830.605577 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5154.208952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1696.649192 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 652.030072 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.597463 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073709 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.078647 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009949 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785698 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65207 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3953 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 12685 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48286 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994980 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 16963603 # Number of tag accesses -system.l2c.tags.data_accesses 16963603 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4298 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1596 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 413244 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 202837 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4578 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 438543 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 146503 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1213542 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571726 # number of Writeback hits -system.l2c.Writeback_hits::total 571726 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1266 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1663 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 238 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 276 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 51499 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57148 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 108647 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4298 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1596 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 413244 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 254336 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4578 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 438543 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 203651 # number of demand (read+write) hits -system.l2c.demand_hits::total 1322189 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4298 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1596 # number of overall hits -system.l2c.overall_hits::cpu0.inst 413244 # number of overall hits -system.l2c.overall_hits::cpu0.data 254336 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4578 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits -system.l2c.overall_hits::cpu1.inst 438543 # number of overall hits -system.l2c.overall_hits::cpu1.data 203651 # number of overall hits -system.l2c.overall_hits::total 1322189 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6774 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9699 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4034 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1828 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22342 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2906 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5033 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 7939 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 414 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 662 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1076 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 94027 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 46518 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140545 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6774 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 103726 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4034 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 48346 # number of demand (read+write) misses -system.l2c.demand_misses::total 162887 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6774 # number of overall misses -system.l2c.overall_misses::cpu0.data 103726 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4034 # number of overall misses -system.l2c.overall_misses::cpu1.data 48346 # number of overall misses -system.l2c.overall_misses::total 162887 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4302 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1599 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 420018 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 212536 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 102859 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 175673 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 175673 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6079 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 6659 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 12738 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 793 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1507 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 100168 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 50523 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 150691 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 60 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 34 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 19288 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 147551 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 68 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 43 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 22698 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 63808 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 253550 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 60 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 34 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 19288 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 147551 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 68 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 43 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 22698 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 63808 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 253550 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.058824 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.358098 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.199607 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.183232 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.111253 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.213934 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.963645 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.973870 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.968990 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.971989 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974779 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.973457 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.926803 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.880332 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.911222 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.058824 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.358098 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.693279 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.183232 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.720207 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.628349 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.058824 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.358098 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.693279 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.183232 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.720207 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.628349 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -264,8 +303,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65231 # number of writebacks -system.l2c.writebacks::total 65231 # number of writebacks +system.l2c.writebacks::writebacks 52587 # number of writebacks +system.l2c.writebacks::total 52587 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -273,11 +312,92 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 156214740 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 140726796 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 46301771 # Throughput (bytes/s) -system.iobus.data_through_bus 41711172 # Total data (bytes) +system.toL2Bus.trans_dist::ReadReq 1357667 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1357667 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767040 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767040 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 175673 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 37136 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 20079 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 57215 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 177634 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 177634 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2263595 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2631190 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4894785 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 23563666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15087382 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38651048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 0 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 575784 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 575784 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 575784 # Request fanout histogram +system.iobus.trans_dist::ReadReq 6098452 # Transaction distribution +system.iobus.trans_dist::ReadResp 6098452 # Transaction distribution +system.iobus.trans_dist::WriteReq 7955 # Transaction distribution +system.iobus.trans_dist::WriteResp 7955 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7906 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 488 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382414 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 9830400 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 9830400 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 12212814 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40294 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15812 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 268 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2389580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 39321600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 39321600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 41711180 # Cumulative packet size per connected master and slave (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -301,9 +421,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7391669 # DTB read hits -system.cpu0.dtb.read_misses 1915 # DTB read misses -system.cpu0.dtb.write_hits 6659638 # DTB write hits +system.cpu0.dtb.read_hits 7391828 # DTB read hits +system.cpu0.dtb.read_misses 1916 # DTB read misses +system.cpu0.dtb.write_hits 6659769 # DTB write hits system.cpu0.dtb.write_misses 1130 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -314,12 +434,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7393584 # DTB read accesses -system.cpu0.dtb.write_accesses 6660768 # DTB write accesses +system.cpu0.dtb.read_accesses 7393744 # DTB read accesses +system.cpu0.dtb.write_accesses 6660899 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14051307 # DTB hits -system.cpu0.dtb.misses 3045 # DTB misses -system.cpu0.dtb.accesses 14054352 # DTB accesses +system.cpu0.dtb.hits 14051597 # DTB hits +system.cpu0.dtb.misses 3046 # DTB misses +system.cpu0.dtb.accesses 14054643 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -341,7 +461,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 37936012 # ITB inst hits +system.cpu0.itb.inst_hits 37936653 # ITB inst hits system.cpu0.itb.inst_misses 1207 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -358,37 +478,37 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37937219 # ITB inst accesses -system.cpu0.itb.hits 37936012 # DTB hits +system.cpu0.itb.inst_accesses 37937860 # ITB inst accesses +system.cpu0.itb.hits 37936653 # DTB hits system.cpu0.itb.misses 1207 # DTB misses -system.cpu0.itb.accesses 37937219 # DTB accesses -system.cpu0.numCycles 1801227301 # number of cpu cycles simulated +system.cpu0.itb.accesses 37937860 # DTB accesses +system.cpu0.numCycles 1801220958 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 37698803 # Number of instructions committed -system.cpu0.committedOps 44946380 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 39863943 # Number of integer alu accesses +system.cpu0.committedInsts 37699441 # Number of instructions committed +system.cpu0.committedOps 44947195 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 39864660 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses -system.cpu0.num_func_calls 1205467 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4697957 # number of instructions that are conditional controls -system.cpu0.num_int_insts 39863943 # number of integer instructions +system.cpu0.num_func_calls 1205511 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4698026 # number of instructions that are conditional controls +system.cpu0.num_int_insts 39864660 # number of integer instructions system.cpu0.num_fp_insts 4171 # number of float instructions -system.cpu0.num_int_register_reads 70363299 # number of times the integer registers were read -system.cpu0.num_int_register_writes 26108579 # number of times the integer registers were written +system.cpu0.num_int_register_reads 70364659 # number of times the integer registers were read +system.cpu0.num_int_register_writes 26109079 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 134797325 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 18388517 # number of times the CC registers were written -system.cpu0.num_mem_refs 14597479 # number of memory refs -system.cpu0.num_load_insts 7571296 # Number of load instructions -system.cpu0.num_store_insts 7026183 # Number of store instructions -system.cpu0.num_idle_cycles 1756006001.161348 # Number of idle cycles -system.cpu0.num_busy_cycles 45221299.838652 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025106 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974894 # Percentage of idle cycles -system.cpu0.Branches 6054325 # Number of branches fetched +system.cpu0.num_cc_register_reads 134799783 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 18388749 # number of times the CC registers were written +system.cpu0.num_mem_refs 14597797 # number of memory refs +system.cpu0.num_load_insts 7571468 # Number of load instructions +system.cpu0.num_store_insts 7026329 # Number of store instructions +system.cpu0.num_idle_cycles 1756040520.255098 # Number of idle cycles +system.cpu0.num_busy_cycles 45180437.744902 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025083 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974917 # Percentage of idle cycles +system.cpu0.Branches 6054439 # Number of branches fetched system.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 30338974 67.42% 67.45% # Class of executed instruction +system.cpu0.op_class::IntAlu 30339474 67.42% 67.45% # Class of executed instruction system.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction @@ -417,52 +537,51 @@ system.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction -system.cpu0.op_class::MemRead 7571296 16.82% 84.39% # Class of executed instruction -system.cpu0.op_class::MemWrite 7026183 15.61% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 7571468 16.82% 84.39% # Class of executed instruction +system.cpu0.op_class::MemWrite 7026329 15.61% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 45002137 # Class of executed instruction +system.cpu0.op_class::total 45002955 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42773 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 419775 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.035896 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 37516680 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 420287 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 89.264431 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 64363581500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.035896 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998117 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998117 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 42789 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 346148 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.428315 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 37590948 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 346660 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 108.437512 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 4521683000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.428315 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998883 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 38357256 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 38357256 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 37516680 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 37516680 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 37516680 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 37516680 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 37516680 # number of overall hits -system.cpu0.icache.overall_hits::total 37516680 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 420288 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 420288 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 420288 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 420288 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 420288 # number of overall misses -system.cpu0.icache.overall_misses::total 420288 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 37936968 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37936968 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37936968 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37936968 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37936968 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37936968 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011079 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011079 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011079 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011079 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011079 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011079 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 76221879 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76221879 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 37590948 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37590948 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37590948 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37590948 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37590948 # number of overall hits +system.cpu0.icache.overall_hits::total 37590948 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 346661 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 346661 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 346661 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 346661 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 346661 # number of overall misses +system.cpu0.icache.overall_misses::total 346661 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37937609 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37937609 # 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number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5591690 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5591690 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 77211 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 77211 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 134223 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 134223 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 135188 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 135188 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12446170 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12446170 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12523381 # number of overall hits +system.cpu0.dcache.overall_hits::total 12523381 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 187851 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 187851 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 165642 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 165642 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 51876 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 51876 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10381 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10381 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8852 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 8852 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 353493 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 353493 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 405369 # number of overall misses +system.cpu0.dcache.overall_misses::total 405369 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042331 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7042331 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757332 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5757332 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144583 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 144583 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144033 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144033 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12799401 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12799401 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12928488 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12928488 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.024611 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.024611 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027643 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.027643 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.389993 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.389993 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064932 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064932 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053085 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053085 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025975 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025975 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029610 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029610 # miss rate for overall accesses +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144604 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 144604 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144040 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144040 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12799663 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12799663 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12928750 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12928750 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026675 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.026675 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028771 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.028771 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.401869 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.401869 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.071789 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.071789 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061455 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061455 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027617 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027617 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031354 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031354 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -550,9 +804,45 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 321785 # number of writebacks -system.cpu0.dcache.writebacks::total 321785 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 323282 # number of writebacks +system.cpu0.dcache.writebacks::total 323282 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.trans_dist::ReadReq 689270 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 689270 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 763494 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 763494 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 323282 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 12769 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 8852 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 21621 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 152873 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 152873 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 706618 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2854542 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 4790 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 11848 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 3577798 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 22212896 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 49695730 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9580 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23696 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 71941902 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 229047 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 1276029 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.135706 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.342476 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 1102864 86.43% 86.43% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 173165 13.57% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 1276029 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -576,9 +866,9 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6028686 # DTB read hits -system.cpu1.dtb.read_misses 5403 # DTB read misses -system.cpu1.dtb.write_hits 4781604 # DTB write hits +system.cpu1.dtb.read_hits 6029083 # DTB read hits +system.cpu1.dtb.read_misses 5405 # DTB read misses +system.cpu1.dtb.write_hits 4781968 # DTB write hits system.cpu1.dtb.write_misses 1104 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -589,12 +879,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6034089 # DTB read accesses -system.cpu1.dtb.write_accesses 4782708 # DTB write accesses +system.cpu1.dtb.read_accesses 6034488 # DTB read accesses +system.cpu1.dtb.write_accesses 4783072 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10810290 # DTB hits -system.cpu1.dtb.misses 6507 # DTB misses -system.cpu1.dtb.accesses 10816797 # DTB accesses +system.cpu1.dtb.hits 10811051 # DTB hits +system.cpu1.dtb.misses 6509 # DTB misses +system.cpu1.dtb.accesses 10817560 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -616,7 +906,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 24626141 # ITB inst hits +system.cpu1.itb.inst_hits 24627232 # ITB inst hits system.cpu1.itb.inst_misses 3166 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -633,38 +923,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 24629307 # ITB inst accesses -system.cpu1.itb.hits 24626141 # DTB hits +system.cpu1.itb.inst_accesses 24630398 # ITB inst accesses +system.cpu1.itb.hits 24627232 # DTB hits system.cpu1.itb.misses 3166 # DTB misses -system.cpu1.itb.accesses 24629307 # DTB accesses -system.cpu1.numCycles 1801709576 # number of cpu cycles simulated +system.cpu1.itb.accesses 24630398 # DTB accesses +system.cpu1.numCycles 1801708036 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 23838609 # Number of instructions committed -system.cpu1.committedOps 29191016 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 25547086 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5650 # Number of float alu accesses -system.cpu1.num_func_calls 987842 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2987341 # number of instructions that are conditional controls -system.cpu1.num_int_insts 25547086 # number of integer instructions -system.cpu1.num_fp_insts 5650 # number of float instructions -system.cpu1.num_int_register_reads 48277330 # number of times the integer registers were read -system.cpu1.num_int_register_writes 17495174 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3706 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 86963152 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 11050350 # number of times the CC registers were written -system.cpu1.num_mem_refs 11165955 # number of memory refs -system.cpu1.num_load_insts 6206289 # Number of load instructions -system.cpu1.num_store_insts 4959666 # Number of store instructions -system.cpu1.num_idle_cycles 1771680344.893366 # Number of idle cycles -system.cpu1.num_busy_cycles 30029231.106634 # Number of busy cycles -system.cpu1.not_idle_fraction 0.016667 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.983333 # Percentage of idle cycles -system.cpu1.Branches 4459555 # Number of branches fetched +system.cpu1.committedInsts 23839695 # Number of instructions committed +system.cpu1.committedOps 29192667 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 25548618 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5779 # Number of float alu accesses +system.cpu1.num_func_calls 987959 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2987443 # number of instructions that are conditional controls +system.cpu1.num_int_insts 25548618 # number of integer instructions +system.cpu1.num_fp_insts 5779 # number of float instructions +system.cpu1.num_int_register_reads 48280801 # number of times the integer registers were read +system.cpu1.num_int_register_writes 17496069 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3771 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2012 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 86968126 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 11050847 # number of times the CC registers were written +system.cpu1.num_mem_refs 11166773 # number of memory refs +system.cpu1.num_load_insts 6206724 # Number of load instructions +system.cpu1.num_store_insts 4960049 # Number of store instructions +system.cpu1.num_idle_cycles 1771724648.110516 # Number of idle cycles +system.cpu1.num_busy_cycles 29983387.889484 # Number of busy cycles +system.cpu1.not_idle_fraction 0.016642 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.983358 # Percentage of idle cycles +system.cpu1.Branches 4459767 # Number of branches fetched system.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 18046643 61.66% 61.71% # Class of executed instruction -system.cpu1.op_class::IntMult 40424 0.14% 61.85% # Class of executed instruction +system.cpu1.op_class::IntAlu 18047467 61.65% 61.71% # Class of executed instruction +system.cpu1.op_class::IntMult 40427 0.14% 61.85% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction @@ -688,58 +978,58 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1539 0.01% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1550 0.01% 61.85% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction -system.cpu1.op_class::MemRead 6206289 21.20% 83.06% # Class of executed instruction -system.cpu1.op_class::MemWrite 4959666 16.94% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 6206724 21.20% 83.06% # Class of executed instruction +system.cpu1.op_class::MemWrite 4960049 16.94% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 29270113 # Class of executed instruction +system.cpu1.op_class::total 29271769 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48301 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 442993 # number of replacements -system.cpu1.icache.tags.tagsinuse 472.644505 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 24184321 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 443505 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 54.529985 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 254679414000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.644505 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.923134 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.923134 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 48299 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 398154 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.812776 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 24230251 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 398666 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 60.778323 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 103932913000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.812776 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927369 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927369 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 257 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 25071331 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 25071331 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 24184321 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 24184321 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 24184321 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 24184321 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 24184321 # number of overall hits -system.cpu1.icache.overall_hits::total 24184321 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 443505 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 443505 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 443505 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 443505 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 443505 # number of overall misses -system.cpu1.icache.overall_misses::total 443505 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 24627826 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 24627826 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 24627826 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 24627826 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 24627826 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 24627826 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018008 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.018008 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018008 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.018008 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018008 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.018008 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 49656500 # 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miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016187 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -749,79 +1039,215 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 274056 # number of replacements -system.cpu1.dcache.tags.tagsinuse 468.122166 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 9407683 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 274568 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 34.263581 # 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number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.tags.replacements 88565 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12390.036216 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 691452 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 104644 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.607660 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 876305009500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 6229.071421 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 8.886003 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.649559 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3323.104999 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2826.324234 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.380192 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000542 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000162 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.202826 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.172505 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.756228 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9480 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2833 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15740589 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15740589 # 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number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 263 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 22734 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 119840 # number of overall misses +system.cpu1.l2cache.overall_misses::total 143186 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 6245 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2963 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 398398 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 202901 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 610507 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 209707 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 209707 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 18773 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 18773 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 11227 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 11227 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 116777 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 116777 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 6245 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2963 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 398398 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 319678 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 727284 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 6245 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2963 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 398398 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 319678 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 727284 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.088761 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.057064 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.253079 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.122351 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998881 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998881 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.586502 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.586502 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.088761 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.057064 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.374877 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.196878 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.088761 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.057064 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.374877 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.196878 # miss rate for overall accesses +system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.l2cache.fast_writes 0 # number of fast writes performed +system.cpu1.l2cache.cache_copies 0 # number of cache copies performed +system.cpu1.l2cache.writebacks::writebacks 61322 # number of writebacks +system.cpu1.l2cache.writebacks::total 61322 # number of writebacks +system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.tags.replacements 299305 # number of replacements +system.cpu1.dcache.tags.tagsinuse 464.628152 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 9384005 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 299817 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 31.299109 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 94422670000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 464.628152 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.907477 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.907477 # 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number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 143554 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 143554 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 130048 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 130048 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 27770 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 27770 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10527 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10527 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9468 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9468 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 273602 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 273602 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 301372 # number of overall misses -system.cpu1.dcache.overall_misses::total 301372 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755511 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4755511 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673443 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4673443 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.tags.tag_accesses 19727044 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 19727044 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4592285 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4592285 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4538287 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4538287 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35329 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 35329 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94231 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 94231 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93873 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 93873 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9130572 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9130572 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9165901 # number of overall hits +system.cpu1.dcache.overall_hits::total 9165901 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 163656 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 163656 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 135550 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 135550 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 28044 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 28044 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11201 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11201 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11227 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 11227 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 299206 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 299206 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 327250 # number of overall misses +system.cpu1.dcache.overall_misses::total 327250 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755941 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4755941 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673837 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4673837 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105466 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105466 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 9428954 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 9428954 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 9492327 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 9492327 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.030187 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.030187 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027827 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027827 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.438199 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.438199 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099814 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.099814 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090064 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090064 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029017 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031749 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.031749 # miss rate for overall accesses +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105432 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 105432 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105100 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105100 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 9429778 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 9429778 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 9493151 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 9493151 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034411 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.034411 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029002 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029002 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.442523 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.442523 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106239 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106239 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106822 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106822 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031730 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031730 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034472 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034472 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -830,9 +1256,45 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 249941 # number of writebacks -system.cpu1.dcache.writebacks::total 249941 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 209707 # number of writebacks +system.cpu1.dcache.writebacks::total 209707 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 1728836 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1728836 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 3546 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 3546 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 209707 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 18773 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 11227 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 30000 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 116777 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 116777 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 797550 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 3132383 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12644 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25448 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3968025 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25515060 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36101346 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25288 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50896 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 61692590 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 259574 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1204043 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.188487 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.391100 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 977097 81.15% 81.15% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 226946 18.85% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1204043 # Request fanout histogram system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 511b86cf1..227319fff 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,18 +1,30 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.321351 # Number of seconds simulated -sim_ticks 2321351025500 # Number of ticks simulated -final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.321335 # Number of seconds simulated +sim_ticks 2321335404000 # Number of ticks simulated +final_tick 2321335404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 818788 # Simulator instruction rate (inst/s) -host_op_rate 985991 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31464875718 # Simulator tick rate (ticks/s) -host_mem_usage 430844 # Number of bytes of host memory used -host_seconds 73.78 # Real time elapsed on the host +host_inst_rate 1308981 # Simulator instruction rate (inst/s) +host_op_rate 1576286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50301976363 # Simulator tick rate (ticks/s) +host_mem_usage 455960 # Number of bytes of host memory used +host_seconds 46.15 # Real time elapsed on the host sim_insts 60406834 # Number of instructions simulated sim_ops 72742429 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory @@ -33,47 +45,127 @@ system.physmem.num_reads::total 13921575 # Nu system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47429803 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 303882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3907997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1595567 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1299164 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2894732 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1595567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 303884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3908023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51641930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1595578 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1299173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2894751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1595578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47429803 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5207161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54536314 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55568847 # Throughput (bytes/s) -system.membus.data_through_bus 128994799 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.physmem.bw_total::cpu.inst 303884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5207196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54536681 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 14973631 # Transaction distribution +system.membus.trans_dist::ReadResp 14973631 # Transaction distribution +system.membus.trans_dist::WriteReq 763122 # Transaction distribution +system.membus.trans_dist::WriteResp 763122 # Transaction distribution +system.membus.trans_dist::Writeback 57873 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution +system.membus.trans_dist::ReadExReq 131874 # Transaction distribution +system.membus.trans_dist::ReadExResp 131874 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4279041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 27525120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 27525120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31804161 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390127 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 6720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16497448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18894319 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 110100480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 110100480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 128994799 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214751 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 214751 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 214751 # Request fanout histogram system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48459111 # Throughput (bytes/s) -system.iobus.data_through_bus 112490607 # Total data (bytes) +system.iobus.trans_dist::ReadReq 14945841 # Transaction distribution +system.iobus.trans_dist::ReadResp 14945841 # Transaction distribution +system.iobus.trans_dist::WriteReq 8131 # Transaction distribution +system.iobus.trans_dist::WriteResp 8131 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7900 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 984 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382824 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 27525120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 27525120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 29907944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39247 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15800 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390127 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 110100480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 110100480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 112490607 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -98,7 +190,7 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13142244 # DTB read hits +system.cpu.dtb.read_hits 13142243 # DTB read hits system.cpu.dtb.read_misses 7297 # DTB read misses system.cpu.dtb.write_hits 11216207 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses @@ -111,12 +203,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13149541 # DTB read accesses +system.cpu.dtb.read_accesses 13149540 # DTB read accesses system.cpu.dtb.write_accesses 11218388 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 24358451 # DTB hits +system.cpu.dtb.hits 24358450 # DTB hits system.cpu.dtb.misses 9478 # DTB misses -system.cpu.dtb.accesses 24367929 # DTB accesses +system.cpu.dtb.accesses 24367928 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -159,7 +251,7 @@ system.cpu.itb.inst_accesses 61434478 # IT system.cpu.itb.hits 61430007 # DTB hits system.cpu.itb.misses 4471 # DTB misses system.cpu.itb.accesses 61434478 # DTB accesses -system.cpu.numCycles 4642702052 # number of cpu cycles simulated +system.cpu.numCycles 4642753590 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60406834 # Number of instructions committed @@ -179,10 +271,10 @@ system.cpu.num_cc_register_writes 28977741 # nu system.cpu.num_mem_refs 25221274 # number of memory refs system.cpu.num_load_insts 13499937 # Number of load instructions system.cpu.num_store_insts 11721337 # Number of store instructions -system.cpu.num_idle_cycles 4568843017.980124 # Number of idle cycles -system.cpu.num_busy_cycles 73859034.019877 # Number of busy cycles -system.cpu.not_idle_fraction 0.015909 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.984091 # Percentage of idle cycles +system.cpu.num_idle_cycles 4568976022.512934 # Number of idle cycles +system.cpu.num_busy_cycles 73777567.487067 # Number of busy cycles +system.cpu.not_idle_fraction 0.015891 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.984109 # Percentage of idle cycles system.cpu.Branches 10298517 # Number of branches fetched system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction @@ -221,35 +313,35 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 72875708 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 850515 # number of replacements -system.cpu.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60581740 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.689593 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 850504 # number of replacements +system.cpu.icache.tags.tagsinuse 511.689630 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60581751 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 851016 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 71.187558 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 5451547500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.689630 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62283794 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62283794 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60581740 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60581740 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60581740 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60581740 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60581740 # number of overall hits -system.cpu.icache.overall_hits::total 60581740 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 851027 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 851027 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 851027 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 851027 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 851027 # number of overall misses -system.cpu.icache.overall_misses::total 851027 # number of overall misses +system.cpu.icache.tags.tag_accesses 62283783 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62283783 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60581751 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60581751 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60581751 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60581751 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60581751 # number of overall hits +system.cpu.icache.overall_hits::total 60581751 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 851016 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 851016 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 851016 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 851016 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 851016 # number of overall misses +system.cpu.icache.overall_misses::total 851016 # number of overall misses system.cpu.icache.ReadReq_accesses::cpu.inst 61432767 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61432767 # number of demand (read+write) accesses @@ -272,21 +364,21 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 62250 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50006.834636 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1669916 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 50006.820137 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1669876 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 127635 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.083527 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36897.866975 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959775 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993971 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.476656 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.537259 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563017 # Average percentage of cache occupancy +system.cpu.l2cache.tags.avg_refs 13.083214 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2306275686000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36897.819647 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959772 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993972 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.485209 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.561537 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563016 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107032 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.092934 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107033 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.092935 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.763044 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id @@ -298,29 +390,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9281 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52125 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17035648 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17035648 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7541 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 17035355 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17035355 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7540 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 838793 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 366790 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1216275 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 592642 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 592642 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 838782 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 366774 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1216247 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 592630 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 592630 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113706 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113706 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7541 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113709 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113709 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7540 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 838793 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 480496 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1329981 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7541 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 838782 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 480483 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1329956 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7540 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3151 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 838793 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 480496 # number of overall hits -system.cpu.l2cache.overall_hits::total 1329981 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 838782 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 480483 # number of overall hits +system.cpu.l2cache.overall_hits::total 1329956 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10608 # number of ReadReq misses @@ -340,46 +432,46 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 3 system.cpu.l2cache.overall_misses::cpu.inst 10608 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 143345 # number of overall misses system.cpu.l2cache.overall_misses::total 153961 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7546 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7545 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 849401 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 376661 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1236762 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 592642 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 592642 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 849390 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 376645 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1236734 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 592630 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 592630 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2943 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7546 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247183 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247183 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7545 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 849401 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 623841 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1483942 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7546 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 849390 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 623828 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1483917 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7545 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 849401 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 623841 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1483942 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 849390 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 623828 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1483917 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.016565 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991165 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539987 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.539987 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539981 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.539981 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229778 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103751 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229783 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103753 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229778 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103751 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229783 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103753 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,11 +483,11 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 57873 # number of writebacks system.cpu.l2cache.writebacks::total 57873 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 623329 # number of replacements +system.cpu.dcache.tags.replacements 623316 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21798545 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.942469 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21798557 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 623828 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.943217 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -405,36 +497,36 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 291 system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 90313385 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 90313385 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11240226 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11240226 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9961316 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9961316 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 90313368 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 90313368 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11240238 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11240238 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9961313 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9961313 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236008 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236008 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236011 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236011 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21201542 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21201542 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21312398 # number of overall hits -system.cpu.dcache.overall_hits::total 21312398 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 292030 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 292030 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250123 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250123 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 21201551 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21201551 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21312407 # number of overall hits +system.cpu.dcache.overall_hits::total 21312407 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 292017 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 292017 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250126 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250126 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11189 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11189 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 542153 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 542153 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 615595 # number of overall misses -system.cpu.dcache.overall_misses::total 615595 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 11532256 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11186 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11186 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 542143 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 542143 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 615585 # number of overall misses +system.cpu.dcache.overall_misses::total 615585 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 11532255 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11532255 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses) @@ -443,20 +535,20 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247197 system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21743695 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21927993 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21927993 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025323 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024494 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024494 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 21743694 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21743694 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21927992 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21927992 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025322 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025322 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045263 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045263 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024934 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045251 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045251 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024933 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024933 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -467,12 +559,44 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 592642 # number of writebacks -system.cpu.dcache.writebacks::total 592642 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592630 # number of writebacks +system.cpu.dcache.writebacks::total 592630 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 59392167 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 137870067 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 2445766 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2445766 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 592630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2943 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2943 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247183 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5740322 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37190 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7510658 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54491548 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83266131 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 35704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74380 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 137867763 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2097938 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2097938 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2097938 # Request fanout histogram system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 051c13810..73c076f14 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,167 +1,189 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.194312 # Number of seconds simulated -sim_ticks 1194312178000 # Number of ticks simulated -final_tick 1194312178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.675181 # Number of seconds simulated +sim_ticks 2675180779000 # Number of ticks simulated +final_tick 2675180779000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 475403 # Simulator instruction rate (inst/s) -host_op_rate 567868 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9241250441 # Simulator tick rate (ticks/s) -host_mem_usage 438040 # Number of bytes of host memory used -host_seconds 129.24 # Real time elapsed on the host -sim_insts 61439698 # Number of instructions simulated -sim_ops 73389630 # Number of ops (including micro ops) simulated +host_inst_rate 485184 # Simulator instruction rate (inst/s) +host_op_rate 579312 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20736099933 # Simulator tick rate (ticks/s) +host_mem_usage 486856 # Number of bytes of host memory used +host_seconds 129.01 # Real time elapsed on the host +sim_insts 62593972 # Number of instructions simulated +sim_ops 74737529 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393932 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4710012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323460 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4796088 # Number of bytes read from this memory -system.physmem.bytes_read::total 62128516 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393932 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323460 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4097216 # Number of bytes written to this memory +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 120908 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 513788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 6659968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 37828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 531832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 3262144 # Number of bytes read from this memory +system.physmem.bytes_read::total 135383236 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 120908 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 37828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 158736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4300032 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7124560 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12383 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73653 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5145 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74957 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654210 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64019 # Number of write requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7329168 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 8117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 8087 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 104062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 50971 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15712287 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 67188 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820855 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43459753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 329840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3943703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 270834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4015774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52020332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 329840 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 270834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 600674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3430607 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2520567 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5965408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3430607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43459753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 329840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3957937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 270834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6536341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57985740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654210 # Number of read requests accepted -system.physmem.writeReqs 820855 # Number of write requests accepted -system.physmem.readBursts 6654210 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 820855 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425838464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue -system.physmem.bytesWritten 7136448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62128516 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7124560 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709321 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12079 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415236 # Per bank write bursts -system.physmem.perBankRdBursts::1 415218 # Per bank write bursts -system.physmem.perBankRdBursts::2 415240 # Per bank write bursts -system.physmem.perBankRdBursts::3 415658 # Per bank write bursts -system.physmem.perBankRdBursts::4 422402 # Per bank write bursts -system.physmem.perBankRdBursts::5 415506 # Per bank write bursts -system.physmem.perBankRdBursts::6 415779 # Per bank write bursts -system.physmem.perBankRdBursts::7 415682 # Per bank write bursts -system.physmem.perBankRdBursts::8 416047 # Per bank write bursts -system.physmem.perBankRdBursts::9 415577 # Per bank write bursts -system.physmem.perBankRdBursts::10 415398 # Per bank write bursts -system.physmem.perBankRdBursts::11 414862 # Per bank write bursts -system.physmem.perBankRdBursts::12 415007 # Per bank write bursts -system.physmem.perBankRdBursts::13 415552 # Per bank write bursts -system.physmem.perBankRdBursts::14 415496 # Per bank write bursts -system.physmem.perBankRdBursts::15 415066 # Per bank write bursts -system.physmem.perBankWrBursts::0 6763 # Per bank write bursts -system.physmem.perBankWrBursts::1 6728 # Per bank write bursts -system.physmem.perBankWrBursts::2 6819 # Per bank write bursts -system.physmem.perBankWrBursts::3 7055 # Per bank write bursts -system.physmem.perBankWrBursts::4 7301 # Per bank write bursts -system.physmem.perBankWrBursts::5 7028 # Per bank write bursts -system.physmem.perBankWrBursts::6 7316 # Per bank write bursts -system.physmem.perBankWrBursts::7 7231 # Per bank write bursts -system.physmem.perBankWrBursts::8 7485 # Per bank write bursts -system.physmem.perBankWrBursts::9 7107 # Per bank write bursts -system.physmem.perBankWrBursts::10 7000 # Per bank write bursts -system.physmem.perBankWrBursts::11 6549 # Per bank write bursts -system.physmem.perBankWrBursts::12 6696 # Per bank write bursts -system.physmem.perBankWrBursts::13 6902 # Per bank write bursts -system.physmem.perBankWrBursts::14 6960 # Per bank write bursts -system.physmem.perBankWrBursts::15 6567 # Per bank write bursts +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824472 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46447798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 48 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 96 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 45196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 192057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2489539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 48 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 198802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 1219411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50607135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 45196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14140 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 59337 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1607380 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6355 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1125956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2739691 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1607380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46447798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 48 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 96 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 45196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 198412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2489539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 48 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1324758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 1219411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53346826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15712287 # Number of read requests accepted +system.physmem.writeReqs 824472 # Number of write requests accepted +system.physmem.readBursts 15712287 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 824472 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1005465984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 120384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7344256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 135383236 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7329168 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1881 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709695 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15472 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 981539 # Per bank write bursts +system.physmem.perBankRdBursts::1 981448 # Per bank write bursts +system.physmem.perBankRdBursts::2 981211 # Per bank write bursts +system.physmem.perBankRdBursts::3 981521 # Per bank write bursts +system.physmem.perBankRdBursts::4 988300 # Per bank write bursts +system.physmem.perBankRdBursts::5 981533 # Per bank write bursts +system.physmem.perBankRdBursts::6 981210 # Per bank write bursts +system.physmem.perBankRdBursts::7 981071 # Per bank write bursts +system.physmem.perBankRdBursts::8 981831 # Per bank write bursts +system.physmem.perBankRdBursts::9 982015 # Per bank write bursts +system.physmem.perBankRdBursts::10 981421 # Per bank write bursts +system.physmem.perBankRdBursts::11 980878 # Per bank write bursts +system.physmem.perBankRdBursts::12 981926 # Per bank write bursts +system.physmem.perBankRdBursts::13 981948 # Per bank write bursts +system.physmem.perBankRdBursts::14 981516 # Per bank write bursts +system.physmem.perBankRdBursts::15 981038 # Per bank write bursts +system.physmem.perBankWrBursts::0 7155 # Per bank write bursts +system.physmem.perBankWrBursts::1 7293 # Per bank write bursts +system.physmem.perBankWrBursts::2 6957 # Per bank write bursts +system.physmem.perBankWrBursts::3 6994 # Per bank write bursts +system.physmem.perBankWrBursts::4 7537 # Per bank write bursts +system.physmem.perBankWrBursts::5 7187 # Per bank write bursts +system.physmem.perBankWrBursts::6 7207 # Per bank write bursts +system.physmem.perBankWrBursts::7 7058 # Per bank write bursts +system.physmem.perBankWrBursts::8 7329 # Per bank write bursts +system.physmem.perBankWrBursts::9 7596 # Per bank write bursts +system.physmem.perBankWrBursts::10 7177 # Per bank write bursts +system.physmem.perBankWrBursts::11 6681 # Per bank write bursts +system.physmem.perBankWrBursts::12 7505 # Per bank write bursts +system.physmem.perBankWrBursts::13 7329 # Per bank write bursts +system.physmem.perBankWrBursts::14 7034 # Per bank write bursts +system.physmem.perBankWrBursts::15 6715 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1194307723500 # Total gap between requests +system.physmem.totGap 2675178052500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6799 # Read request sizes (log2) -system.physmem.readPktSize::3 6488089 # Read request sizes (log2) +system.physmem.readPktSize::3 15532057 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159322 # Read request sizes (log2) +system.physmem.readPktSize::6 173431 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64019 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 572550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 410650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 412558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 460055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 417389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 445707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1151151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1116358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1442650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 62467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 48974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 43130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 67188 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1100287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 996591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 996926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1111424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1006011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1072049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2766642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2669294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3474563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 133275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 114946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 106575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 103058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see @@ -180,47 +202,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -229,394 +251,422 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 473292 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 914.815615 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 785.169464 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 288.643252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25022 5.29% 5.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21566 4.56% 9.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5869 1.24% 11.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2391 0.51% 11.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2344 0.50% 12.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1629 0.34% 12.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4093 0.86% 13.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 899 0.19% 13.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 409479 86.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 473292 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6481 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1026.648974 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 26505.494009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6473 99.88% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6481 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.205215 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.176618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.984217 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2581 39.82% 39.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.23% 40.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3862 59.59% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 20 0.31% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6481 # Writes before turning the bus around for reads -system.physmem.totQLat 170730095750 # Total ticks spent queuing -system.physmem.totMemAccLat 295487458250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33268630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25659.32 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1051606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 963.108084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 883.927529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 220.726845 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 33004 3.14% 3.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22001 2.09% 5.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9307 0.89% 6.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2514 0.24% 6.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3272 0.31% 6.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2167 0.21% 6.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8722 0.83% 7.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1051 0.10% 7.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 969568 92.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1051606 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6601 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2380.003939 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98592.588392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6595 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6601 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6601 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.384336 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.341066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.250693 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2463 37.31% 37.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 32 0.48% 37.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3686 55.84% 93.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 215 3.26% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 85 1.29% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 0.76% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 28 0.42% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.21% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 7 0.11% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6601 # Writes before turning the bus around for reads +system.physmem.totQLat 408788863752 # Total ticks spent queuing +system.physmem.totMemAccLat 703358976252 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78552030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26020.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44409.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 52.02 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44770.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 375.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.61 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.83 # Data bus utilization in percentage -system.physmem.busUtilRead 2.79 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 4.36 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing -system.physmem.readRowHits 6199598 # Number of row buffer hits during reads -system.physmem.writeRowHits 92343 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.79 # Row buffer hit rate for writes -system.physmem.avgGap 159772.22 # Average gap between requests -system.physmem.pageHitRate 93.00 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 945808643750 # Time in different power states -system.physmem.memoryStateTime::REF 39880620000 # Time in different power states +system.physmem.busUtil 2.96 # Data bus utilization in percentage +system.physmem.busUtilRead 2.94 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 6.50 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.70 # Average write queue length when enqueuing +system.physmem.readRowHits 14689438 # Number of row buffer hits during reads +system.physmem.writeRowHits 84116 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.29 # Row buffer hit rate for writes +system.physmem.avgGap 161771.61 # Average gap between requests +system.physmem.pageHitRate 93.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2326940534750 # Time in different power states +system.physmem.memoryStateTime::REF 89330020000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 208620525000 # Time in different power states +system.physmem.memoryStateTime::ACT 258906121500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 60005732 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703348 # Transaction distribution -system.membus.trans_dist::ReadResp 7703348 # Transaction distribution -system.membus.trans_dist::WriteReq 767581 # Transaction distribution -system.membus.trans_dist::WriteResp 767581 # Transaction distribution -system.membus.trans_dist::Writeback 64019 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31325 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17234 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12079 # Transaction distribution -system.membus.trans_dist::ReadExReq 137481 # Transaction distribution -system.membus.trans_dist::ReadExResp 137066 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382642 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 16891737 # Transaction distribution +system.membus.trans_dist::ReadResp 16891737 # Transaction distribution +system.membus.trans_dist::WriteReq 769090 # Transaction distribution +system.membus.trans_dist::WriteResp 769090 # Transaction distribution +system.membus.trans_dist::Writeback 67188 # Transaction distribution +system.membus.trans_dist::UpgradeReq 56135 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 22757 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15472 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 15580 # Transaction distribution +system.membus.trans_dist::ReadExResp 8709 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384390 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971036 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4364934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17341062 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389989 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17348564 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19761065 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71665577 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71665577 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224785500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2098 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2043502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4443432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35507496 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4196 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18456148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 20879924 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 145136180 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 70292 # Total snoops (count) +system.membus.snoop_fanout::samples 326383 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 326383 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 326383 # Request fanout histogram +system.membus.reqLayer0.occupancy 1567209495 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9231500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11789999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 778500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 2092500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9212282000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5079172023 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 16050388750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.reqLayer6.occupancy 18080219999 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4994463970 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 38410223885 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69203 # number of replacements -system.l2c.tags.tagsinuse 52959.316379 # Cycle average of tags in use -system.l2c.tags.total_refs 1672724 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134375 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.448179 # Average number of references to valid blocks. +system.l2c.tags.replacements 91391 # number of replacements +system.l2c.tags.tagsinuse 54779.294121 # Cycle average of tags in use +system.l2c.tags.total_refs 364235 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 156090 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.333493 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40136.915421 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3716.167205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4233.542603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.741623 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001622 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2809.362324 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2060.583626 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.612441 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056704 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064599 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031442 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808095 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 8096.170170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.060665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.035962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 869.411373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1869.125081 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29277.356218 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.888363 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 410.348906 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3214.362362 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11039.535021 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.123538 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.013266 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.028521 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.446737 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.006261 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.049047 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.168450 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.835866 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 51568 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 13123 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4964 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 46576 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8176 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55031 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17204185 # Number of tag accesses -system.l2c.tags.data_accesses 17204185 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 3944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1786 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419390 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205855 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5333 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1846 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464270 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143434 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1245858 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 570720 # number of Writeback hits -system.l2c.Writeback_hits::total 570720 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1291 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1814 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 97 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 311 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56339 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52717 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109056 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3944 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1786 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419390 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262194 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5333 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1846 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464270 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196151 # number of demand (read+write) hits -system.l2c.demand_hits::total 1354914 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3944 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1786 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419390 # number of overall hits -system.l2c.overall_hits::cpu0.data 262194 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5333 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1846 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464270 # number of overall hits -system.l2c.overall_hits::cpu1.data 196151 # number of overall hits -system.l2c.overall_hits::total 1354914 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5741 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7844 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5048 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3616 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22257 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4858 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3744 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8602 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 567 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 472 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1039 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67076 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72428 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139504 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5741 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74920 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5048 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76044 # number of demand (read+write) misses -system.l2c.demand_misses::total 161761 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5741 # number of overall misses -system.l2c.overall_misses::cpu0.data 74920 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5048 # number of overall misses -system.l2c.overall_misses::cpu1.data 76044 # number of overall misses -system.l2c.overall_misses::total 161761 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 405931250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 580562999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 320500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 360408000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 277006500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1624485749 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 12826446 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12064984 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24891430 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1764424 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2465394 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4229818 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4470263914 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64144.911504 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60422.020983 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.865377 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.762019 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.913857 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.109347 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.472458 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.548604 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53749.881836 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59393.523292 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56679.960281 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63612.049707 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65506.557783 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 83986.890786 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10043.574479 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.066839 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.987400 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10112.391602 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.746628 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.249887 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60750.569019 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59271.077532 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60028.558346 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54565.083729 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59619.458537 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57194.817495 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54565.083729 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59619.458537 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57194.817495 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -810,67 +872,53 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119643708 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2534658 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2534658 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767581 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767581 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 570720 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30701 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17545 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48246 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260694 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260694 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864108 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226294 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6184 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12819 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 939372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6173 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15243 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7670949 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27234976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41362613 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15780 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30036788 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39599456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7388 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21348 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138285501 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138285501 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4606436 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4757764712 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1924888432 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1752701680 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396499 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8876994 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2115350205 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2925844707 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) -system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 9906999 # Layer occupancy (ticks) -system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45460895 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671423 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671423 # Transaction distribution -system.iobus.trans_dist::WriteReq 7962 # Transaction distribution -system.iobus.trans_dist::WriteResp 7962 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8040 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 1633013 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1633009 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769090 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769090 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 208041 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 61292 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 23072 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 84364 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 39 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 23321 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 23321 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2956029 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2099720 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5055749 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 25795270 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15582958 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41378228 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 171942 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 753795 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 753795 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 753795 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2576673570 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2390227339 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1329617427 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 16716140 # Transaction distribution +system.iobus.trans_dist::ReadResp 16716140 # Transaction distribution +system.iobus.trans_dist::WriteReq 8087 # Transaction distribution +system.iobus.trans_dist::WriteResp 8087 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8820 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -887,54 +935,53 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382642 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358770 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40317 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389989 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294501 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294501 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21416000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 2384390 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33448454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40731 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2392696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 126648952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 21726000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4026000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4416000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) @@ -965,12 +1012,12 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374680000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16364250250 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2376303000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 39178496115 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -994,25 +1041,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6063582 # DTB read hits -system.cpu0.dtb.read_misses 3748 # DTB read misses -system.cpu0.dtb.write_hits 5648980 # DTB write hits -system.cpu0.dtb.write_misses 807 # DTB write misses +system.cpu0.dtb.read_hits 7131006 # DTB read hits +system.cpu0.dtb.read_misses 3644 # DTB read misses +system.cpu0.dtb.write_hits 6127729 # DTB write hits +system.cpu0.dtb.write_misses 663 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1893 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 116 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6067330 # DTB read accesses -system.cpu0.dtb.write_accesses 5649787 # DTB write accesses +system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7134650 # DTB read accesses +system.cpu0.dtb.write_accesses 6128392 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 11712562 # DTB hits -system.cpu0.dtb.misses 4555 # DTB misses -system.cpu0.dtb.accesses 11717117 # DTB accesses +system.cpu0.dtb.hits 13258735 # DTB hits +system.cpu0.dtb.misses 4307 # DTB misses +system.cpu0.dtb.accesses 13263042 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1034,8 +1081,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 29557926 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.itb.inst_hits 31182741 # ITB inst hits +system.cpu0.itb.inst_misses 2176 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1044,132 +1091,130 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1281 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29560131 # ITB inst accesses -system.cpu0.itb.hits 29557926 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29560131 # DTB accesses -system.cpu0.numCycles 2388624356 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 31184917 # ITB inst accesses +system.cpu0.itb.hits 31182741 # DTB hits +system.cpu0.itb.misses 2176 # DTB misses +system.cpu0.itb.accesses 31184917 # DTB accesses +system.cpu0.numCycles 5349463018 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28859743 # Number of instructions committed -system.cpu0.committedOps 34624628 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30439288 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241573 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4174263 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30439288 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 53589242 # number of times the integer registers were read -system.cpu0.num_int_register_writes 19764786 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 123695766 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 15045730 # number of times the CC registers were written -system.cpu0.num_mem_refs 12225186 # number of memory refs -system.cpu0.num_load_insts 6245915 # Number of load instructions -system.cpu0.num_store_insts 5979271 # Number of store instructions -system.cpu0.num_idle_cycles 2246427873.598119 # Number of idle cycles -system.cpu0.num_busy_cycles 142196482.401881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles -system.cpu0.Branches 5599312 # Number of branches fetched -system.cpu0.op_class::No_OpClass 14563 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 22957352 65.14% 65.18% # Class of executed instruction -system.cpu0.op_class::IntMult 43755 0.12% 65.31% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 692 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::MemRead 6245915 17.72% 83.03% # Class of executed instruction -system.cpu0.op_class::MemWrite 5979271 16.97% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30507218 # Number of instructions committed +system.cpu0.committedOps 36803230 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 32859018 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses +system.cpu0.num_func_calls 1290775 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3957686 # number of instructions that are conditional controls +system.cpu0.num_int_insts 32859018 # number of integer instructions +system.cpu0.num_fp_insts 5449 # number of float instructions +system.cpu0.num_int_register_reads 60131579 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21902535 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133610661 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 14490121 # number of times the CC registers were written +system.cpu0.num_mem_refs 13795466 # number of memory refs +system.cpu0.num_load_insts 7343231 # Number of load instructions +system.cpu0.num_store_insts 6452235 # Number of store instructions +system.cpu0.num_idle_cycles 4898257252.279955 # Number of idle cycles +system.cpu0.num_busy_cycles 451205765.720045 # Number of busy cycles +system.cpu0.not_idle_fraction 0.084346 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.915654 # Percentage of idle cycles +system.cpu0.Branches 5660514 # Number of branches fetched +system.cpu0.op_class::No_OpClass 16321 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 23591543 62.99% 63.03% # Class of executed instruction +system.cpu0.op_class::IntMult 47189 0.13% 63.16% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1591 0.00% 63.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 63.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.17% # Class of executed instruction +system.cpu0.op_class::MemRead 7343231 19.61% 82.77% # Class of executed instruction +system.cpu0.op_class::MemWrite 6452235 17.23% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 35241548 # Class of executed instruction +system.cpu0.op_class::total 37452110 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 47055 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 425168 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.375466 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29132228 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 425680 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.436920 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 75988011000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.375466 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994874 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994874 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 51950 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 369506 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.465010 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 30812705 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 370018 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 83.273530 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10201796750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.465010 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998955 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998955 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 506 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29983590 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29983590 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29132228 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29132228 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29132228 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29132228 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29132228 # number of overall hits -system.cpu0.icache.overall_hits::total 29132228 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425681 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425681 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425681 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425681 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425681 # number of overall misses -system.cpu0.icache.overall_misses::total 425681 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5899766682 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5899766682 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5899766682 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5899766682 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5899766682 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5899766682 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29557909 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29557909 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29557909 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29557909 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29557909 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29557909 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014402 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014402 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014402 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014402 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014402 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014402 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13859.595993 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13859.595993 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13859.595993 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13859.595993 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 62735467 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62735467 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 30812705 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 30812705 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30812705 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 30812705 # 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number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 3209345752 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 3209345752 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 31182724 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 31182724 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 31182724 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 31182724 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 31182724 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 31182724 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011866 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011866 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011866 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011866 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011866 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011866 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8673.462044 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8673.462044 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8673.462044 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8673.462044 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8673.462044 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8673.462044 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1178,136 +1223,471 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425681 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425681 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425681 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425681 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425681 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425681 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5046160318 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5046160318 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5046160318 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5046160318 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5046160318 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5046160318 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 442165750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 442165750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 442165750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 442165750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014402 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014402 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014402 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11854.323585 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11854.323585 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11854.323585 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 370019 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 370019 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 370019 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 370019 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 370019 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 370019 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2653955748 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 2653955748 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2653955748 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 2653955748 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2653955748 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 2653955748 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 531257750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 531257750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 531257750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 531257750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011866 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011866 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011866 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7172.485056 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7172.485056 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7172.485056 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 329792 # number of replacements -system.cpu0.dcache.tags.tagsinuse 452.041842 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11239100 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 330304 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.026533 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 671364250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 452.041842 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.882894 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.882894 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 46848154 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 46848154 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5514035 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5514035 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5340154 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5340154 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 64966 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 64966 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148024 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 148024 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149636 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149636 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10854189 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10854189 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10919155 # number of overall hits -system.cpu0.dcache.overall_hits::total 10919155 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 179189 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 179189 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 145422 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 145422 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 62829 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 62829 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9439 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9439 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7485 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7485 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 324611 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 324611 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 387440 # number of overall misses -system.cpu0.dcache.overall_misses::total 387440 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2350643732 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 2350643732 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5817567140 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5817567140 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94706749 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 94706749 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44450567 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44450567 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8168210872 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8168210872 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8168210872 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8168210872 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5693224 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5693224 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5485576 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5485576 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 127795 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 127795 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157463 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157463 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157121 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157121 # 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average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.557474 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.557474 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5938.619506 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5938.619506 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25163.074794 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25163.074794 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21082.518253 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21082.518253 # average overall miss latency +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 4129417 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 113341 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 3763718 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 300 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 22 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 252036 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 312183 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.tags.replacements 213190 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16168.240053 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 848978 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 228702 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.712158 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 7921739000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4749.054127 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.517230 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.260718 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 821.211493 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1542.145038 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9052.051448 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.289859 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000215 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.050123 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.094125 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.552493 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.986831 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8284 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7219 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1260 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1944 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 5080 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1775 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1943 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3501 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.505615 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.440613 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 17864213 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 17864213 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4737 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 2374 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 361048 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 184302 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 552461 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 286361 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 286361 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 5612 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 5612 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 831 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 831 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 133749 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 133749 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 4737 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2374 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 361048 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 318051 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 686210 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4737 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2374 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 361048 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 318051 # number of overall hits +system.cpu0.l2cache.overall_hits::total 686210 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 146 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 8693 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 48360 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 57424 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 18405 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 18405 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10323 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 10323 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 24100 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 24100 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # 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number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4897000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3307000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 300815745 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 2108993418 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 2418013163 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4897000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3307000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 300815745 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 2108993418 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 2418013163 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 4962 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2520 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 369741 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 232662 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 609885 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 286363 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 286363 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 24017 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 24017 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11154 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 11154 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 157849 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 157849 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 4962 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 2520 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 369741 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 390511 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 767734 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 4962 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 2520 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 369741 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 390511 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 767734 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057937 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.023511 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.207855 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.094155 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.766332 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.766332 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.925498 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.925498 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.152678 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.152678 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057937 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.023511 # 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average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27208.187308 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15661.674980 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15661.674980 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19764.230941 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19764.230941 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 528000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 35502.498548 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 35502.498548 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21764.444444 # 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average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21816.315828 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36956.950356 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 355829 # number of replacements +system.cpu0.dcache.tags.tagsinuse 496.967445 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11721464 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 356159 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 32.910762 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 767187000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.967445 # 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number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 163545 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11682575 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11682575 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11811992 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11811992 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031174 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031174 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030844 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030844 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.515821 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.515821 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064162 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064162 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.068318 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.068318 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.031006 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.031006 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036317 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036317 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11981.415124 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11981.415124 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15418.649600 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15418.649600 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16777.100400 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16777.100400 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23395.582297 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23395.582297 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13724.519307 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13724.519307 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11588.774342 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11588.774342 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1316,78 +1696,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 305747 # number of writebacks -system.cpu0.dcache.writebacks::total 305747 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 4042 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 4042 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 4318 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 4318 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 4318 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 4318 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 178913 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 178913 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141380 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141380 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 48508 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 48508 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9439 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9439 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7483 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7483 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320293 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320293 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 368801 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 368801 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1988652518 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1988652518 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5320324110 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5320324110 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 853626758 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 853626758 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 75777251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 75777251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29483433 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29483433 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7308976628 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7308976628 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8162603386 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8162603386 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13564535750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13564535750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170801000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170801000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14735336750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14735336750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031426 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031426 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025773 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025773 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.379577 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.379577 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059944 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059944 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047626 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047626 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028652 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028652 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032618 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032618 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11115.192960 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11115.192960 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37631.377210 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37631.377210 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17597.649006 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17597.649006 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8028.101600 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8028.101600 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3940.055192 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3940.055192 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22819.657713 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22819.657713 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22132.812509 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22132.812509 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 286365 # number of writebacks +system.cpu0.dcache.writebacks::total 286365 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3418 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3418 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2438 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2438 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 5856 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 5856 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 5856 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 5856 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 175114 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 175114 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 181255 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 181255 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 47050 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 47050 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 10498 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10498 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11156 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11156 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 356369 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 356369 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 403419 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 403419 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1737360745 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1737360745 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2335118999 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2335118999 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 699675494 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 699675494 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 155125000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 155125000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 237977159 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 237977159 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1080000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1080000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 4072479744 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4072479744 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4772155238 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4772155238 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 185341734990 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 185341734990 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1669232496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1669232496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 187010967486 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 187010967486 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030577 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030577 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.030434 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.030434 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.363553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.363553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064162 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064162 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.068214 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.068214 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030504 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030504 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034153 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.034153 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 9921.312659 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9921.312659 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12883.059772 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12883.059772 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14870.892540 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14870.892540 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14776.624119 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14776.624119 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21331.763984 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21331.763984 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11427.704834 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11427.704834 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11829.277347 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11829.277347 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1395,6 +1779,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.trans_dist::ReadReq 1907557 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1767698 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 12543 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 12543 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 286363 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 331583 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 53089 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23925 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 60027 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 17 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 171374 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 163301 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 753056 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 3449820 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6852 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 13348 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4223076 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 23690016 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 48159078 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10080 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 19848 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 71879022 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 631972 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 1656253 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.339000 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.473370 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 1094784 66.10% 66.10% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 561469 33.90% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 1656253 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1405252745 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 72604500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 563408502 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1726182117 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 4332000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 8386000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1418,25 +1853,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7408792 # DTB read hits -system.cpu1.dtb.read_misses 3640 # DTB read misses -system.cpu1.dtb.write_hits 5825509 # DTB write hits -system.cpu1.dtb.write_misses 1435 # DTB write misses +system.cpu1.dtb.read_hits 6599972 # DTB read hits +system.cpu1.dtb.read_misses 3720 # DTB read misses +system.cpu1.dtb.write_hits 5539858 # DTB write hits +system.cpu1.dtb.write_misses 1581 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1866 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1672 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7412432 # DTB read accesses -system.cpu1.dtb.write_accesses 5826944 # DTB write accesses +system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6603692 # DTB read accesses +system.cpu1.dtb.write_accesses 5541439 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13234301 # DTB hits -system.cpu1.dtb.misses 5075 # DTB misses -system.cpu1.dtb.accesses 13239376 # DTB accesses +system.cpu1.dtb.hits 12139830 # DTB hits +system.cpu1.dtb.misses 5301 # DTB misses +system.cpu1.dtb.accesses 12145131 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1458,8 +1893,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 33190882 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.itb.inst_hits 32728613 # ITB inst hits +system.cpu1.itb.inst_misses 2200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1468,130 +1903,132 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33193053 # ITB inst accesses -system.cpu1.itb.hits 33190882 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33193053 # DTB accesses -system.cpu1.numCycles 2387219429 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 32730813 # ITB inst accesses +system.cpu1.itb.hits 32728613 # DTB hits +system.cpu1.itb.misses 2200 # DTB misses +system.cpu1.itb.accesses 32730813 # DTB accesses +system.cpu1.numCycles 5350361558 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32579955 # Number of instructions committed -system.cpu1.committedOps 38765002 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35167643 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962341 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3529676 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35167643 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 64976079 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23977665 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 139669414 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 14465628 # number of times the CC registers were written -system.cpu1.num_mem_refs 13620676 # number of memory refs -system.cpu1.num_load_insts 7578910 # Number of load instructions -system.cpu1.num_store_insts 6041766 # Number of store instructions -system.cpu1.num_idle_cycles 1873842319.884373 # Number of idle cycles -system.cpu1.num_busy_cycles 513377109.115627 # Number of busy cycles -system.cpu1.not_idle_fraction 0.215052 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.784948 # Percentage of idle cycles -system.cpu1.Branches 4944984 # Number of branches fetched -system.cpu1.op_class::No_OpClass 14265 0.04% 0.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 25564023 65.13% 65.17% # Class of executed instruction -system.cpu1.op_class::IntMult 50133 0.13% 65.29% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1482 0.00% 65.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.30% # Class of executed instruction -system.cpu1.op_class::MemRead 7578910 19.31% 84.61% # Class of executed instruction -system.cpu1.op_class::MemWrite 6041766 15.39% 100.00% # Class of executed instruction +system.cpu1.committedInsts 32086754 # Number of instructions committed +system.cpu1.committedOps 37934299 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 33961237 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses +system.cpu1.num_func_calls 973285 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3888456 # number of instructions that are conditional controls +system.cpu1.num_int_insts 33961237 # number of integer instructions +system.cpu1.num_fp_insts 4436 # number of float instructions +system.cpu1.num_int_register_reads 60527961 # number of times the integer registers were read +system.cpu1.num_int_register_writes 22681940 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 134686779 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 15567897 # number of times the CC registers were written +system.cpu1.num_mem_refs 12531559 # number of memory refs +system.cpu1.num_load_insts 6744563 # Number of load instructions +system.cpu1.num_store_insts 5786996 # Number of store instructions +system.cpu1.num_idle_cycles 5182201093.372063 # Number of idle cycles +system.cpu1.num_busy_cycles 168160464.627937 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031430 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968570 # Percentage of idle cycles +system.cpu1.Branches 5094014 # Number of branches fetched +system.cpu1.op_class::No_OpClass 12501 0.03% 0.03% # Class of executed instruction +system.cpu1.op_class::IntAlu 25826807 67.22% 67.25% # Class of executed instruction +system.cpu1.op_class::IntMult 50699 0.13% 67.38% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 745 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::MemRead 6744563 17.55% 84.94% # Class of executed instruction +system.cpu1.op_class::MemWrite 5786996 15.06% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 39250579 # Class of executed instruction +system.cpu1.op_class::total 38422311 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 44258 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469324 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.642267 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32721042 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 469836 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.643539 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 93149552500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.642267 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934848 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934848 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 40934 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 375227 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.528279 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32352870 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 375739 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 86.104636 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79843888000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.528279 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973688 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973688 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 456 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33660714 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33660714 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32721042 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32721042 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32721042 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32721042 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32721042 # number of overall hits -system.cpu1.icache.overall_hits::total 32721042 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469836 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469836 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469836 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469836 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469836 # number of overall misses -system.cpu1.icache.overall_misses::total 469836 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6435695955 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6435695955 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6435695955 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6435695955 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6435695955 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6435695955 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33190878 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33190878 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33190878 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33190878 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33190878 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33190878 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014156 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014156 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014156 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13697.749757 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13697.749757 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13697.749757 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13697.749757 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 65832957 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 65832957 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 32352870 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32352870 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32352870 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32352870 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32352870 # number of overall hits +system.cpu1.icache.overall_hits::total 32352870 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 375739 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 375739 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 375739 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 375739 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 375739 # number of overall misses +system.cpu1.icache.overall_misses::total 375739 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3159151510 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3159151510 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3159151510 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3159151510 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3159151510 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3159151510 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 32728609 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 32728609 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 32728609 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 32728609 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 32728609 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 32728609 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011480 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011480 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011480 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011480 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011480 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011480 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8407.834987 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8407.834987 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8407.834987 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8407.834987 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8407.834987 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8407.834987 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1600,214 +2037,554 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469836 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 469836 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 469836 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 469836 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 469836 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 469836 # 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number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11693.678315 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11693.678315 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11693.678315 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 375739 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 375739 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 375739 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 375739 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 375739 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 375739 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2595414990 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2595414990 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2595414990 # 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mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011480 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011480 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6907.494271 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6907.494271 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6907.494271 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 292234 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.923930 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11040887 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292603 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.733335 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 84705826250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.923930 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921726 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.921726 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 369 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.720703 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 45818347 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 45818347 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 6006097 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6006097 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4823101 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4823101 # 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number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 152082 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41875 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 41875 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11222 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11222 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10064 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10064 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 296135 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 296135 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 338010 # number of overall misses -system.cpu1.dcache.overall_misses::total 338010 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1718496498 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1718496498 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6437170330 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6437170330 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 96291249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 96291249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52005971 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 52005971 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8155666828 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8155666828 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8155666828 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8155666828 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6150150 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6150150 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975183 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4975183 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 64358 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 64358 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93158 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 93158 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92771 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92771 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11125333 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11125333 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11189691 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11189691 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023423 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023423 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030568 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030568 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.650657 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.650657 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120462 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120462 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108482 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108482 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026618 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026618 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030207 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.030207 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11929.612698 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 11929.612698 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42326.970516 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 42326.970516 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8580.578239 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8580.578239 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5167.524940 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5167.524940 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27540.367832 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 27540.367832 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24128.477939 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24128.477939 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 3539349 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 109722 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 3291325 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 217 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 15 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 138070 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 329563 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.tags.replacements 122650 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15477.303394 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 769651 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 138796 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.545196 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 2606454315500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5482.269126 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 12.040765 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.187836 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 603.787912 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2723.851785 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6655.165971 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.334611 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 481 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4215 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 2330 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1744 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5747 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1414 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.432556 # 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number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 12231230753 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 12238879503 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 28539732155 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28539732155 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7648750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 40770962908 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 40778611658 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.251119 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.102958 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.938411 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938411 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935255 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.935255 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.201397 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.201397 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234845 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.117995 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234845 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.309501 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 18698.875974 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 19181.395564 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51048.255365 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16263.259832 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16263.259832 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14141.580726 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14141.580726 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186999.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186999.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 26663.835843 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26663.835843 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20934.463207 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21132.265734 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20934.463207 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39643.018101 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.tags.replacements 313601 # number of replacements +system.cpu1.dcache.tags.tagsinuse 474.302028 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 10949850 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 314113 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 34.859589 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 76456711000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.302028 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.926371 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.926371 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 22948274 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 22948274 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 6183420 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6183420 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4558750 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4558750 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 19290 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 19290 # 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number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4809305384 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6370663 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6370663 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4693687 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4693687 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 62617 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 62617 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89491 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 89491 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89426 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 89426 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 11064350 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11064350 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11126967 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11126967 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029391 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.029391 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028749 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028749 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.691937 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.691937 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135086 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135086 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.152897 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.152897 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029119 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029119 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032849 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.032849 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12279.923714 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12279.923714 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18601.092569 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18601.092569 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18035.734966 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18035.734966 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23209.607987 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23209.607987 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14927.386504 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14927.386504 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13157.902267 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13157.902267 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 264973 # number of writebacks -system.cpu1.dcache.writebacks::total 264973 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 379 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 2067 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 2067 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 2446 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 2446 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 2446 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 2446 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143674 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 143674 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150015 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150015 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 26855 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 26855 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11222 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11222 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 293689 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 293689 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320544 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320544 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1427169251 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1427169251 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6022199670 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6022199670 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 445093004 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 445093004 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73834751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73834751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31881029 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31881029 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7449368921 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7449368921 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7894461925 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7894461925 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168604609000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168604609000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187299088 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187299088 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791908088 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791908088 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023361 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023361 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030153 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030153 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.417275 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.417275 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120462 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120462 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108461 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108461 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026398 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026398 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.028646 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9933.385658 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9933.385658 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40143.983402 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40143.983402 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16573.934239 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16573.934239 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6579.464534 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6579.464534 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3168.458458 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3168.458458 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25364.821022 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25364.821022 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24628.325363 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24628.325363 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 225255 # number of writebacks +system.cpu1.dcache.writebacks::total 225255 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 794 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 3242 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 3242 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 4036 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 4036 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 4036 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 4036 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 186449 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 186449 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 131695 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 131695 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 27821 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 27821 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12089 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12089 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 13671 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 13671 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 318144 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 345965 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 345965 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1916001744 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1916001744 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2027549872 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2027549872 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 596503999 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 596503999 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 193851000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 193851000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 289002030 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 289002030 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 494000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 494000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3943551616 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3943551616 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4540055615 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4540055615 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 12848996742 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 12848996742 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34213847345 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34213847345 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 47062844087 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 47062844087 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029267 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029267 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028058 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028058 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.444304 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.444304 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.135086 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.135086 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.152875 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.152875 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028754 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028754 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031092 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031092 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10276.277931 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10276.277931 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15395.799932 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15395.799932 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21440.782107 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21440.782107 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16035.321367 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16035.321367 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21139.787141 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21139.787141 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12395.492657 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12395.492657 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13122.875479 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13122.875479 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1815,6 +2592,57 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 957719 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 715905 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 756547 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 756547 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 225255 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 189199 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 53977 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23970 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 50977 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 119927 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 111476 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 751552 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 2675268 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6827 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16819 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3450466 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24038516 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 40612602 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 64686634 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 549743 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1492746 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.338347 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.473147 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 987680 66.17% 66.17% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 505066 33.83% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1492746 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1514414783 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 42402999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 563804260 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 984220768 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 4390000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 10377250 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1831,10 +2659,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745112259250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 745112259250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745112259250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 745112259250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1782387791115 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1782387791115 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 563f1978d..51c016582 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,134 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.614581 # Number of seconds simulated -sim_ticks 2614581252500 # Number of ticks simulated -final_tick 2614581252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.614572 # Number of seconds simulated +sim_ticks 2614571564500 # Number of ticks simulated +final_tick 2614571564500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 331710 # Simulator instruction rate (inst/s) -host_op_rate 396174 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14409825510 # Simulator tick rate (ticks/s) -host_mem_usage 433940 # Number of bytes of host memory used -host_seconds 181.44 # Real time elapsed on the host -sim_insts 60186875 # Number of instructions simulated -sim_ops 71883476 # Number of ops (including micro ops) simulated +host_inst_rate 536806 # Simulator instruction rate (inst/s) +host_op_rate 641128 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23319189669 # Simulator tick rate (ticks/s) +host_mem_usage 459056 # Number of bytes of host memory used +host_seconds 112.12 # Real time elapsed on the host +sim_insts 60187274 # Number of instructions simulated +sim_ops 71883961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9109080 # Number of bytes read from this memory -system.physmem.bytes_read::total 132497440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3720512 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9109336 # Number of bytes read from this memory +system.physmem.bytes_read::total 132497824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3720832 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6736584 # Number of bytes written to this memory +system.physmem.bytes_written::total 6736904 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142355 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15495006 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58133 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17222 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142359 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15495012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58138 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812151 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46922769 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 812156 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46922943 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3483954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50676352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1422986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2576544 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1422986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46922769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3484065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50676687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1423113 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2576676 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1423113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46922943 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4637512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53252896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15495006 # Number of read requests accepted -system.physmem.writeReqs 812151 # Number of write requests accepted -system.physmem.readBursts 15495006 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 812151 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991553920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 126464 # Total number of bytes read from write queue -system.physmem.bytesWritten 6744512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132497440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6736584 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1976 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706747 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.inst 269508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4637627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53253363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15495012 # Number of read requests accepted +system.physmem.writeReqs 812156 # Number of write requests accepted +system.physmem.readBursts 15495012 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812156 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991563904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 116864 # Total number of bytes read from write queue +system.physmem.bytesWritten 6748800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132497824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6736904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1826 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706685 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 968147 # Per bank write bursts +system.physmem.perBankRdBursts::0 968097 # Per bank write bursts system.physmem.perBankRdBursts::1 967810 # Per bank write bursts system.physmem.perBankRdBursts::2 967673 # Per bank write bursts system.physmem.perBankRdBursts::3 967915 # Per bank write bursts -system.physmem.perBankRdBursts::4 974375 # Per bank write bursts -system.physmem.perBankRdBursts::5 968054 # Per bank write bursts +system.physmem.perBankRdBursts::4 974446 # Per bank write bursts +system.physmem.perBankRdBursts::5 968066 # Per bank write bursts system.physmem.perBankRdBursts::6 967653 # Per bank write bursts -system.physmem.perBankRdBursts::7 967480 # Per bank write bursts -system.physmem.perBankRdBursts::8 968459 # Per bank write bursts +system.physmem.perBankRdBursts::7 967482 # Per bank write bursts +system.physmem.perBankRdBursts::8 968460 # Per bank write bursts system.physmem.perBankRdBursts::9 968209 # Per bank write bursts system.physmem.perBankRdBursts::10 967967 # Per bank write bursts system.physmem.perBankRdBursts::11 967960 # Per bank write bursts -system.physmem.perBankRdBursts::12 967929 # Per bank write bursts -system.physmem.perBankRdBursts::13 967878 # Per bank write bursts +system.physmem.perBankRdBursts::12 967930 # Per bank write bursts +system.physmem.perBankRdBursts::13 967880 # Per bank write bursts system.physmem.perBankRdBursts::14 967953 # Per bank write bursts -system.physmem.perBankRdBursts::15 967568 # Per bank write bursts -system.physmem.perBankWrBursts::0 6652 # Per bank write bursts -system.physmem.perBankWrBursts::1 6388 # Per bank write bursts -system.physmem.perBankWrBursts::2 6319 # Per bank write bursts -system.physmem.perBankWrBursts::3 6364 # Per bank write bursts -system.physmem.perBankWrBursts::4 6622 # Per bank write bursts -system.physmem.perBankWrBursts::5 6858 # Per bank write bursts -system.physmem.perBankWrBursts::6 6646 # Per bank write bursts -system.physmem.perBankWrBursts::7 6573 # Per bank write bursts -system.physmem.perBankWrBursts::8 7007 # Per bank write bursts +system.physmem.perBankRdBursts::15 967685 # Per bank write bursts +system.physmem.perBankWrBursts::0 6670 # Per bank write bursts +system.physmem.perBankWrBursts::1 6386 # Per bank write bursts +system.physmem.perBankWrBursts::2 6320 # Per bank write bursts +system.physmem.perBankWrBursts::3 6360 # Per bank write bursts +system.physmem.perBankWrBursts::4 6634 # Per bank write bursts +system.physmem.perBankWrBursts::5 6864 # Per bank write bursts +system.physmem.perBankWrBursts::6 6659 # Per bank write bursts +system.physmem.perBankWrBursts::7 6574 # Per bank write bursts +system.physmem.perBankWrBursts::8 7028 # Per bank write bursts system.physmem.perBankWrBursts::9 6769 # Per bank write bursts system.physmem.perBankWrBursts::10 6571 # Per bank write bursts -system.physmem.perBankWrBursts::11 6647 # Per bank write bursts +system.physmem.perBankWrBursts::11 6645 # Per bank write bursts system.physmem.perBankWrBursts::12 6565 # Per bank write bursts -system.physmem.perBankWrBursts::13 6381 # Per bank write bursts -system.physmem.perBankWrBursts::14 6555 # Per bank write bursts -system.physmem.perBankWrBursts::15 6466 # Per bank write bursts +system.physmem.perBankWrBursts::13 6383 # Per bank write bursts +system.physmem.perBankWrBursts::14 6560 # Per bank write bursts +system.physmem.perBankWrBursts::15 6462 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2614576987500 # Total gap between requests +system.physmem.totGap 2614567301000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6644 # Read request sizes (log2) system.physmem.readPktSize::3 15335434 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152928 # Read request sizes (log2) +system.physmem.readPktSize::6 152934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 58133 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1126497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 970808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1092616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 986699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1053397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2722203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2628336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3415970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 138177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 115073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 106569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 103082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58138 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1126447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 970731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1093523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 987097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1054685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2721121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2624601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3412795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 139881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 116829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 107818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 104436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -159,25 +171,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -208,45 +220,45 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1027240 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.825895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.842120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 203.903622 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22776 2.22% 2.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22448 2.19% 4.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8450 0.82% 5.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2555 0.25% 5.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2575 0.25% 5.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1819 0.18% 5.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8664 0.84% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 942 0.09% 6.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 957011 93.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1027240 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2531.539869 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116318.280129 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6115 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1027284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.798163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.747967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 203.998959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22800 2.22% 2.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22532 2.19% 4.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8422 0.82% 5.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2556 0.25% 5.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2545 0.25% 5.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1785 0.17% 5.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8607 0.84% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 981 0.10% 6.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 957056 93.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1027284 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6124 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2529.911822 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116281.505657 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6119 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6120 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.219444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.191199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.977796 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2386 38.99% 38.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 19 0.31% 39.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3702 60.49% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 12 0.20% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6120 # Writes before turning the bus around for reads -system.physmem.totQLat 400457727500 # Total ticks spent queuing -system.physmem.totMemAccLat 690952040000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77465150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25847.61 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6124 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6124 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.219138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.190607 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.983110 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2397 39.14% 39.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 24 0.39% 39.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3669 59.91% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 32 0.52% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6124 # Writes before turning the bus around for reads +system.physmem.totQLat 400730693500 # Total ticks spent queuing +system.physmem.totMemAccLat 691227931000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77465930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25864.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44597.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 379.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44614.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 379.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s @@ -254,74 +266,71 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.98 # Data bus utilization in percentage system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.67 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing -system.physmem.readRowHits 14482583 # Number of row buffer hits during reads -system.physmem.writeRowHits 88590 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing +system.physmem.avgWrQLen 28.13 # Average write queue length when enqueuing +system.physmem.readRowHits 14482679 # Number of row buffer hits during reads +system.physmem.writeRowHits 88673 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes -system.physmem.avgGap 160333.10 # Average gap between requests +system.physmem.writeRowHitRate 84.07 # Row buffer hit rate for writes +system.physmem.avgGap 160332.39 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2239817846000 # Time in different power states -system.physmem.memoryStateTime::REF 87306440000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2239359524750 # Time in different power states +system.physmem.memoryStateTime::REF 87306180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 287452006500 # Time in different power states +system.physmem.memoryStateTime::ACT 287902801500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54170150 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546653 # Transaction distribution -system.membus.trans_dist::ReadResp 16546653 # Transaction distribution +system.membus.trans_dist::ReadReq 16546657 # Transaction distribution +system.membus.trans_dist::ReadResp 16546657 # Transaction distribution system.membus.trans_dist::WriteReq 763381 # Transaction distribution system.membus.trans_dist::WriteResp 763381 # Transaction distribution -system.membus.trans_dist::Writeback 58133 # Transaction distribution +system.membus.trans_dist::Writeback 58138 # Transaction distribution system.membus.trans_dist::UpgradeReq 4511 # Transaction distribution system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 132457 # Transaction distribution -system.membus.trans_dist::ReadExResp 132457 # Transaction distribution +system.membus.trans_dist::ReadExReq 132459 # Transaction distribution +system.membus.trans_dist::ReadExResp 132459 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383082 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3840 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894355 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281306 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34952137 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16550632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18948866 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141632258 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141632258 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1207280500 # Layer occupancy (ticks) +system.membus.pkt_count::total 34952154 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16551336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18949570 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 141632962 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 215583 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 215583 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 215583 # Request fanout histogram +system.membus.reqLayer0.occupancy 1204828500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3534000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3334000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17916889500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17917176000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4952195664 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4952454428 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37921268500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37912905250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -329,7 +338,6 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47837076 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16518783 # Transaction distribution system.iobus.trans_dist::ReadResp 16518783 # Transaction distribution system.iobus.trans_dist::WriteReq 8182 # Transaction distribution @@ -361,34 +369,33 @@ system.iobus.pkt_count_system.bridge.master::total 2383082 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 33053930 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073922 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) @@ -435,11 +442,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374900000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38692913500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38695381750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -465,9 +472,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13160128 # DTB read hits +system.cpu.dtb.read_hits 13160242 # DTB read hits system.cpu.dtb.read_misses 7329 # DTB read misses -system.cpu.dtb.write_hits 11227968 # DTB write hits +system.cpu.dtb.write_hits 11228050 # DTB write hits system.cpu.dtb.write_misses 2212 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -478,12 +485,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13167457 # DTB read accesses -system.cpu.dtb.write_accesses 11230180 # DTB write accesses +system.cpu.dtb.read_accesses 13167571 # DTB read accesses +system.cpu.dtb.write_accesses 11230262 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 24388096 # DTB hits +system.cpu.dtb.hits 24388292 # DTB hits system.cpu.dtb.misses 9541 # DTB misses -system.cpu.dtb.accesses 24397637 # DTB accesses +system.cpu.dtb.accesses 24397833 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -505,7 +512,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61480692 # ITB inst hits +system.cpu.itb.inst_hits 61481095 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -522,37 +529,37 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61485163 # ITB inst accesses -system.cpu.itb.hits 61480692 # DTB hits +system.cpu.itb.inst_accesses 61485566 # ITB inst accesses +system.cpu.itb.hits 61481095 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61485163 # DTB accesses -system.cpu.numCycles 5229162505 # number of cpu cycles simulated +system.cpu.itb.accesses 61485566 # DTB accesses +system.cpu.numCycles 5229143129 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60186875 # Number of instructions committed -system.cpu.committedOps 71883476 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 64248071 # Number of integer alu accesses +system.cpu.committedInsts 60187274 # Number of instructions committed +system.cpu.committedOps 71883961 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 64248492 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139776 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7549008 # number of instructions that are conditional controls -system.cpu.num_int_insts 64248071 # number of integer instructions +system.cpu.num_func_calls 2139801 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7549047 # number of instructions that are conditional controls +system.cpu.num_int_insts 64248492 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 116109819 # number of times the integer registers were read -system.cpu.num_int_register_writes 42862791 # number of times the integer registers were written +system.cpu.num_int_register_reads 116110622 # number of times the integer registers were read +system.cpu.num_int_register_writes 42863098 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_cc_register_reads 257767219 # number of times the CC registers were read -system.cpu.num_cc_register_writes 28995131 # number of times the CC registers were written -system.cpu.num_mem_refs 25244051 # number of memory refs -system.cpu.num_load_insts 13512687 # Number of load instructions -system.cpu.num_store_insts 11731364 # Number of store instructions -system.cpu.num_idle_cycles 4584182254.578246 # Number of idle cycles -system.cpu.num_busy_cycles 644980250.421753 # Number of busy cycles -system.cpu.not_idle_fraction 0.123343 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.876657 # Percentage of idle cycles -system.cpu.Branches 10306559 # Number of branches fetched +system.cpu.num_cc_register_reads 257769006 # number of times the CC registers were read +system.cpu.num_cc_register_writes 28995258 # number of times the CC registers were written +system.cpu.num_mem_refs 25244235 # number of memory refs +system.cpu.num_load_insts 13512788 # Number of load instructions +system.cpu.num_store_insts 11731447 # Number of store instructions +system.cpu.num_idle_cycles 4584209782.584247 # Number of idle cycles +system.cpu.num_busy_cycles 644933346.415753 # Number of busy cycles +system.cpu.not_idle_fraction 0.123334 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.876666 # Percentage of idle cycles +system.cpu.Branches 10306630 # Number of branches fetched system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 47576706 65.23% 65.27% # Class of executed instruction +system.cpu.op_class::IntAlu 47577014 65.23% 65.27% # Class of executed instruction system.cpu.op_class::IntMult 87551 0.12% 65.39% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction @@ -581,20 +588,20 @@ system.cpu.op_class::SimdFloatMisc 2109 0.00% 65.39% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::MemRead 13512687 18.53% 83.92% # Class of executed instruction -system.cpu.op_class::MemWrite 11731364 16.08% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13512788 18.53% 83.92% # Class of executed instruction +system.cpu.op_class::MemWrite 11731447 16.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 72938935 # Class of executed instruction +system.cpu.op_class::total 72939427 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83001 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 855859 # number of replacements -system.cpu.icache.tags.tagsinuse 510.877209 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60624321 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856371 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.792123 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19627747250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.877209 # Average occupied blocks per requestor +system.cpu.kern.inst.quiesce 83004 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 855897 # number of replacements +system.cpu.icache.tags.tagsinuse 510.877214 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60624686 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856409 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.789408 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19623933250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.877214 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -603,44 +610,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 194 system.cpu.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62337063 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62337063 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60624321 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60624321 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60624321 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60624321 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60624321 # number of overall hits -system.cpu.icache.overall_hits::total 60624321 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856371 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856371 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856371 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856371 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856371 # number of overall misses -system.cpu.icache.overall_misses::total 856371 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11763954000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11763954000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11763954000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11763954000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11763954000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11763954000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61480692 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61480692 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61480692 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61480692 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61480692 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61480692 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013929 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013929 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013929 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13736.983153 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13736.983153 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13736.983153 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13736.983153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13736.983153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13736.983153 # average overall miss latency +system.cpu.icache.tags.tag_accesses 62337504 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62337504 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60624686 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60624686 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60624686 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60624686 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60624686 # number of overall hits +system.cpu.icache.overall_hits::total 60624686 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856409 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856409 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856409 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856409 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856409 # number of overall misses +system.cpu.icache.overall_misses::total 856409 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766778500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11766778500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11766778500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11766778500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11766778500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11766778500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61481095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61481095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61481095 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61481095 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61481095 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61481095 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013930 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013930 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013930 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13739.671699 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13739.671699 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13739.671699 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13739.671699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13739.671699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13739.671699 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,186 +656,186 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856371 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856371 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856371 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856371 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856371 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856371 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10047194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10047194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10047194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10047194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10047194000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10047194000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856409 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856409 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856409 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856409 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856409 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856409 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10049953500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10049953500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10049953500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10049953500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10049953500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10049953500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 440846250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 440846250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 440846250 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 440846250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013929 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013929 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013929 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013929 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013929 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013929 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11732.291262 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11732.291262 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11732.291262 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11732.291262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11732.291262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11732.291262 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013930 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013930 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013930 # 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average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62821 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50750.711022 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1678966 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 128205 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.095948 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2564782857000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37685.579713 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 62827 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69993.462530 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -837,92 +844,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58133 # number of writebacks -system.cpu.l2cache.writebacks::total 58133 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 58138 # number of writebacks +system.cpu.l2cache.writebacks::total 58138 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664674250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167014182000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16705839575 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16705839575 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166662160750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167011668500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16705919061 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16705919061 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 349507750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370513825 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720021575 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183368079811 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183717587561 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012394 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026055 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016453 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991102 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012394 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229809 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103597 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012396 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229798 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103596 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58038.465169 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62306.914894 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60094.597235 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.381215 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.381215 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56954.786346 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56954.786346 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58237.400906 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61751.696718 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59929.865690 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.036269 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.036269 # 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average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58038.465169 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57321.777973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57370.690455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58237.400906 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57429.738834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57484.890754 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -932,94 +939,94 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 625842 # number of replacements +system.cpu.dcache.tags.replacements 625894 # number of replacements system.cpu.dcache.tags.tagsinuse 511.875658 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21786000 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626354 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.782248 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21786154 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626406 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.779606 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.875658 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 90403758 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 90403758 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11249339 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11249339 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9965366 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9965366 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 84253 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 84253 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236457 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236457 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247663 # 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average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13711.884421 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45175.314481 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45175.314481 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13846.881413 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13846.881413 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28317.527202 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28317.527202 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.809401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23956.809401 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.543003 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.543003 # 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average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13827.913098 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28347.450827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28347.450827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23982.306362 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23982.306362 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1028,70 +1035,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 58 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 594981 # number of writebacks -system.cpu.dcache.writebacks::total 594981 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 534 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 534 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4836 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 4836 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5370 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5370 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5370 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5370 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 294129 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 294129 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250461 # 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number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058544250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058544250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242551425 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242551425 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301095675 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301095675 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025479 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025479 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398565 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398565 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045251 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045251 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025022 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025022 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11714.476471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11714.476471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42972.780149 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42972.780149 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16715.952857 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16715.952857 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11841.706077 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11841.706077 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26090.403311 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26090.403311 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24975.923787 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15453754489 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15453754489 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182056011250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182056011250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242438939 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242438939 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208298450189 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208298450189 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398573 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398573 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045254 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045254 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025024 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025024 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028161 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028161 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11708.909255 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11708.909255 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43057.923596 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43057.923596 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16665.359072 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16665.359072 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11822.872056 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.872056 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26125.917103 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26125.917103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25001.261066 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25001.261066 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1099,33 +1106,46 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52981595 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2453579 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2453579 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2453657 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2453657 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763381 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763381 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 594981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247539 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724389 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748549 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12041 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::Writeback 595027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247551 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724466 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748697 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12042 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 26252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7511231 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54730908 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83579878 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138353418 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138353418 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 171268 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3007873000 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count::total 7511457 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54733404 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83586150 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 138362190 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 18590 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2108398 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2108398 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2108398 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3007986500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1294746250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1294797750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2533153086 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2533255572 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1147,10 +1167,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1760059764500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1760059764500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1760318460750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1760318460750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index a9cd1b1ac..5818937f9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.321351 # Number of seconds simulated -sim_ticks 2321351025500 # Number of ticks simulated -final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.321335 # Number of seconds simulated +sim_ticks 2321335404000 # Number of ticks simulated +final_tick 2321335404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 709541 # Simulator instruction rate (inst/s) -host_op_rate 854435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27266672116 # Simulator tick rate (ticks/s) -host_mem_usage 431868 # Number of bytes of host memory used -host_seconds 85.14 # Real time elapsed on the host +host_inst_rate 1185543 # Simulator instruction rate (inst/s) +host_op_rate 1427641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45558461303 # Simulator tick rate (ticks/s) +host_mem_usage 457752 # Number of bytes of host memory used +host_seconds 50.95 # Real time elapsed on the host sim_insts 60406834 # Number of instructions simulated sim_ops 72742429 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -16,54 +16,54 @@ system.clk_domain.clock 1000 # Cl system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 508168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5844952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 197248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3227072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 508104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5777624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 197312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3294400 # Number of bytes read from this memory system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 508168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 197248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 508104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 197312 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3703808 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1462736 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1553080 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1461532 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1554284 # Number of bytes written to this memory system.physmem.bytes_written::total 6719624 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14152 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 91353 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 50423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14151 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 90301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 51475 # Number of read requests responded to by this memory system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57872 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 365684 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 388270 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 365383 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 388571 # Number of write requests responded to by this memory system.physmem.num_writes::total 811826 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47429803 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 83 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 218910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2517910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 84971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1390170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 218910 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 84971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1595540 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 630123 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 669041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2894704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1595540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 218884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2488923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 84999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1419183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51641930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 218884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 84999 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1595551 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 629608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 669565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2894723 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1595551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47429803 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 83 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 218910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3148032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 84971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2059211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54536286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 218884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3118531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 84999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2088748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54536653 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -76,30 +76,66 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55568819 # Throughput (bytes/s) -system.membus.data_through_bus 128994735 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 14973628 # Transaction distribution +system.membus.trans_dist::ReadResp 14973628 # Transaction distribution +system.membus.trans_dist::WriteReq 763122 # Transaction distribution +system.membus.trans_dist::WriteResp 763122 # Transaction distribution +system.membus.trans_dist::Writeback 57872 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4519 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4519 # Transaction distribution +system.membus.trans_dist::ReadExReq 131877 # Transaction distribution +system.membus.trans_dist::ReadExResp 131877 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 27525120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 27525120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31804164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390127 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 6720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16497384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18894255 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 110100480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 110100480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 128994735 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214752 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 214752 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 214752 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 62250 # number of replacements -system.l2c.tags.tagsinuse 50005.872632 # Cycle average of tags in use -system.l2c.tags.total_refs 1678480 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 50005.858036 # Cycle average of tags in use +system.l2c.tags.total_refs 1678527 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 127635 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.150625 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36900.828862 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993863 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993971 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4874.093087 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3539.587837 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2140.383073 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2548.991939 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563062 # Average percentage of cache occupancy +system.l2c.tags.avg_refs 13.150993 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2306275686000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36902.743708 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993864 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993972 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4873.119904 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3553.057866 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2141.364810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2533.583912 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563091 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.054010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032660 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.038895 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074358 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.054215 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032675 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.038659 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.763029 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id @@ -107,136 +143,136 @@ system.l2c.tags.age_task_id_blocks_1023::4 2 # system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 3672 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9281 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9282 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52127 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17104797 # Number of tag accesses -system.l2c.tags.data_accesses 17104797 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8775 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3263 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 451755 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 188951 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5151 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2105 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 387038 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 177833 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1224871 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 592686 # number of Writeback hits -system.l2c.Writeback_hits::total 592686 # number of Writeback hits +system.l2c.tags.tag_accesses 17105211 # Number of tag accesses +system.l2c.tags.data_accesses 17105211 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8799 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3276 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 451004 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 189163 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5176 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2130 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 387778 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 177603 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1224929 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 592674 # number of Writeback hits +system.l2c.Writeback_hits::total 592674 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 10 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 62028 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 51680 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113708 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8775 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3263 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 451755 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 250979 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5151 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2105 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 387038 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 229513 # number of demand (read+write) hits -system.l2c.demand_hits::total 1338579 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8775 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3263 # number of overall hits -system.l2c.overall_hits::cpu0.inst 451755 # number of overall hits -system.l2c.overall_hits::cpu0.data 250979 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5151 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2105 # number of overall hits -system.l2c.overall_hits::cpu1.inst 387038 # number of overall hits -system.l2c.overall_hits::cpu1.data 229513 # number of overall hits -system.l2c.overall_hits::total 1338579 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 62080 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 51632 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113712 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8799 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3276 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 451004 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 251243 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5176 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2130 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 387778 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 229235 # number of demand (read+write) hits +system.l2c.demand_hits::total 1338641 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8799 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3276 # number of overall hits +system.l2c.overall_hits::cpu0.inst 451004 # number of overall hits +system.l2c.overall_hits::cpu0.data 251243 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5176 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2130 # number of overall hits +system.l2c.overall_hits::cpu1.inst 387778 # number of overall hits +system.l2c.overall_hits::cpu1.data 229235 # number of overall hits +system.l2c.overall_hits::total 1338641 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7526 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6094 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3082 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3778 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20485 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7525 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6105 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3083 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3766 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20484 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1505 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1412 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2917 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 86064 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 47413 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133477 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 85002 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 48477 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133479 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7526 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 92158 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3082 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 51191 # number of demand (read+write) misses -system.l2c.demand_misses::total 153962 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7525 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 91107 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3083 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 52243 # number of demand (read+write) misses +system.l2c.demand_misses::total 153963 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7526 # number of overall misses -system.l2c.overall_misses::cpu0.data 92158 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3082 # number of overall misses -system.l2c.overall_misses::cpu1.data 51191 # number of overall misses -system.l2c.overall_misses::total 153962 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8777 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3266 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 459281 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 195045 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5151 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2105 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 390120 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 181611 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1245356 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 592686 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 592686 # number of Writeback accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 7525 # number of overall misses +system.l2c.overall_misses::cpu0.data 91107 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3083 # number of overall misses +system.l2c.overall_misses::cpu1.data 52243 # number of overall misses +system.l2c.overall_misses::total 153963 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8801 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3279 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 458529 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 195268 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5176 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2130 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 390861 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 181369 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1245413 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 592674 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 592674 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1521 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1422 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 148092 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 99093 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247185 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8777 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3266 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 459281 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 343137 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5151 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2105 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 390120 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 280704 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1492541 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8777 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3266 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 459281 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 343137 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5151 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2105 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 390120 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 280704 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1492541 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000919 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016386 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.031244 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007900 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020803 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016449 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 147082 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 100109 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247191 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8801 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3279 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 458529 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 342350 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5176 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2130 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 390861 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 281478 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1492604 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8801 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3279 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 458529 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 342350 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5176 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2130 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 390861 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 281478 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1492604 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000227 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000915 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016411 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.031265 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007888 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020764 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016448 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989481 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992968 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.581152 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.478470 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539988 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000919 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016386 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.268575 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007900 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.182366 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.103154 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000919 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016386 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.268575 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007900 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.182366 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.103154 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.577923 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.484242 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539983 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000227 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000915 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016411 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.266122 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007888 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.185602 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103151 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000227 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000915 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016411 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.266122 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007888 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.185602 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103151 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -254,11 +290,99 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 59409488 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 137910275 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 48459111 # Throughput (bytes/s) -system.iobus.data_through_bus 112490607 # Total data (bytes) +system.toL2Bus.trans_dist::ReadReq 2455233 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2455233 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763122 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763122 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 592674 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2943 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2943 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247191 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247191 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1715294 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5740366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 22916 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51076 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7529652 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54491548 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83268947 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 45832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 137908479 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 0 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2107457 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2107457 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2107457 # Request fanout histogram +system.iobus.trans_dist::ReadReq 14945841 # Transaction distribution +system.iobus.trans_dist::ReadResp 14945841 # Transaction distribution +system.iobus.trans_dist::WriteReq 8131 # Transaction distribution +system.iobus.trans_dist::WriteResp 8131 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7900 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 984 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382824 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 27525120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 27525120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 29907944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39247 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15800 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390127 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 110100480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 110100480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 112490607 # Cumulative packet size per connected master and slave (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -282,25 +406,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6811742 # DTB read hits -system.cpu0.dtb.read_misses 6183 # DTB read misses -system.cpu0.dtb.write_hits 6269363 # DTB write hits -system.cpu0.dtb.write_misses 2047 # DTB write misses +system.cpu0.dtb.read_hits 6816435 # DTB read hits +system.cpu0.dtb.read_misses 6211 # DTB read misses +system.cpu0.dtb.write_hits 6254825 # DTB write hits +system.cpu0.dtb.write_misses 2049 # DTB write misses system.cpu0.dtb.flush_tlb 2324 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 763 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 758 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5527 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5541 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 120 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 235 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6817925 # DTB read accesses -system.cpu0.dtb.write_accesses 6271410 # DTB write accesses +system.cpu0.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6822646 # DTB read accesses +system.cpu0.dtb.write_accesses 6256874 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13081105 # DTB hits -system.cpu0.dtb.misses 8230 # DTB misses -system.cpu0.dtb.accesses 13089335 # DTB accesses +system.cpu0.dtb.hits 13071260 # DTB hits +system.cpu0.dtb.misses 8260 # DTB misses +system.cpu0.dtb.accesses 13079520 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -322,143 +446,143 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32133466 # ITB inst hits -system.cpu0.itb.inst_misses 3581 # ITB inst misses +system.cpu0.itb.inst_hits 32152502 # ITB inst hits +system.cpu0.itb.inst_misses 3598 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2324 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 763 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 758 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2662 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2674 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32137047 # ITB inst accesses -system.cpu0.itb.hits 32133466 # DTB hits -system.cpu0.itb.misses 3581 # DTB misses -system.cpu0.itb.accesses 32137047 # DTB accesses -system.cpu0.numCycles 4608021079 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32156100 # ITB inst accesses +system.cpu0.itb.hits 32152502 # DTB hits +system.cpu0.itb.misses 3598 # DTB misses +system.cpu0.itb.accesses 32156100 # DTB accesses +system.cpu0.numCycles 4610022066 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31639227 # Number of instructions committed -system.cpu0.committedOps 38587883 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34004805 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5482 # Number of float alu accesses -system.cpu0.num_func_calls 1192523 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4010781 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34004805 # number of integer instructions -system.cpu0.num_fp_insts 5482 # number of float instructions -system.cpu0.num_int_register_reads 62290177 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22551825 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3925 # number of times the floating registers were read +system.cpu0.committedInsts 31655881 # Number of instructions committed +system.cpu0.committedOps 38589756 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34002307 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5498 # Number of float alu accesses +system.cpu0.num_func_calls 1192858 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4013764 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34002307 # number of integer instructions +system.cpu0.num_fp_insts 5498 # number of float instructions +system.cpu0.num_int_register_reads 62271464 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22558612 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3941 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1558 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 115496065 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 15262729 # number of times the CC registers were written -system.cpu0.num_mem_refs 13528824 # number of memory refs -system.cpu0.num_load_insts 6988108 # Number of load instructions -system.cpu0.num_store_insts 6540716 # Number of store instructions -system.cpu0.num_idle_cycles 4534732444.570566 # Number of idle cycles -system.cpu0.num_busy_cycles 73288634.429434 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015905 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984095 # Percentage of idle cycles -system.cpu0.Branches 5541899 # Number of branches fetched -system.cpu0.op_class::No_OpClass 16090 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 25070156 64.84% 64.89% # Class of executed instruction -system.cpu0.op_class::IntMult 45827 0.12% 65.00% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1368 0.00% 65.01% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 65.01% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.01% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.01% # Class of executed instruction -system.cpu0.op_class::MemRead 6988108 18.07% 83.08% # Class of executed instruction -system.cpu0.op_class::MemWrite 6540716 16.92% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 115497170 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 15275707 # number of times the CC registers were written +system.cpu0.num_mem_refs 13519126 # number of memory refs +system.cpu0.num_load_insts 6992673 # Number of load instructions +system.cpu0.num_store_insts 6526453 # Number of store instructions +system.cpu0.num_idle_cycles 4538759726.926458 # Number of idle cycles +system.cpu0.num_busy_cycles 71262339.073542 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015458 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984542 # Percentage of idle cycles +system.cpu0.Branches 5545179 # Number of branches fetched +system.cpu0.op_class::No_OpClass 16079 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 25081623 64.87% 64.91% # Class of executed instruction +system.cpu0.op_class::IntMult 45922 0.12% 65.03% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1365 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::MemRead 6992673 18.09% 83.12% # Class of executed instruction +system.cpu0.op_class::MemWrite 6526453 16.88% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 38662265 # Class of executed instruction +system.cpu0.op_class::total 38664115 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82781 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 850515 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60581740 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 446.344221 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.345372 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.871766 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127628 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 850504 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.689630 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60581751 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 851016 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 71.187558 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5451547500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 446.338382 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.351248 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.871755 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127639 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62283794 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62283794 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31676072 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 28905668 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60581740 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31676072 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 28905668 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60581740 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31676072 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 28905668 # number of overall hits -system.cpu0.icache.overall_hits::total 60581740 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 460107 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 390920 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 851027 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 460107 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 390920 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 851027 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 460107 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 390920 # number of overall misses -system.cpu0.icache.overall_misses::total 851027 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32136179 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 29296588 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.tags.tag_accesses 62283783 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62283783 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 31695864 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 28885887 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60581751 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31695864 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 28885887 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60581751 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31695864 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 28885887 # number of overall hits +system.cpu0.icache.overall_hits::total 60581751 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 459362 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 391654 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 851016 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 459362 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 391654 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 851016 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 459362 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 391654 # number of overall misses +system.cpu0.icache.overall_misses::total 851016 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32155226 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 29277541 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32136179 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 29296588 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 32155226 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 29277541 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 61432767 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32136179 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 29296588 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32155226 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 29277541 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 61432767 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014317 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013344 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014286 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013377 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014317 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013344 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014286 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013377 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014317 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013344 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014286 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013377 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -469,101 +593,101 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 623329 # number of replacements +system.cpu0.dcache.tags.replacements 623316 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21798515 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.942421 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 21798519 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623828 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.943156 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.974436 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 58.022582 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.886669 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.113325 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.972290 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 58.024728 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.886665 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.113330 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 90313265 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 90313265 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5835707 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 5404504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11240211 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5610278 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4351033 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9961311 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 52098 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58749 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 110847 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136238 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 99769 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236007 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142767 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 104429 # number of StoreCondReq hits +system.cpu0.dcache.tags.tag_accesses 90313216 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90313216 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5840103 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 5400119 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11240222 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5597078 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4364227 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9961305 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 52143 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58700 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 110843 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136250 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 99760 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236010 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142749 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 104447 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11445985 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 9755537 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21201522 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11498083 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 9814286 # number of overall hits -system.cpu0.dcache.overall_hits::total 21312369 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 155593 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 136452 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 292045 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 149613 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 100515 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250128 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 32922 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 40499 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 73421 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6530 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4660 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11190 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 305206 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 236967 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 542173 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 338128 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 277466 # number of overall misses -system.cpu0.dcache.overall_misses::total 615594 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5991300 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 5540956 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5759891 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4451548 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_hits::cpu0.data 11437181 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 9764346 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21201527 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11489324 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 9823046 # number of overall hits +system.cpu0.dcache.overall_hits::total 21312370 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 155804 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 136229 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 292033 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 148603 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 101531 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250134 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 32964 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 40453 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 73417 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6500 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4687 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11187 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 304407 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 237760 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 542167 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 337371 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 278213 # number of overall misses +system.cpu0.dcache.overall_misses::total 615584 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5995907 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 5536348 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 11532255 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5745681 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4465758 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 85020 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 99248 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 184268 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 142768 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 104429 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 85107 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 99153 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 184260 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 142750 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 104447 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 142767 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 104429 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 142749 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 104447 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11751191 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 9992504 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11836211 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10091752 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21927963 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025970 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.024626 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.025324 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025975 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.022580 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 11741588 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 10002106 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21743694 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11826695 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10101259 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21927954 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025985 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.024606 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025863 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.022735 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.387227 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.408059 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.398447 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045739 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044624 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045268 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025972 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023714 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.024935 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028567 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027494 # miss rate for overall accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.387324 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.407986 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.398442 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045534 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044874 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025926 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023771 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028526 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027542 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -573,8 +697,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 592686 # number of writebacks -system.cpu0.dcache.writebacks::total 592686 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 592674 # number of writebacks +system.cpu0.dcache.writebacks::total 592674 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -599,25 +723,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6327054 # DTB read hits -system.cpu1.dtb.read_misses 4532 # DTB read misses -system.cpu1.dtb.write_hits 4945852 # DTB write hits -system.cpu1.dtb.write_misses 1126 # DTB write misses +system.cpu1.dtb.read_hits 6322311 # DTB read hits +system.cpu1.dtb.read_misses 4545 # DTB read misses +system.cpu1.dtb.write_hits 4960387 # DTB write hits +system.cpu1.dtb.write_misses 1127 # DTB write misses system.cpu1.dtb.flush_tlb 2320 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3028 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3056 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 87 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6331586 # DTB read accesses -system.cpu1.dtb.write_accesses 4946978 # DTB write accesses +system.cpu1.dtb.perms_faults 220 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6326856 # DTB read accesses +system.cpu1.dtb.write_accesses 4961514 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 11272906 # DTB hits -system.cpu1.dtb.misses 5658 # DTB misses -system.cpu1.dtb.accesses 11278564 # DTB accesses +system.cpu1.dtb.hits 11282698 # DTB hits +system.cpu1.dtb.misses 5672 # DTB misses +system.cpu1.dtb.accesses 11288370 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -639,87 +763,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 29294834 # ITB inst hits -system.cpu1.itb.inst_misses 2597 # ITB inst misses +system.cpu1.itb.inst_hits 29275767 # ITB inst hits +system.cpu1.itb.inst_misses 2611 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2320 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1660 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1680 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 29297431 # ITB inst accesses -system.cpu1.itb.hits 29294834 # DTB hits -system.cpu1.itb.misses 2597 # DTB misses -system.cpu1.itb.accesses 29297431 # DTB accesses -system.cpu1.numCycles 141054432 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 29278378 # ITB inst accesses +system.cpu1.itb.hits 29275767 # DTB hits +system.cpu1.itb.misses 2611 # DTB misses +system.cpu1.itb.accesses 29278378 # DTB accesses +system.cpu1.numCycles 143033518 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 28767607 # Number of instructions committed -system.cpu1.committedOps 34154546 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 30186625 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4787 # Number of float alu accesses -system.cpu1.num_func_calls 943239 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3534203 # number of instructions that are conditional controls -system.cpu1.num_int_insts 30186625 # number of integer instructions -system.cpu1.num_fp_insts 4787 # number of float instructions -system.cpu1.num_int_register_reads 54137170 # number of times the integer registers were read -system.cpu1.num_int_register_writes 20266282 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3568 # number of times the floating registers were read +system.cpu1.committedInsts 28750953 # Number of instructions committed +system.cpu1.committedOps 34152673 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 30189123 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4771 # Number of float alu accesses +system.cpu1.num_func_calls 942904 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3531220 # number of instructions that are conditional controls +system.cpu1.num_int_insts 30189123 # number of integer instructions +system.cpu1.num_fp_insts 4771 # number of float instructions +system.cpu1.num_int_register_reads 54155883 # number of times the integer registers were read +system.cpu1.num_int_register_writes 20259495 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3552 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1222 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 102073939 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 13715012 # number of times the CC registers were written -system.cpu1.num_mem_refs 11692450 # number of memory refs -system.cpu1.num_load_insts 6511829 # Number of load instructions -system.cpu1.num_store_insts 5180621 # Number of store instructions -system.cpu1.num_idle_cycles 138966556.858503 # Number of idle cycles -system.cpu1.num_busy_cycles 2087875.141497 # Number of busy cycles -system.cpu1.not_idle_fraction 0.014802 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.985198 # Percentage of idle cycles -system.cpu1.Branches 4756618 # Number of branches fetched -system.cpu1.op_class::No_OpClass 12428 0.04% 0.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 22465876 65.66% 65.70% # Class of executed instruction -system.cpu1.op_class::IntMult 41944 0.12% 65.82% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 745 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::MemRead 6511829 19.03% 84.86% # Class of executed instruction -system.cpu1.op_class::MemWrite 5180621 15.14% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 102072834 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 13702034 # number of times the CC registers were written +system.cpu1.num_mem_refs 11702148 # number of memory refs +system.cpu1.num_load_insts 6507264 # Number of load instructions +system.cpu1.num_store_insts 5194884 # Number of store instructions +system.cpu1.num_idle_cycles 140979209.208319 # Number of idle cycles +system.cpu1.num_busy_cycles 2054308.791681 # Number of busy cycles +system.cpu1.not_idle_fraction 0.014362 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.985638 # Percentage of idle cycles +system.cpu1.Branches 4753338 # Number of branches fetched +system.cpu1.op_class::No_OpClass 12439 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 22454409 65.63% 65.67% # Class of executed instruction +system.cpu1.op_class::IntMult 41849 0.12% 65.79% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 748 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::MemRead 6507264 19.02% 84.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 5194884 15.18% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 34213443 # Class of executed instruction +system.cpu1.op_class::total 34211593 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements |