diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 216 |
1 files changed, 108 insertions, 108 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 58cc29985..5a613cfa1 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -46,114 +46,114 @@ system.physmem.bw_total::cpu.itb.walker 63 # To system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 106561 # number of replacements -system.l2c.tagsinuse 64822.143261 # Cycle average of tags in use -system.l2c.total_refs 3456533 # Total number of references to valid blocks. -system.l2c.sampled_refs 170680 # Sample count of references to valid blocks. -system.l2c.avg_refs 20.251541 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989107 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1538130 # number of Writeback hits -system.l2c.Writeback_hits::total 1538130 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179208 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 777957 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1454603 # number of demand (read+write) hits -system.l2c.demand_hits::total 2241838 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6578 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 2700 # number of overall hits -system.l2c.overall_hits::cpu.inst 777957 # number of overall hits -system.l2c.overall_hits::cpu.data 1454603 # number of overall hits -system.l2c.overall_hits::total 2241838 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 32184 # number of ReadReq misses -system.l2c.ReadReq_misses::total 45533 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1796 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 134377 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 13342 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 166561 # number of demand (read+write) misses -system.l2c.demand_misses::total 179910 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu.inst 13342 # number of overall misses -system.l2c.overall_misses::cpu.data 166561 # number of overall misses -system.l2c.overall_misses::total 179910 # number of overall misses -system.l2c.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2421748 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2421748 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.074289 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.074289 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 98533 # number of writebacks -system.l2c.writebacks::total 98533 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 106561 # number of replacements +system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits +system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses +system.cpu.l2cache.overall_misses::total 179910 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks +system.cpu.l2cache.writebacks::total 98533 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47570 # number of replacements system.iocache.tagsinuse 0.042409 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. |