diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 496 |
1 files changed, 248 insertions, 248 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 82168f91d..1886c90bb 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,145 +4,145 @@ sim_seconds 5.112043 # Nu sim_ticks 5112043255000 # Number of ticks simulated final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1304311 # Simulator instruction rate (inst/s) -host_op_rate 2670670 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33369516688 # Simulator tick rate (ticks/s) -host_mem_usage 357276 # Number of bytes of host memory used -host_seconds 153.20 # Real time elapsed on the host -sim_insts 199813913 # Number of instructions simulated -sim_ops 409133277 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2786624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 972736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11807616 # Number of bytes read from this memory -system.physmem.bytes_read::total 15568704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 972736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 972736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 12232896 # Number of bytes written to this memory -system.physmem.bytes_written::total 12232896 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 43541 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 15199 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 184494 # Number of read requests responded to by this memory -system.physmem.num_reads::total 243261 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 191139 # Number of write requests responded to by this memory -system.physmem.num_writes::total 191139 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 545110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 190283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2309764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3045495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 190283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 190283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2392956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2392956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2392956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 545110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 190283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2309764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5438452 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 164044 # number of replacements -system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use -system.l2c.total_refs 3332458 # Total number of references to valid blocks. -system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. -system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. +host_inst_rate 1996585 # Simulator instruction rate (inst/s) +host_op_rate 4088150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51080652430 # Simulator tick rate (ticks/s) +host_mem_usage 357308 # Number of bytes of host memory used +host_seconds 100.08 # Real time elapsed on the host +sim_insts 199813912 # Number of instructions simulated +sim_ops 409133288 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory +system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory +system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 106561 # number of replacements +system.l2c.tagsinuse 64822.143270 # Cycle average of tags in use +system.l2c.total_refs 3457342 # Total number of references to valid blocks. +system.l2c.sampled_refs 170680 # Sample count of references to valid blocks. +system.l2c.avg_refs 20.256281 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits -system.l2c.Writeback_hits::total 1529403 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits -system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits -system.l2c.overall_hits::cpu.inst 776101 # number of overall hits -system.l2c.overall_hits::cpu.data 1435764 # number of overall hits -system.l2c.overall_hits::total 2221403 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses -system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses -system.l2c.demand_misses::total 200638 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu.inst 15200 # number of overall misses -system.l2c.overall_misses::cpu.data 185411 # number of overall misses -system.l2c.overall_misses::total 200638 # number of overall misses -system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026559 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.982995 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.461240 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.082838 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.082838 # miss rate for overall accesses +system.l2c.occ_blocks::writebacks 51981.461992 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 2434.983597 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 10405.560616 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989107 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1538939 # number of Writeback hits +system.l2c.Writeback_hits::total 1538939 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179208 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 777957 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1454603 # number of demand (read+write) hits +system.l2c.demand_hits::total 2241838 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 6578 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 2700 # number of overall hits +system.l2c.overall_hits::cpu.inst 777957 # number of overall hits +system.l2c.overall_hits::cpu.data 1454603 # number of overall hits +system.l2c.overall_hits::total 2241838 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 32184 # number of ReadReq misses +system.l2c.ReadReq_misses::total 45533 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1796 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 134377 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 13342 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 166561 # number of demand (read+write) misses +system.l2c.demand_misses::total 179910 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu.inst 13342 # number of overall misses +system.l2c.overall_misses::cpu.data 166561 # number of overall misses +system.l2c.overall_misses::total 179910 # number of overall misses +system.l2c.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1538939 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1538939 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2421748 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2421748 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.074289 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.074289 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,8 +151,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 144472 # number of writebacks -system.l2c.writebacks::total 144472 # number of writebacks +system.l2c.writebacks::writebacks 98533 # number of writebacks +system.l2c.writebacks::total 98533 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47570 # number of replacements system.iocache.tagsinuse 0.042409 # Cycle average of tags in use @@ -213,32 +213,32 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10224086531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199813913 # Number of instructions committed -system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses +system.cpu.committedInsts 199813912 # Number of instructions committed +system.cpu.committedOps 409133288 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374297254 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls -system.cpu.num_int_insts 374297244 # number of integer instructions +system.cpu.num_conditional_control_insts 39954972 # number of instructions that are conditional controls +system.cpu.num_int_insts 374297254 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 1159028861 # number of times the integer registers were read -system.cpu.num_int_register_writes 636431619 # number of times the integer registers were written +system.cpu.num_int_register_reads 1159028950 # number of times the integer registers were read +system.cpu.num_int_register_writes 636431660 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35626519 # number of memory refs -system.cpu.num_load_insts 27217784 # Number of load instructions +system.cpu.num_mem_refs 35626517 # number of memory refs +system.cpu.num_load_insts 27217782 # Number of load instructions system.cpu.num_store_insts 8408735 # Number of store instructions -system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles -system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles +system.cpu.num_idle_cycles 9770605328.086651 # Number of idle cycles +system.cpu.num_busy_cycles 453481202.913350 # Number of busy cycles system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955646 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790795 # number of replacements +system.cpu.icache.replacements 790793 # number of replacements system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks. +system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.549904 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy @@ -249,18 +249,18 @@ system.cpu.icache.demand_hits::cpu.inst 243365777 # nu system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits system.cpu.icache.overall_hits::total 243365777 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses -system.cpu.icache.overall_misses::total 791314 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses +system.cpu.icache.overall_misses::total 791312 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244157089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244157089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244157089 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244157089 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244157089 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244157089 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses @@ -278,29 +278,29 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.writebacks::writebacks 809 # number of writebacks system.cpu.icache.writebacks::total 809 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3435 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3335 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) @@ -309,12 +309,12 @@ system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349939 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.349881 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.349881 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,42 +323,42 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks +system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7755 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses +system.cpu.dtb_walker_cache.replacements 7598 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409620 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409620 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409620 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,42 +367,42 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621277 # number of replacements -system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use -system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1621273 # number of replacements +system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use +system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits -system.cpu.dcache.overall_hits::total 20139962 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses +system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits +system.cpu.dcache.overall_hits::total 20139960 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses system.cpu.dcache.overall_misses::total 1624057 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses @@ -419,8 +419,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks -system.cpu.dcache.writebacks::total 1525559 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks +system.cpu.dcache.writebacks::total 1534981 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |