diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 608 |
1 files changed, 304 insertions, 304 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index fb87772ef..55530e4a5 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112041 # Number of seconds simulated -sim_ticks 5112040970500 # Number of ticks simulated -final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112100 # Number of seconds simulated +sim_ticks 5112099860500 # Number of ticks simulated +final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1074050 # Simulator instruction rate (inst/s) -host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27479001055 # Simulator tick rate (ticks/s) -host_mem_usage 583620 # Number of bytes of host memory used -host_seconds 186.03 # Real time elapsed on the host -sim_insts 199810242 # Number of instructions simulated -sim_ops 409125913 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory +host_inst_rate 1028107 # Simulator instruction rate (inst/s) +host_op_rate 2105009 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26291327617 # Simulator tick rate (ticks/s) +host_mem_usage 628192 # Number of bytes of host memory used +host_seconds 194.44 # Real time elapsed on the host +sim_insts 199905607 # Number of instructions simulated +sim_ops 409299132 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory -system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory -system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory +system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9264448 # Number of bytes written to this memory +system.physmem.bytes_written::total 9264448 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37827 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165706 # Number of read requests responded to by this memory +system.physmem.num_reads::total 216864 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 144757 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144757 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 473568 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2074526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2714989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1812259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1812259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1812259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 473568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2074526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4527248 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -189,31 +189,31 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests -system.iocache.replacements 47569 # number of replacements -system.iocache.tagsinuse 0.042402 # Cycle average of tags in use +system.iocache.replacements 47568 # number of replacements +system.iocache.tagsinuse 0.042441 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses +system.iocache.ReadReq_misses::total 903 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses -system.iocache.demand_misses::total 47624 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses -system.iocache.overall_misses::total 47624 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses +system.iocache.demand_misses::total 47623 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses +system.iocache.overall_misses::total 47623 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,63 +245,63 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224081964 # number of cpu cycles simulated +system.cpu.numCycles 10224199744 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199810242 # Number of instructions committed -system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses +system.cpu.committedInsts 199905607 # Number of instructions committed +system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374462045 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls -system.cpu.num_int_insts 374289904 # number of integer instructions +system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls +system.cpu.num_int_insts 374462045 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read -system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written +system.cpu.num_int_register_reads 915890298 # number of times the integer registers were read +system.cpu.num_int_register_writes 480542887 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35624590 # number of memory refs -system.cpu.num_load_insts 27216588 # Number of load instructions -system.cpu.num_store_insts 8408002 # Number of store instructions -system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles -system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles -system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955647 # Percentage of idle cycles +system.cpu.num_mem_refs 35654170 # number of memory refs +system.cpu.num_load_insts 27234345 # Number of load instructions +system.cpu.num_store_insts 8419825 # Number of store instructions +system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles +system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles +system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955627 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790732 # number of replacements -system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use -system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits -system.cpu.icache.overall_hits::total 243360727 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses -system.cpu.icache.overall_misses::total 791251 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses +system.cpu.icache.replacements 790584 # number of replacements +system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use +system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits +system.cpu.icache.overall_hits::total 243492014 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses +system.cpu.icache.overall_misses::total 791103 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -311,43 +311,43 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3335 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3477 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -356,42 +356,42 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks +system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7597 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses +system.cpu.dtb_walker_cache.replacements 7629 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12955 # 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number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21774 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21774 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21774 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21774 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21774 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405024 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405024 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405024 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405024 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405024 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405024 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,50 +400,50 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621135 # number of replacements -system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use -system.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1621965 # number of replacements +system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use +system.cpu.dcache.total_refs 20168700 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622477 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.430808 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits -system.cpu.dcache.overall_hits::total 20138169 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses -system.cpu.dcache.overall_misses::total 1623919 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12073043 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12073043 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8093389 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8093389 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20166432 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20166432 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20166432 # number of overall hits +system.cpu.dcache.overall_hits::total 20166432 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308511 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308511 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316250 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316250 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624761 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624761 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624761 # number of overall misses +system.cpu.dcache.overall_misses::total 1624761 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8409639 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21791193 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097785 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097785 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037606 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037606 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074560 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -452,106 +452,106 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks -system.cpu.dcache.writebacks::total 1534848 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535695 # number of writebacks +system.cpu.dcache.writebacks::total 1535695 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 106558 # number of replacements -system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 105930 # number of replacements +system.cpu.l2cache.tagsinuse 64821.868749 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3456653 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 20.326318 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 51906.789291 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10424.349245 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # 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miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -560,8 +560,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks -system.cpu.l2cache.writebacks::total 98530 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98090 # number of writebacks +system.cpu.l2cache.writebacks::total 98090 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |