diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 827 |
1 files changed, 476 insertions, 351 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index b0c415fa9..ec6df0068 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,89 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112126 # Number of seconds simulated -sim_ticks 5112125984500 # Number of ticks simulated -final_tick 5112125984500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112127 # Number of seconds simulated +sim_ticks 5112126720000 # Number of ticks simulated +final_tick 5112126720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1274105 # Simulator instruction rate (inst/s) -host_op_rate 2608650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32578287771 # Simulator tick rate (ticks/s) -host_mem_usage 593532 # Number of bytes of host memory used -host_seconds 156.92 # Real time elapsed on the host -sim_insts 199930130 # Number of instructions simulated -sim_ops 409344539 # Number of ops (including micro ops) simulated +host_inst_rate 1627732 # Simulator instruction rate (inst/s) +host_op_rate 3332615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41616843658 # Simulator tick rate (ticks/s) +host_mem_usage 647148 # Number of bytes of host memory used +host_seconds 122.84 # Real time elapsed on the host +sim_insts 199947158 # Number of instructions simulated +sim_ops 409371517 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 852800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10650880 # Number of bytes read from this memory -system.physmem.bytes_read::total 11532416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 852800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 852800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6281856 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 852352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10669504 # Number of bytes read from this memory +system.physmem.bytes_read::total 11550592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 852352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 852352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6285632 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9271936 # Number of bytes written to this memory +system.physmem.bytes_written::total 9275712 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 13325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 166420 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180194 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 98154 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 13318 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 166711 # Number of read requests responded to by this memory +system.physmem.num_reads::total 180478 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 98213 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144874 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144933 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 166819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2083454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2255894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 166819 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 166819 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1228815 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 584900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1813714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1228815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 590446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 166731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2087097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2259449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 166731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 166731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1229553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 584899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1814453 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1229553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 590445 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 166819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2083454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4069609 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9050072 # Throughput (bytes/s) -system.membus.data_through_bus 46265107 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.042447 # Cycle average of tags in use +system.physmem.bw_total::cpu.inst 166731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2087097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4073902 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 13903648 # Transaction distribution +system.membus.trans_dist::ReadResp 13903648 # Transaction distribution +system.membus.trans_dist::WriteReq 13796 # Transaction distribution +system.membus.trans_dist::WriteResp 13796 # Transaction distribution +system.membus.trans_dist::Writeback 98213 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2521 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2092 # Transaction distribution +system.membus.trans_dist::ReadExReq 134490 # Transaction distribution +system.membus.trans_dist::ReadExResp 134485 # Transaction distribution +system.membus.trans_dist::MessageReq 1696 # Transaction distribution +system.membus.trans_dist::MessageResp 1696 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20043728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28204873 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28303521 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10027982 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17807872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43232339 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46287315 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 328402 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 328402 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 328402 # Request fanout histogram +system.iocache.tags.replacements 47573 # number of replacements +system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042447 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 4994846765009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428616 # Number of tag accesses -system.iocache.tags.data_accesses 428616 # Number of data accesses +system.iocache.tags.tag_accesses 428652 # Number of tag accesses +system.iocache.tags.data_accesses 428652 # Number of data accesses system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses -system.iocache.demand_misses::total 904 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses -system.iocache.overall_misses::total 904 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses +system.iocache.demand_misses::total 908 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses +system.iocache.overall_misses::total 908 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses @@ -111,39 +151,92 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 2555207 # Throughput (bytes/s) -system.iobus.data_through_bus 13062542 # Total data (bytes) +system.iobus.trans_dist::ReadReq 10011915 # Transaction distribution +system.iobus.trans_dist::ReadResp 10011915 # Transaction distribution +system.iobus.trans_dist::WriteReq 57577 # Transaction distribution +system.iobus.trans_dist::WriteResp 10857 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.iobus.trans_dist::MessageReq 1696 # Transaction distribution +system.iobus.trans_dist::MessageResp 1696 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27352 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 20043728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 20142376 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13676 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 10027982 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 13062574 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10224253344 # number of cpu cycles simulated +system.cpu.numCycles 10224257410 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199930130 # Number of instructions committed -system.cpu.committedOps 409344539 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374365317 # Number of integer alu accesses +system.cpu.committedInsts 199947158 # Number of instructions committed +system.cpu.committedOps 409371517 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374392167 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2307745 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39976374 # number of instructions that are conditional controls -system.cpu.num_int_insts 374365317 # number of integer instructions +system.cpu.num_func_calls 2307997 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39978602 # number of instructions that are conditional controls +system.cpu.num_int_insts 374392167 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 682286798 # number of times the integer registers were read -system.cpu.num_int_register_writes 323369753 # number of times the integer registers were written +system.cpu.num_int_register_reads 682348609 # number of times the integer registers were read +system.cpu.num_int_register_writes 323388730 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 233715334 # number of times the CC registers were read -system.cpu.num_cc_register_writes 157233726 # number of times the CC registers were written -system.cpu.num_mem_refs 35661072 # number of memory refs -system.cpu.num_load_insts 27238907 # Number of load instructions -system.cpu.num_store_insts 8422165 # Number of store instructions -system.cpu.num_idle_cycles 9770516870.697727 # Number of idle cycles -system.cpu.num_busy_cycles 453736473.302274 # Number of busy cycles -system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955622 # Percentage of idle cycles -system.cpu.Branches 43125613 # Number of branches fetched -system.cpu.op_class::No_OpClass 175318 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 373241846 91.18% 91.22% # Class of executed instruction -system.cpu.op_class::IntMult 144365 0.04% 91.26% # Class of executed instruction -system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction +system.cpu.num_cc_register_reads 233729759 # number of times the CC registers were read +system.cpu.num_cc_register_writes 157242019 # number of times the CC registers were written +system.cpu.num_mem_refs 35671209 # number of memory refs +system.cpu.num_load_insts 27243676 # Number of load instructions +system.cpu.num_store_insts 8427533 # Number of store instructions +system.cpu.num_idle_cycles 9770491320.524229 # Number of idle cycles +system.cpu.num_busy_cycles 453766089.475771 # Number of busy cycles +system.cpu.not_idle_fraction 0.044381 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955619 # Percentage of idle cycles +system.cpu.Branches 43128209 # Number of branches fetched +system.cpu.op_class::No_OpClass 175380 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 373258577 91.18% 91.22% # Class of executed instruction +system.cpu.op_class::IntMult 144442 0.04% 91.26% # Class of executed instruction +system.cpu.op_class::IntDiv 122944 0.03% 91.29% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction @@ -170,18 +263,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction -system.cpu.op_class::MemRead 27238907 6.65% 97.94% # Class of executed instruction -system.cpu.op_class::MemWrite 8422165 2.06% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 27243676 6.65% 97.94% # Class of executed instruction +system.cpu.op_class::MemWrite 8427533 2.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 409345569 # Class of executed instruction +system.cpu.op_class::total 409372552 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 790679 # number of replacements +system.cpu.icache.tags.replacements 791918 # number of replacements system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243526070 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791191 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.796815 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 243546972 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 792430 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.341938 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy @@ -189,34 +282,35 @@ system.cpu.icache.tags.occ_percent::total 0.997393 # A system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 245108466 # Number of tag accesses -system.cpu.icache.tags.data_accesses 245108466 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 243526070 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243526070 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243526070 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243526070 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243526070 # number of overall hits -system.cpu.icache.overall_hits::total 243526070 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791198 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791198 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791198 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791198 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791198 # number of overall misses -system.cpu.icache.overall_misses::total 791198 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244317268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244317268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244317268 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244317268 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244317268 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244317268 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 245131846 # Number of tag accesses +system.cpu.icache.tags.data_accesses 245131846 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243546972 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243546972 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243546972 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243546972 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243546972 # number of overall hits +system.cpu.icache.overall_hits::total 243546972 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792437 # number of overall misses +system.cpu.icache.overall_misses::total 792437 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244339409 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244339409 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244339409 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244339409 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244339409 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244339409 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -226,50 +320,51 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.026310 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5102111082500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026310 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.026447 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5102112149000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026447 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 28774 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 28774 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29024 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29024 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7640 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7640 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7642 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7642 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7642 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4580 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4580 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4580 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4580 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4580 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4580 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374795 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374795 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374734 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.374734 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374734 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.374734 # miss rate for overall accesses system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,49 +373,49 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks +system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.014183 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12951 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.694270 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5100459675500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014183 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52390 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52390 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12959 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12959 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12959 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12959 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12959 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12959 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21783 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21783 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21783 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21783 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21783 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21783 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405087 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405087 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405087 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405087 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405087 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405087 # miss rate for overall accesses +system.cpu.dtb_walker_cache.tags.replacements 8177 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.013955 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12514 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 8191 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.527774 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101283486500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013955 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53146 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53146 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12515 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12515 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12515 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12515 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12515 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12515 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9372 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9372 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9372 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9372 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9372 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9372 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21887 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21887 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21887 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21887 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21887 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21887 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428199 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428199 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428199 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428199 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428199 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428199 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -329,65 +424,65 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2797 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2797 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622084 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20175355 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622596 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.433998 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1623316 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20184260 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623828 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.430048 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88814480 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88814480 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12018728 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12018728 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8095451 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8095451 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58906 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58906 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20114179 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20114179 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20173085 # number of overall hits -system.cpu.dcache.overall_hits::total 20173085 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905666 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905666 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316462 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316462 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402754 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402754 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1222128 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1222128 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624882 # number of overall misses -system.cpu.dcache.overall_misses::total 1624882 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 12924394 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12924394 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8411913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8411913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461660 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461660 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21336307 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21336307 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21797967 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21797967 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070074 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070074 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872404 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872404 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074543 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074543 # miss rate for overall accesses +system.cpu.dcache.tags.tag_accesses 88856245 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88856245 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12022868 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12022868 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8100233 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8100233 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58899 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58899 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20123101 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20123101 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20182000 # number of overall hits +system.cpu.dcache.overall_hits::total 20182000 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 905995 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 905995 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317045 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317045 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403061 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403061 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1223040 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1223040 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1626101 # number of overall misses +system.cpu.dcache.overall_misses::total 1626101 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 12928863 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12928863 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8417278 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8417278 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461960 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461960 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21346141 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21346141 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21808101 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21808101 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070075 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070075 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037666 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037666 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872502 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872502 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057296 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057296 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074564 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074564 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,118 +491,148 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535815 # number of writebacks -system.cpu.dcache.writebacks::total 1535815 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1536734 # number of writebacks +system.cpu.dcache.writebacks::total 1536734 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 55211163 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 279231827 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 3014592 # Total snoop data (bytes) -system.cpu.l2cache.tags.replacements 105997 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64822.035422 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3456726 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 170125 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.318742 # Average number of references to valid blocks. +system.cpu.toL2Bus.trans_dist::ReadReq 15972635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 15972635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1540333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314785 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314785 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584874 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32530908 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21541 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 34147285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50715968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227701267 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 279540499 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 48008 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4020451 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108195 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3972823 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4020451 # Request fanout histogram +system.cpu.l2cache.tags.replacements 106060 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64822.097552 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3461863 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170171 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.343437 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51909.062113 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.541573 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.519483 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.551712 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.348992 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.792069 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20884 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39461 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32199668 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32199668 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 777860 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062710 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538774 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538774 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179729 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179729 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 777860 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1455273 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2242439 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 777860 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791185 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108287 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538774 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538774 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314187 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314187 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621977 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422474 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621977 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422474 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016842 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021618 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427955 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.427955 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016842 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1308415 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2111516 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1540333 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1540333 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1831 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1831 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314780 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314780 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7335 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792424 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1623195 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2426296 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7335 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792424 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1623195 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2426296 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024630 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021572 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987985 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987985 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428134 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428134 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102880 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074318 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102880 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074318 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,8 +641,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98154 # number of writebacks -system.cpu.l2cache.writebacks::total 98154 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98213 # number of writebacks +system.cpu.l2cache.writebacks::total 98213 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |