diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic')
-rwxr-xr-x | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout | 6 | ||||
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 194 |
2 files changed, 100 insertions, 100 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index f095afad7..451dd9824 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2013 09:59:18 -gem5 started Mar 28 2013 09:59:40 +gem5 compiled Apr 18 2013 13:37:41 +gem5 started Apr 18 2013 14:20:21 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112099860500 because m5_exit instruction encountered +Exiting @ tick 5112099861500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 55530e4a5..c125666af 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.112100 # Number of seconds simulated -sim_ticks 5112099860500 # Number of ticks simulated -final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5112099861500 # Number of ticks simulated +final_tick 5112099861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1028107 # Simulator instruction rate (inst/s) -host_op_rate 2105009 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26291327617 # Simulator tick rate (ticks/s) -host_mem_usage 628192 # Number of bytes of host memory used -host_seconds 194.44 # Real time elapsed on the host +host_inst_rate 1058684 # Simulator instruction rate (inst/s) +host_op_rate 2167614 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27073251373 # Simulator tick rate (ticks/s) +host_mem_usage 628224 # Number of bytes of host memory used +host_seconds 188.82 # Real time elapsed on the host sim_insts 199905607 # Number of instructions simulated -sim_ops 409299132 # Number of ops (including micro ops) simulated +sim_ops 409299164 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -194,7 +194,7 @@ system.iocache.tagsinuse 0.042441 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 4994822604059 # Cycle when the warmup percentage was hit. system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy @@ -245,57 +245,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224199744 # number of cpu cycles simulated +system.cpu.numCycles 10224199746 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 199905607 # Number of instructions committed -system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374462045 # Number of integer alu accesses +system.cpu.committedOps 409299164 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374462077 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls -system.cpu.num_int_insts 374462045 # number of integer instructions +system.cpu.num_conditional_control_insts 39972120 # number of instructions that are conditional controls +system.cpu.num_int_insts 374462077 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915890298 # number of times the integer registers were read -system.cpu.num_int_register_writes 480542887 # number of times the integer registers were written +system.cpu.num_int_register_reads 915890450 # number of times the integer registers were read +system.cpu.num_int_register_writes 480542967 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 35654170 # number of memory refs system.cpu.num_load_insts 27234345 # Number of load instructions system.cpu.num_store_insts 8419825 # Number of store instructions -system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles -system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles +system.cpu.num_idle_cycles 9770518373.401503 # Number of idle cycles +system.cpu.num_busy_cycles 453681372.598497 # Number of busy cycles system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955627 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.icache.replacements 790584 # number of replacements system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use -system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks. +system.cpu.icache.total_refs 243492011 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. +system.cpu.icache.avg_refs 307.790725 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 148824779500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits -system.cpu.icache.overall_hits::total 243492014 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 243492011 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243492011 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243492011 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243492011 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243492011 # number of overall hits +system.cpu.icache.overall_hits::total 243492011 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses system.cpu.icache.overall_misses::total 791103 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 244283114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244283114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244283114 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244283114 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244283114 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244283114 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses @@ -316,7 +316,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cy system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.warmup_cycle 5102064746500 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy @@ -364,7 +364,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cy system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.warmup_cycle 5100425402500 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy @@ -403,31 +403,31 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621965 # number of replacements +system.cpu.dcache.replacements 1621960 # number of replacements system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use -system.cpu.dcache.total_refs 20168700 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622477 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.430808 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.total_refs 20168705 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622472 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.430849 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7550500 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12073043 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12073043 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8093389 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8093389 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20166432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20166432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20166432 # number of overall hits -system.cpu.dcache.overall_hits::total 20166432 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308511 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308511 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316250 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316250 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624761 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624761 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624761 # number of overall misses -system.cpu.dcache.overall_misses::total 1624761 # number of overall misses +system.cpu.dcache.ReadReq_hits::cpu.data 12073184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12073184 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8093253 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8093253 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20166437 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20166437 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20166437 # number of overall hits +system.cpu.dcache.overall_hits::total 20166437 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308370 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308370 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316386 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316386 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624756 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624756 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624756 # number of overall misses +system.cpu.dcache.overall_misses::total 1624756 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses) @@ -436,10 +436,10 @@ system.cpu.dcache.demand_accesses::cpu.data 21791193 # system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097785 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097785 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037606 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037606 # miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097774 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses @@ -452,56 +452,56 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535695 # number of writebacks -system.cpu.dcache.writebacks::total 1535695 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535700 # number of writebacks +system.cpu.dcache.writebacks::total 1535700 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 105930 # number of replacements -system.cpu.l2cache.tagsinuse 64821.868749 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3456653 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 64819.953894 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3456507 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.326318 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 20.325460 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51906.789291 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 51906.788142 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10424.349245 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2490.593014 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10422.435538 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.159063 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989103 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989074 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062699 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538634 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538634 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275492 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062560 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1538639 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538639 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179586 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179586 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179720 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1455217 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2242285 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1455212 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2242280 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1455217 # number of overall hits -system.cpu.l2cache.overall_hits::total 2242285 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1455212 # number of overall hits +system.cpu.l2cache.overall_hits::total 2242280 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32248 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 45580 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134391 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134391 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134393 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134393 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses @@ -515,33 +515,33 @@ system.cpu.l2cache.overall_misses::total 179971 # nu system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307879 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108279 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538634 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538634 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307738 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2108138 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1538639 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538639 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313977 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313977 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314113 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314113 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621856 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422256 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621851 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2422251 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621856 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422256 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621851 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2422251 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024658 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428028 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428028 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427849 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.427849 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses |