diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/x86/linux')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 78 | ||||
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt | 2017 |
2 files changed, 1053 insertions, 1042 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index fee5e3090..838105743 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu sim_ticks 5112152301500 # Number of ticks simulated final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1340669 # Simulator instruction rate (inst/s) -host_op_rate 2744641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34257071569 # Simulator tick rate (ticks/s) -host_mem_usage 654012 # Number of bytes of host memory used -host_seconds 149.23 # Real time elapsed on the host +host_inst_rate 1349307 # Simulator instruction rate (inst/s) +host_op_rate 2762327 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34477807791 # Simulator tick rate (ticks/s) +host_mem_usage 659588 # Number of bytes of host memory used +host_seconds 148.27 # Real time elapsed on the host sim_insts 200066731 # Number of instructions simulated sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -337,9 +337,9 @@ system.cpu.itb_walker_cache.writebacks::total 545 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 106193 # number of replacements system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4345511 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4340112 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 170151 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.539145 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.507414 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor @@ -359,8 +359,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39306136 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39306136 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 39255968 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39255968 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 1538777 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1538777 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits @@ -456,42 +456,48 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 98168 # number of writebacks system.cpu.l2cache.writebacks::total 98168 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1538777 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 886676 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880405 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 792735 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321418 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377686 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 35029733 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377675 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613331 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 279335545 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 49698 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18776912 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.002627 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051183 # Request fanout histogram +system.cpu.toL2Bus.snoops 203459 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18930673 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 18727593 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 49319 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18911114 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18776912 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18930673 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution @@ -600,7 +606,7 @@ system.membus.trans_dist::ReadResp 13903747 # Tr system.membus.trans_dist::WriteReq 13943 # Transaction distribution system.membus.trans_dist::WriteResp 13943 # Transaction distribution system.membus.trans_dist::Writeback 144835 # Transaction distribution -system.membus.trans_dist::CleanEvict 9844 # Transaction distribution +system.membus.trans_dist::CleanEvict 8392 # Transaction distribution system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution system.membus.trans_dist::ReadExReq 134360 # Transaction distribution @@ -614,11 +620,11 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 471480 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28214040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28360246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28213119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28358794 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) @@ -629,17 +635,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 46269945 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 14257691 # Request fanout histogram +system.membus.snoop_fanout::samples 14256770 # Request fanout histogram system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 14255995 99.99% 99.99% # Request fanout histogram +system.membus.snoop_fanout::1 14255074 99.99% 99.99% # Request fanout histogram system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 14257691 # Request fanout histogram +system.membus.snoop_fanout::total 14256770 # Request fanout histogram system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 2f3799b17..aa1e69b35 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.184733 # Number of seconds simulated -sim_ticks 5184732721500 # Number of ticks simulated -final_tick 5184732721500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.194921 # Number of seconds simulated +sim_ticks 5194921252500 # Number of ticks simulated +final_tick 5194921252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 808289 # Simulator instruction rate (inst/s) -host_op_rate 1558079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32570584041 # Simulator tick rate (ticks/s) -host_mem_usage 654268 # Number of bytes of host memory used -host_seconds 159.18 # Real time elapsed on the host -sim_insts 128667033 # Number of instructions simulated -sim_ops 248022101 # Number of ops (including micro ops) simulated +host_inst_rate 862150 # Simulator instruction rate (inst/s) +host_op_rate 1661827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34815163679 # Simulator tick rate (ticks/s) +host_mem_usage 660376 # Number of bytes of host memory used +host_seconds 149.21 # Real time elapsed on the host +sim_insts 128645146 # Number of instructions simulated +sim_ops 247968367 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9044928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 824576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8975232 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9898944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8133056 # Number of bytes written to this memory -system.physmem.bytes_written::total 8133056 # Number of bytes written to this memory +system.physmem.bytes_read::total 9828480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8074432 # Number of bytes written to this memory +system.physmem.bytes_written::total 8074432 # Number of bytes written to this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141327 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12884 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140238 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154671 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 127079 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127079 # Number of write requests responded to by this memory +system.physmem.num_reads::total 153570 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126163 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1744531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1909249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159187 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159187 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1568655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1568655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1568655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1727694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1891940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1554293 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1554293 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1554293 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1744531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3477903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154671 # Number of read requests accepted -system.physmem.writeReqs 127079 # Number of write requests accepted -system.physmem.readBursts 154671 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 127079 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9888768 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu.inst 158727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1727694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3446234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 153570 # Number of read requests accepted +system.physmem.writeReqs 126163 # Number of write requests accepted +system.physmem.readBursts 153570 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 126163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9818304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 8131392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9898944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8133056 # Total written bytes from the system interface side +system.physmem.bytesWritten 8073216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9828480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8074432 # Total written bytes from the system interface side system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48348 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9772 # Per bank write bursts -system.physmem.perBankRdBursts::1 9412 # Per bank write bursts -system.physmem.perBankRdBursts::2 9829 # Per bank write bursts -system.physmem.perBankRdBursts::3 9622 # Per bank write bursts -system.physmem.perBankRdBursts::4 9563 # Per bank write bursts -system.physmem.perBankRdBursts::5 9355 # Per bank write bursts -system.physmem.perBankRdBursts::6 9720 # Per bank write bursts -system.physmem.perBankRdBursts::7 9664 # Per bank write bursts -system.physmem.perBankRdBursts::8 9219 # Per bank write bursts -system.physmem.perBankRdBursts::9 9313 # Per bank write bursts -system.physmem.perBankRdBursts::10 9431 # Per bank write bursts -system.physmem.perBankRdBursts::11 9415 # Per bank write bursts -system.physmem.perBankRdBursts::12 9985 # Per bank write bursts -system.physmem.perBankRdBursts::13 10194 # Per bank write bursts -system.physmem.perBankRdBursts::14 10163 # Per bank write bursts -system.physmem.perBankRdBursts::15 9855 # Per bank write bursts -system.physmem.perBankWrBursts::0 8316 # Per bank write bursts -system.physmem.perBankWrBursts::1 7960 # Per bank write bursts -system.physmem.perBankWrBursts::2 8144 # Per bank write bursts -system.physmem.perBankWrBursts::3 8236 # Per bank write bursts -system.physmem.perBankWrBursts::4 8504 # Per bank write bursts -system.physmem.perBankWrBursts::5 7731 # Per bank write bursts -system.physmem.perBankWrBursts::6 7974 # Per bank write bursts -system.physmem.perBankWrBursts::7 7835 # Per bank write bursts -system.physmem.perBankWrBursts::8 7118 # Per bank write bursts -system.physmem.perBankWrBursts::9 7555 # Per bank write bursts -system.physmem.perBankWrBursts::10 7609 # Per bank write bursts -system.physmem.perBankWrBursts::11 7637 # Per bank write bursts -system.physmem.perBankWrBursts::12 8092 # Per bank write bursts -system.physmem.perBankWrBursts::13 8095 # Per bank write bursts -system.physmem.perBankWrBursts::14 8240 # Per bank write bursts -system.physmem.perBankWrBursts::15 8007 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48373 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9606 # Per bank write bursts +system.physmem.perBankRdBursts::1 9083 # Per bank write bursts +system.physmem.perBankRdBursts::2 10021 # Per bank write bursts +system.physmem.perBankRdBursts::3 9578 # Per bank write bursts +system.physmem.perBankRdBursts::4 9425 # Per bank write bursts +system.physmem.perBankRdBursts::5 9133 # Per bank write bursts +system.physmem.perBankRdBursts::6 9428 # Per bank write bursts +system.physmem.perBankRdBursts::7 9379 # Per bank write bursts +system.physmem.perBankRdBursts::8 9296 # Per bank write bursts +system.physmem.perBankRdBursts::9 9532 # Per bank write bursts +system.physmem.perBankRdBursts::10 9485 # Per bank write bursts +system.physmem.perBankRdBursts::11 9788 # Per bank write bursts +system.physmem.perBankRdBursts::12 9982 # Per bank write bursts +system.physmem.perBankRdBursts::13 10070 # Per bank write bursts +system.physmem.perBankRdBursts::14 9926 # Per bank write bursts +system.physmem.perBankRdBursts::15 9679 # Per bank write bursts +system.physmem.perBankWrBursts::0 8208 # Per bank write bursts +system.physmem.perBankWrBursts::1 7344 # Per bank write bursts +system.physmem.perBankWrBursts::2 8031 # Per bank write bursts +system.physmem.perBankWrBursts::3 7623 # Per bank write bursts +system.physmem.perBankWrBursts::4 7645 # Per bank write bursts +system.physmem.perBankWrBursts::5 7565 # Per bank write bursts +system.physmem.perBankWrBursts::6 7708 # Per bank write bursts +system.physmem.perBankWrBursts::7 7791 # Per bank write bursts +system.physmem.perBankWrBursts::8 7759 # Per bank write bursts +system.physmem.perBankWrBursts::9 7930 # Per bank write bursts +system.physmem.perBankWrBursts::10 7732 # Per bank write bursts +system.physmem.perBankWrBursts::11 7853 # Per bank write bursts +system.physmem.perBankWrBursts::12 8038 # Per bank write bursts +system.physmem.perBankWrBursts::13 8512 # Per bank write bursts +system.physmem.perBankWrBursts::14 8378 # Per bank write bursts +system.physmem.perBankWrBursts::15 8027 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 5184732588500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5194921069000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154671 # Read request sizes (log2) +system.physmem.readPktSize::6 153570 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 127079 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126163 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -152,189 +152,188 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 55882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.466912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.971568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.231986 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19566 35.01% 35.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13855 24.79% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5752 10.29% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3280 5.87% 75.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2436 4.36% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1597 2.86% 83.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1106 1.98% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 958 1.71% 86.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7332 13.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 55882 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5902 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.177906 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 623.301246 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5901 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::51 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 55967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.678668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.248377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.031309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19371 34.61% 34.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13720 24.51% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6335 11.32% 70.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3428 6.13% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2404 4.30% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1641 2.93% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1130 2.02% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 964 1.72% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6974 12.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 55967 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5838 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.276465 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 626.709863 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5837 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5902 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5902 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.527109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.363013 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.814592 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4841 82.02% 82.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 49 0.83% 82.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 261 4.42% 87.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 70 1.19% 88.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 69 1.17% 89.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 251 4.25% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.37% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 13 0.22% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.25% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.12% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 235 3.98% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.14% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.46% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5902 # Writes before turning the bus around for reads -system.physmem.totQLat 1454171981 # Total ticks spent queuing -system.physmem.totMemAccLat 4351271981 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9411.39 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5838 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5838 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.607400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.425561 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.518520 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4794 82.12% 82.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 110 1.88% 84.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 38 0.65% 84.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 229 3.92% 88.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 28 0.48% 89.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 201 3.44% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 72 1.23% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 93.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.21% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 30 0.51% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.10% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 233 3.99% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 31 0.53% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.27% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5838 # Writes before turning the bus around for reads +system.physmem.totQLat 1519267484 # Total ticks spent queuing +system.physmem.totMemAccLat 4395723734 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 767055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9903.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28161.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28653.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 126926 # Number of row buffer hits during reads -system.physmem.writeRowHits 98756 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.71 # Row buffer hit rate for writes -system.physmem.avgGap 18401890.29 # Average gap between requests -system.physmem.pageHitRate 80.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 207522000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 113231250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 600100800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 419256000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 134001495225 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2993293881750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3467276945505 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.747605 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4979520185732 # Time in different power states -system.physmem_0.memoryStateTime::REF 173129580000 # Time in different power states +system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing +system.physmem.readRowHits 125316 # Number of row buffer hits during reads +system.physmem.writeRowHits 98271 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.89 # Row buffer hit rate for writes +system.physmem.avgGap 18570998.31 # Average gap between requests +system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 205775640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 112278375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 590093400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 401209200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 136710410535 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2997028289250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3474354711360 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.798995 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4985717898976 # Time in different power states +system.physmem_0.memoryStateTime::REF 173469660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32082834268 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35728624774 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214945920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 117282000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 605085000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 404047440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 134530881300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2992829508000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3467343208140 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.760386 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4978746411720 # Time in different power states -system.physmem_1.memoryStateTime::REF 173129580000 # Time in different power states +system.physmem_1.actEnergy 217334880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118585500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 606504600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 416203920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 137303657415 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2996507897250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3474476838525 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.822504 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4984854152228 # Time in different power states +system.physmem_1.memoryStateTime::REF 173469660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32855777030 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36597268272 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10369465443 # number of cpu cycles simulated +system.cpu.numCycles 10389842505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128667033 # Number of instructions committed -system.cpu.committedOps 248022101 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232599125 # Number of integer alu accesses +system.cpu.committedInsts 128645146 # Number of instructions committed +system.cpu.committedOps 247968367 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232546073 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2317363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23194478 # number of instructions that are conditional controls -system.cpu.num_int_insts 232599125 # number of integer instructions +system.cpu.num_func_calls 2315361 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23194066 # number of instructions that are conditional controls +system.cpu.num_int_insts 232546073 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 435753384 # number of times the integer registers were read -system.cpu.num_int_register_writes 198362025 # number of times the integer registers were written +system.cpu.num_int_register_reads 435625867 # number of times the integer registers were read +system.cpu.num_int_register_writes 198317571 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133133176 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95670461 # number of times the CC registers were written -system.cpu.num_mem_refs 22356642 # number of memory refs -system.cpu.num_load_insts 13946240 # Number of load instructions -system.cpu.num_store_insts 8410402 # Number of store instructions -system.cpu.num_idle_cycles 9769457503.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600007939.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057863 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942137 # Percentage of idle cycles -system.cpu.Branches 26370667 # Number of branches fetched -system.cpu.op_class::No_OpClass 172538 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225235379 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140393 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 123647 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 133116487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95666128 # number of times the CC registers were written +system.cpu.num_mem_refs 22339099 # number of memory refs +system.cpu.num_load_insts 13935933 # Number of load instructions +system.cpu.num_store_insts 8403166 # Number of store instructions +system.cpu.num_idle_cycles 9774871363.998119 # Number of idle cycles +system.cpu.num_busy_cycles 614971141.001882 # Number of busy cycles +system.cpu.not_idle_fraction 0.059190 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940810 # Percentage of idle cycles +system.cpu.Branches 26367781 # Number of branches fetched +system.cpu.op_class::No_OpClass 172241 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 225200251 90.82% 90.89% # Class of executed instruction +system.cpu.op_class::IntMult 140056 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 123237 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -361,215 +360,215 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13941273 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8410402 3.39% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13930961 5.62% 96.61% # Class of executed instruction +system.cpu.op_class::MemWrite 8403166 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 248023648 # Class of executed instruction +system.cpu.op_class::total 247969928 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1621027 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996962 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20151381 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1621539 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.427318 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54359500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996962 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1623328 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995361 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20131143 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623840 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.397245 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995361 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88751069 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88751069 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12012436 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12012436 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8077606 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8077606 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59170 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59170 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20090042 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20090042 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20149212 # number of overall hits -system.cpu.dcache.overall_hits::total 20149212 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905821 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905821 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 324802 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 324802 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402538 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402538 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1230623 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1230623 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1633161 # number of overall misses -system.cpu.dcache.overall_misses::total 1633161 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12812474000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12812474000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12127378479 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12127378479 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24939852479 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24939852479 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24939852479 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24939852479 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12918257 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12918257 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8402408 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8402408 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461708 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461708 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21320665 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21320665 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21782373 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21782373 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070119 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070119 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038656 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038656 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871845 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871845 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057720 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057720 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074976 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074976 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14144.598105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14144.598105 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37337.758016 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37337.758016 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20266.037998 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20266.037998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15270.908673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15270.908673 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5798 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88683234 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88683234 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12000893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12000893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8069415 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8069415 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58662 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58662 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20070308 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20070308 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20128970 # number of overall hits +system.cpu.dcache.overall_hits::total 20128970 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906883 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906883 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325772 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403210 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403210 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1232655 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1232655 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1635865 # number of overall misses +system.cpu.dcache.overall_misses::total 1635865 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13550557000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13550557000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18295357977 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18295357977 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31845914977 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31845914977 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31845914977 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31845914977 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12907776 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12907776 # 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miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038805 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872991 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872991 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075161 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075161 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.902098 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.902098 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56160.007542 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56160.007542 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25835.221515 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25835.221515 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19467.324612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19467.324612 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15094 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 441 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.527778 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.226757 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1537873 # number of writebacks -system.cpu.dcache.writebacks::total 1537873 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9093 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9093 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9381 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9381 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9381 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9381 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 905533 # 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number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 403174 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1222893 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1222893 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1626067 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1626067 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 572954 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 572954 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 586870 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 586870 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11904745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11904745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11312729479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11312729479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5814985000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5814985000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23217474979 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23217474979 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29032459979 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29032459979 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684333500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684333500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622247500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622247500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97306581000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 97306581000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070097 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070097 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037574 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037574 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871772 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871772 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057280 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057280 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074544 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074544 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.672181 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.672181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35832.774736 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35832.774736 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14447.024129 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14447.024129 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19011.363005 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19011.363005 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17879.927020 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17879.927020 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.431581 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.431581 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188433.996838 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188433.996838 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165806.023480 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165806.023480 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 586874 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 586874 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12641489000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12641489000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17000944477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17000944477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6508610000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6508610000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29642433477 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29642433477 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36151043477 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36151043477 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684331000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684331000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622740500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622740500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97307071500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 97307071500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070236 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070236 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872913 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872913 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057405 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057405 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074711 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074711 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.982457 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.982457 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53749.089405 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53749.089405 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16143.426907 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16143.426907 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24239.596986 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24239.596986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22232.197983 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22232.197983 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.427218 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.427218 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188415.265805 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188415.265805 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165805.729168 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165805.729168 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7782 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.044171 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13071 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7797 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.676414 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5158049844500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.044171 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315261 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315261 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 7724 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13169 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7738 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.701861 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5166372049500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53116 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53116 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13073 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13073 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13073 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13073 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13073 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13073 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8990 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8990 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8990 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8990 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8990 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8990 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97324000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97324000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97324000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 97324000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97324000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 97324000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22063 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22063 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22063 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22063 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22063 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22063 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407470 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407470 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407470 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407470 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407470 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407470 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10825.806452 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10825.806452 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10825.806452 # average overall miss latency +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13186 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13186 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13186 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13186 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13186 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13186 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8927 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8927 # 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number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22113 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22113 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22113 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22113 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22113 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22113 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403699 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403699 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403699 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403699 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403699 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403699 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10893.133191 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10893.133191 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10893.133191 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -578,86 +577,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8990 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8990 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8990 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8990 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8990 # 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Cycle average of tags in use -system.cpu.icache.tags.total_refs 144952019 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 793149 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.755093 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161555480500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.330403 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996739 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996739 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 789867 # number of replacements +system.cpu.icache.tags.tagsinuse 510.214824 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144930127 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 790379 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 183.367887 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 164495636500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.214824 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996513 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996513 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # 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number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145745175 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145745175 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145745175 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005442 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005442 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005442 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005442 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005442 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005442 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14148.103274 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14148.103274 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14148.103274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14148.103274 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146510899 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146510899 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144930127 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144930127 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144930127 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144930127 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144930127 # number of overall hits +system.cpu.icache.overall_hits::total 144930127 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145720513 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145720513 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145720513 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145720513 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145720513 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145720513 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005424 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005424 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005424 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005424 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005424 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005424 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14972.069976 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14972.069976 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14972.069976 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14972.069976 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14972.069976 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14972.069976 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -666,88 +665,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10428497000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10428497000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005442 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005442 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005442 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13148.103274 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13148.103274 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790386 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 790386 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 790386 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 790386 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 790386 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 790386 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11043328500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11043328500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11043328500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11043328500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11043328500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11043328500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005424 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005424 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005424 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13972.069976 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13972.069976 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13972.069976 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13972.069976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13972.069976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13972.069976 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3538 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.060279 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7930 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3549 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.234432 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161245744500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.060279 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191267 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191267 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3784 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.071212 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7587 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3797 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.998156 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5168596607500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071212 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191951 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191951 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 29062 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 29062 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7929 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7929 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29077 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29077 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7587 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7587 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7931 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7931 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7931 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7931 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4400 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4400 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4400 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4400 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4400 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4400 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45407000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45407000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45407000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 45407000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45407000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 45407000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12329 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12329 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7589 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7589 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7589 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7589 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4633 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4633 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4633 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4633 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4633 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4633 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48911500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48911500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48911500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 48911500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48911500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 48911500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12331 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12331 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12331 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12331 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356882 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356882 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356824 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.356824 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356824 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.356824 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10319.772727 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10319.772727 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10319.772727 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.379133 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.379133 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.379071 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.379071 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.379071 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.379071 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10557.198360 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10557.198360 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10557.198360 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,169 +755,169 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 796 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 796 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4400 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4400 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4400 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4400 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4400 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4400 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 41007000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 41007000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 41007000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 41007000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 41007000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 41007000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356882 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356882 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356824 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356824 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9319.772727 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 721 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 721 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4633 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4633 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4633 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4633 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4633 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4633 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 44278500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 44278500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 44278500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 44278500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 44278500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 44278500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.379133 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.379133 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.379071 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.379071 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.379071 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.379071 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9557.198360 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9557.198360 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87263 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64757.225173 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4369524 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151965 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 28.753489 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 86240 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64592.333945 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4367637 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 150989 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 28.926856 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50419.617435 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.145028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3328.329800 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11009.132909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.769342 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50133.527739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3457.643805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11001.015544 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.764977 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050786 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.167986 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.988117 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64702 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5302 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56392 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987274 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39224493 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39224493 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1541775 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1541775 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 307 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 307 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199754 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199754 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 780246 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 780246 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6724 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3018 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1278797 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1288539 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6724 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3018 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 780246 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1478551 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2268539 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6724 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3018 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 780246 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1478551 # number of overall hits -system.cpu.l2cache.overall_hits::total 2268539 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1367 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1367 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113781 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113781 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12897 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 12897 # number of ReadCleanReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052759 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.167862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.985601 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64749 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2897 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5100 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56598 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987991 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 39213781 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39213781 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 1544059 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1544059 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 298 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 298 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 201469 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 201469 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 777488 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 777488 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6514 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3101 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1280565 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121237.834692 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121237.834692 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121074.096808 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121073.470103 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.423727 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.423727 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176915.265805 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176915.265805 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.444651 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.444651 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4854729 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2424193 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1088 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1088 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 572954 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2687857 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1668857 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 884964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 793156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322272 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2686987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1670227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2186 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2186 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 790386 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378925 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6040657 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20226 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8448782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50761152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203819691 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 629120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255454379 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 189246 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5626152 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.032703 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.177859 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2370613 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6047740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8447236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50583872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204138427 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 601024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255568251 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 188441 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5624579 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004514 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.080591 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5442159 96.73% 96.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 183993 3.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5604820 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14130 0.25% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5629 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5626152 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4269812500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5624579 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4271820500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 480000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 588787 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1189734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1185579000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3013374987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3016848998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6600000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6949500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13485000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13390500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 226549 # Transaction distribution -system.iobus.trans_dist::ReadResp 226549 # Transaction distribution +system.iobus.trans_dist::ReadReq 226550 # Transaction distribution +system.iobus.trans_dist::ReadResp 226550 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 57726 # Transaction distribution -system.iobus.trans_dist::MessageReq 1652 # Transaction distribution -system.iobus.trans_dist::MessageResp 1652 # Transaction distribution +system.iobus.trans_dist::MessageReq 1654 # Transaction distribution +system.iobus.trans_dist::MessageResp 1654 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -1095,11 +1100,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 473420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 571854 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 571860 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1119,12 +1124,12 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 242990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276902 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3939784 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3276918 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1160,54 +1165,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 242362178 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 240989862 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 462414000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50042000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50044000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47510 # number of replacements -system.iocache.tags.tagsinuse 0.095938 # Cycle average of tags in use +system.iocache.tags.replacements 47511 # number of replacements +system.iocache.tags.tagsinuse 0.108299 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5046145075000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095938 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005996 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005996 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5048321264000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108299 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006769 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428085 # Number of tag accesses -system.iocache.tags.data_accesses 428085 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 845 # number of ReadReq misses -system.iocache.ReadReq_misses::total 845 # number of ReadReq misses +system.iocache.tags.tag_accesses 428094 # Number of tag accesses +system.iocache.tags.data_accesses 428094 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses +system.iocache.ReadReq_misses::total 846 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 845 # number of demand (read+write) misses -system.iocache.demand_misses::total 845 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 845 # number of overall misses -system.iocache.overall_misses::total 845 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 134017694 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 134017694 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5509470484 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5509470484 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 134017694 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 134017694 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 134017694 # number of overall miss cycles -system.iocache.overall_miss_latency::total 134017694 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 845 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 845 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses +system.iocache.demand_misses::total 846 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses +system.iocache.overall_misses::total 846 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144199688 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144199688 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6059543174 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6059543174 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144199688 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144199688 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144199688 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144199688 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 845 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 845 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 845 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 845 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1216,40 +1221,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158600.821302 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 117925.310017 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117925.310017 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 158600.821302 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 158600.821302 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 170448.803783 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129699.126156 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129699.126156 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 170448.803783 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 170448.803783 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 693 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 36 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.178571 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 19.250000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 845 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 845 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 845 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 845 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 845 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 91767694 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3173470484 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3173470484 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 91767694 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 91767694 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 101899688 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3723543174 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3723543174 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 101899688 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 101899688 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1258,73 +1263,73 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108600.821302 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67925.310017 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67925.310017 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 120448.803783 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79699.126156 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79699.126156 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 572954 # Transaction distribution -system.membus.trans_dist::ReadResp 615177 # Transaction distribution -system.membus.trans_dist::WriteReq 13916 # Transaction distribution -system.membus.trans_dist::WriteResp 13916 # Transaction distribution -system.membus.trans_dist::Writeback 127079 # Transaction distribution -system.membus.trans_dist::CleanEvict 7222 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2154 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1646 # Transaction distribution -system.membus.trans_dist::ReadExReq 113502 # Transaction distribution -system.membus.trans_dist::ReadExResp 113502 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42223 # Transaction distribution -system.membus.trans_dist::MessageReq 1652 # Transaction distribution -system.membus.trans_dist::MessageResp 1652 # Transaction distribution +system.membus.trans_dist::ReadResp 615200 # Transaction distribution +system.membus.trans_dist::WriteReq 13920 # Transaction distribution +system.membus.trans_dist::WriteResp 13920 # Transaction distribution +system.membus.trans_dist::Writeback 126163 # Transaction distribution +system.membus.trans_dist::CleanEvict 7113 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2165 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1671 # Transaction distribution +system.membus.trans_dist::ReadExReq 112377 # Transaction distribution +system.membus.trans_dist::ReadExResp 112377 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42246 # Transaction distribution +system.membus.trans_dist::MessageReq 1654 # Transaction distribution +system.membus.trans_dist::MessageResp 1654 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 473420 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 400152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1573892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141767 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141767 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1718963 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 396961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1570709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1715783 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242990 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15016960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16660587 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400653 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14887872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16531515 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19682235 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1580 # Total snoops (count) -system.membus.snoop_fanout::samples 927896 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001780 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.042157 # Request fanout histogram +system.membus.pkt_size::total 19553171 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1565 # Total snoops (count) +system.membus.snoop_fanout::samples 925791 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001787 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.042230 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 926244 99.82% 99.82% # Request fanout histogram -system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 924137 99.82% 99.82% # Request fanout histogram +system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 927896 # Request fanout histogram -system.membus.reqLayer0.occupancy 359896000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 925791 # Request fanout histogram +system.membus.reqLayer0.occupancy 359890000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 527973000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 527983500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 848970266 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 843164843 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2157850870 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2152042345 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 85904679 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 85908558 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |