diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/x86/linux')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 512 | ||||
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt | 162 |
2 files changed, 337 insertions, 337 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 5a613cfa1..551274795 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,184 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112043 # Number of seconds simulated -sim_ticks 5112043255000 # Number of ticks simulated -final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112041 # Number of seconds simulated +sim_ticks 5112040968500 # Number of ticks simulated +final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011485 # Simulator instruction rate (inst/s) -host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25877843451 # Simulator tick rate (ticks/s) -host_mem_usage 397304 # Number of bytes of host memory used -host_seconds 197.55 # Real time elapsed on the host -sim_insts 199813914 # Number of instructions simulated -sim_ops 409133298 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory +host_inst_rate 923075 # Simulator instruction rate (inst/s) +host_op_rate 1890063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23616389220 # Simulator tick rate (ticks/s) +host_mem_usage 353316 # Number of bytes of host memory used +host_seconds 216.46 # Real time elapsed on the host +sim_insts 199810236 # Number of instructions simulated +sim_ops 409125915 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory -system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory +system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory -system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory +system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 106561 # number of replacements -system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits -system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses -system.cpu.l2cache.overall_misses::total 179910 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks -system.cpu.l2cache.writebacks::total 98533 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47570 # number of replacements -system.iocache.tagsinuse 0.042409 # Cycle average of tags in use +system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) +system.iocache.replacements 47569 # number of replacements +system.iocache.tagsinuse 0.042402 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses +system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses -system.iocache.demand_misses::total 47625 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses -system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses +system.iocache.demand_misses::total 47624 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses +system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -200,7 +92,7 @@ system.iocache.writebacks::total 46667 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -210,57 +102,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224086531 # number of cpu cycles simulated +system.cpu.numCycles 10224081960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199813914 # Number of instructions committed -system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses +system.cpu.committedInsts 199810236 # Number of instructions committed +system.cpu.committedOps 409125915 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374289906 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls -system.cpu.num_int_insts 374297264 # number of integer instructions +system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls +system.cpu.num_int_insts 374289906 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915470380 # number of times the integer registers were read -system.cpu.num_int_register_writes 480331069 # number of times the integer registers were written +system.cpu.num_int_register_reads 915450684 # number of times the integer registers were read +system.cpu.num_int_register_writes 480322735 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35626517 # number of memory refs -system.cpu.num_load_insts 27217782 # Number of load instructions -system.cpu.num_store_insts 8408735 # Number of store instructions -system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles -system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles -system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955646 # Percentage of idle cycles +system.cpu.num_mem_refs 35624588 # number of memory refs +system.cpu.num_load_insts 27216588 # Number of load instructions +system.cpu.num_store_insts 8408000 # Number of store instructions +system.cpu.num_idle_cycles 9770609605.299961 # Number of idle cycles +system.cpu.num_busy_cycles 453472354.700038 # Number of busy cycles +system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955647 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790793 # number of replacements +system.cpu.icache.replacements 790732 # number of replacements system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use -system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks. +system.cpu.icache.total_refs 243360722 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.567226 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits -system.cpu.icache.overall_hits::total 243365779 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses -system.cpu.icache.overall_misses::total 791312 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243360722 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243360722 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243360722 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243360722 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243360722 # number of overall hits +system.cpu.icache.overall_hits::total 243360722 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses +system.cpu.icache.overall_misses::total 791251 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244151973 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244151973 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244151973 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244151973 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244151973 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244151973 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses @@ -277,14 +169,14 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3335 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use +system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.warmup_cycle 5102019603000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -324,39 +216,39 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7598 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses +system.cpu.dtb_walker_cache.replacements 7597 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101206381500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -368,39 +260,39 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621273 # number of replacements +system.cpu.dcache.replacements 1621135 # number of replacements system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use -system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20140429 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.419737 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits -system.cpu.dcache.overall_hits::total 20139960 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses -system.cpu.dcache.overall_misses::total 1624057 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8082226 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8082226 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20138167 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20138167 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20138167 # number of overall hits +system.cpu.dcache.overall_hits::total 20138167 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses +system.cpu.dcache.overall_misses::total 1623919 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8398054 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8398054 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21762086 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21762086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21762086 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21762086 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses @@ -417,8 +309,116 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks -system.cpu.dcache.writebacks::total 1534981 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks +system.cpu.dcache.writebacks::total 1534848 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 106558 # number of replacements +system.cpu.l2cache.tagsinuse 64822.149249 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.994085 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.564956 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits +system.cpu.l2cache.overall_hits::total 2241638 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses +system.cpu.l2cache.overall_misses::total 179909 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks +system.cpu.l2cache.writebacks::total 98530 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 358803d5d..b8216d15c 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.187896 # Nu sim_ticks 5187896410000 # Number of ticks simulated final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 834857 # Simulator instruction rate (inst/s) -host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33766110220 # Simulator tick rate (ticks/s) -host_mem_usage 354356 # Number of bytes of host memory used -host_seconds 153.64 # Real time elapsed on the host +host_inst_rate 812782 # Simulator instruction rate (inst/s) +host_op_rate 1566838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32873266023 # Simulator tick rate (ticks/s) +host_mem_usage 347504 # Number of bytes of host memory used +host_seconds 157.82 # Real time elapsed on the host sim_insts 128269216 # Number of instructions simulated sim_ops 247270559 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory @@ -59,14 +59,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130086932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130086932 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10826250092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10826250092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10826250092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10826250092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -83,19 +83,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155235.002387 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155235.002387 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227643.090374 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227643.090374 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 90078 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.170340 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -109,14 +109,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86510932 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86510932 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266723160 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8266723160 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8353234092 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8353234092 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -125,14 +125,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103235.002387 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 103235.002387 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176941.848459 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176941.848459 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -437,14 +437,14 @@ system.cpu.dcache.demand_misses::cpu.data 1621067 # n system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses system.cpu.dcache.overall_misses::total 1621067 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175236500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18175236500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175237000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18175237000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27078679000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27078679000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27078679000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27078679000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27078679500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27078679500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27078679500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27078679500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses) @@ -461,14 +461,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074870 system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843616 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843999 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843999 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16704.231842 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16704.231842 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16704.232151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16704.232151 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,20 +487,20 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1621067 system.cpu.dcache.demand_mshr_misses::total 1621067 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1621067 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1621067 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562696500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562696500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562697000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8273848500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8273848500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23836545000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23836545000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23836545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23836545500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94146954000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94146954000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469435000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469435000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616389000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616389000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469434500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469434500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616388500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616388500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098224 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098224 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037687 # mshr miss rate for WriteReq accesses @@ -509,14 +509,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074870 system.cpu.dcache.demand_mshr_miss_rate::total 0.074870 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074870 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843616 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843616 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843999 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26283.123727 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26283.123727 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -672,21 +672,21 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 12922 system.cpu.l2cache.overall_mshr_misses::cpu.data 141498 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 154425 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144074500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661603500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144100000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661629500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6194660000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677130500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6194660000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles @@ -710,21 +710,21 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.785637 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40516.325519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40365.103850 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |