diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref')
8 files changed, 3183 insertions, 3219 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 98f92d27e..b9451bcf6 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.870336 # Number of seconds simulated -sim_ticks 1870335522500 # Number of ticks simulated -final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.870325 # Number of seconds simulated +sim_ticks 1870325497500 # Number of ticks simulated +final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3051606 # Simulator instruction rate (inst/s) -host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90374561583 # Simulator tick rate (ticks/s) -host_mem_usage 305448 # Number of bytes of host memory used -host_seconds 20.70 # Real time elapsed on the host -sim_insts 63154034 # Number of instructions simulated -sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory +host_inst_rate 2529303 # Simulator instruction rate (inst/s) +host_op_rate 2529302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74909435310 # Simulator tick rate (ticks/s) +host_mem_usage 298360 # Number of bytes of host memory used +host_seconds 24.97 # Real time elapsed on the host +sim_insts 63151114 # Number of instructions simulated +sim_ops 63151114 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66666560 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory -system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory -system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 111168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 681792 # Number of bytes read from this memory +system.physmem.bytes_read::total 70870016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 760896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 111168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7852480 # Number of bytes written to this memory +system.physmem.bytes_written::total 7852480 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1041665 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1000626 # number of replacements -system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use -system.l2c.total_refs 2464737 # Total number of references to valid blocks. -system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.312639 # Average number of references to valid blocks. +system.physmem.num_reads::cpu1.inst 1737 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10653 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1107344 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122695 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122695 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35644362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1416652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 364531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37891809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4198456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4198456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4198456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35644362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1416652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 1000406 # number of replacements +system.l2c.tagsinuse 65381.817479 # Cycle average of tags in use +system.l2c.total_refs 2465974 # Total number of references to valid blocks. +system.l2c.sampled_refs 1065550 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.314273 # Average number of references to valid blocks. system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 56158.126687 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4894.240577 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4135.004263 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 174.436812 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 20.009142 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.856905 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.063095 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002662 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits -system.l2c.Writeback_hits::total 816653 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits +system.l2c.occ_percent::total 0.997647 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 872724 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 763058 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 102911 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 36889 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1775582 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 816811 # number of Writeback hits +system.l2c.Writeback_hits::total 816811 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 138 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 175 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 23 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23947 # 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number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816811 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816811 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2579 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 612 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3191 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 112 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 193 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281716 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 24162 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305878 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 884613 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971544 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 104648 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61969 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3022774 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 884613 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971544 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 104648 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 61969 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3022774 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346467 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.827160 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.919643 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.880829 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.409214 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528546 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352808 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528546 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352808 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,34 +173,34 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81316 # number of writebacks -system.l2c.writebacks::total 81316 # number of writebacks +system.l2c.writebacks::writebacks 81175 # number of writebacks +system.l2c.writebacks::total 81175 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41695 # number of replacements -system.iocache.tagsinuse 0.435437 # Cycle average of tags in use +system.iocache.replacements 41694 # number of replacements +system.iocache.tagsinuse 0.435353 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.027215 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.warmup_cycle 1685787105067 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.435353 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.027210 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.027210 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -236,22 +236,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9154530 # DTB read hits +system.cpu0.dtb.read_hits 9148429 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.write_hits 5936899 # DTB write hits +system.cpu0.dtb.write_hits 5932048 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses system.cpu0.dtb.write_acv 99 # DTB write access violations system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.data_hits 15091429 # DTB hits +system.cpu0.dtb.data_hits 15080477 # DTB hits system.cpu0.dtb.data_misses 7805 # DTB misses system.cpu0.dtb.data_acv 251 # DTB access violations system.cpu0.dtb.data_accesses 698037 # DTB accesses -system.cpu0.itb.fetch_hits 3855556 # ITB hits +system.cpu0.itb.fetch_hits 3854196 # ITB hits system.cpu0.itb.fetch_misses 3485 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3859041 # ITB accesses +system.cpu0.itb.fetch_accesses 3857681 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -264,55 +264,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.numCycles 3740650883 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57222076 # Number of instructions committed -system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses -system.cpu0.num_func_calls 1399585 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls -system.cpu0.num_int_insts 53249924 # number of integer instructions -system.cpu0.num_fp_insts 299810 # number of float instructions -system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written -system.cpu0.num_mem_refs 15135515 # number of memory refs -system.cpu0.num_load_insts 9184477 # Number of load instructions -system.cpu0.num_store_insts 5951038 # Number of store instructions -system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles -system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles +system.cpu0.committedInsts 57184467 # Number of instructions committed +system.cpu0.committedOps 57184467 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 53214865 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 299670 # Number of float alu accesses +system.cpu0.num_func_calls 1398025 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6803964 # number of instructions that are conditional controls +system.cpu0.num_int_insts 53214865 # number of integer instructions +system.cpu0.num_fp_insts 299670 # number of float instructions +system.cpu0.num_int_register_reads 73271755 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39802131 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 147658 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 150767 # number of times the floating registers were written +system.cpu0.num_mem_refs 15124548 # number of memory refs +system.cpu0.num_load_insts 9178366 # Number of load instructions +system.cpu0.num_store_insts 5946182 # Number of store instructions +system.cpu0.num_idle_cycles 3683454679.572560 # Number of idle cycles +system.cpu0.num_busy_cycles 57196203.427440 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6280 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 196965 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 70940 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 101631 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 174730 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69573 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 69565 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 141297 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1852985718000 99.07% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::31 17236468500 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1870325290000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980730 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684486 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808659 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -345,37 +345,37 @@ system.cpu0.kern.syscall::144 2 0.88% 99.12% # nu system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 226 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 111 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3760 2.05% 2.12% # number of callpals executed system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 167897 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal::rdps 6134 3.35% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183291 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches +system.cpu0.kern.callpal::total 183136 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7089 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1157 -system.cpu0.kern.mode_good::user 1158 +system.cpu0.kern.mode_good::kernel 1155 +system.cpu0.kern.mode_good::user 1156 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162928 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.280291 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1869368290000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3763 # number of times the context was actually changed +system.cpu0.kern.swap_context 3761 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -407,39 +407,39 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 884404 # number of replacements -system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use -system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. +system.cpu0.icache.replacements 883989 # number of replacements +system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use +system.cpu0.icache.total_refs 56307893 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 884501 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 63.660632 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.244895 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits -system.cpu0.icache.overall_hits::total 56345132 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses -system.cpu0.icache.overall_misses::total 885000 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 56307893 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 56307893 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56307893 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 56307893 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56307893 # number of overall hits +system.cpu0.icache.overall_hits::total 56307893 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 884630 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 884630 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 884630 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 884630 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 884630 # number of overall misses +system.cpu0.icache.overall_misses::total 884630 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57192523 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 57192523 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57192523 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 57192523 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57192523 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 57192523 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015468 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015468 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015468 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015468 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015468 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015468 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,63 +449,63 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978686 # number of replacements -system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1978242 # number of replacements +system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13113201 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1978754 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 6.626999 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses +system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7292600 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7292600 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12750387 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12750387 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12750387 # number of overall hits +system.cpu0.dcache.overall_hits::total 12750387 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683130 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683130 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1968928 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1968928 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1968928 # number of overall misses +system.cpu0.dcache.overall_misses::total 1968928 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5743585 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188129 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 188129 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187169 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187169 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14719315 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187520 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187520 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085856 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003879 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003879 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133765 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133765 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133765 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133765 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -514,29 +514,29 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks -system.cpu0.dcache.writebacks::total 775641 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775494 # number of writebacks +system.cpu0.dcache.writebacks::total 775494 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1163439 # DTB read hits +system.cpu1.dtb.read_hits 1169160 # DTB read hits system.cpu1.dtb.read_misses 3277 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 220342 # DTB read accesses -system.cpu1.dtb.write_hits 751446 # DTB write hits +system.cpu1.dtb.write_hits 755883 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_accesses 103280 # DTB write accesses -system.cpu1.dtb.data_hits 1914885 # DTB hits +system.cpu1.dtb.data_hits 1925043 # DTB hits system.cpu1.dtb.data_misses 3692 # DTB misses system.cpu1.dtb.data_acv 116 # DTB access violations system.cpu1.dtb.data_accesses 323622 # DTB accesses -system.cpu1.itb.fetch_hits 1468399 # ITB hits +system.cpu1.itb.fetch_hits 1469677 # ITB hits system.cpu1.itb.fetch_misses 1539 # ITB misses system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1469938 # ITB accesses +system.cpu1.itb.fetch_accesses 1471216 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -549,51 +549,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.numCycles 3740237218 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5931958 # Number of instructions committed -system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses -system.cpu1.num_func_calls 182742 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls -system.cpu1.num_int_insts 5550578 # number of integer instructions -system.cpu1.num_fp_insts 28590 # number of float instructions -system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written -system.cpu1.num_mem_refs 1926244 # number of memory refs -system.cpu1.num_load_insts 1170888 # Number of load instructions -system.cpu1.num_store_insts 755356 # Number of store instructions -system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles -system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles -system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles +system.cpu1.committedInsts 5966647 # Number of instructions committed +system.cpu1.committedOps 5966647 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 5582916 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 28730 # Number of float alu accesses +system.cpu1.num_func_calls 184190 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 581489 # number of instructions that are conditional controls +system.cpu1.num_int_insts 5582916 # number of integer instructions +system.cpu1.num_fp_insts 28730 # number of float instructions +system.cpu1.num_int_register_reads 7700123 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4186358 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 17955 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 17751 # number of times the floating registers were written +system.cpu1.num_mem_refs 1936419 # number of memory refs +system.cpu1.num_load_insts 1176619 # Number of load instructions +system.cpu1.num_store_insts 759800 # Number of store instructions +system.cpu1.num_idle_cycles 3734265828.606121 # Number of idle cycles +system.cpu1.num_busy_cycles 5971389.393879 # Number of busy cycles +system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10388 33.53% 33.53% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1907 6.15% 39.68% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 111 0.36% 40.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18579 59.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30985 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22663 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1859112376500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks::30 14176500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 10910041500 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1870118595500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999037 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.552613 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.731418 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed @@ -616,67 +616,67 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal::swpctx 472 1.46% 1.50% # number of callpals executed system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed -system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed -system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26358 81.69% 83.25% # number of callpals executed +system.cpu1.kern.callpal::rdps 2589 8.02% 91.28% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.28% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 91.29% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.01% 91.30% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.31% # number of callpals executed +system.cpu1.kern.callpal::rti 2608 8.08% 99.39% # number of callpals executed system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 32131 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches +system.cpu1.kern.callpal::total 32267 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1034 # number of protection mode switches system.cpu1.kern.mode_switch::user 580 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 612 +system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 613 system.cpu1.kern.mode_good::user 580 -system.cpu1.kern.mode_good::idle 32 -system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 33 +system.cpu1.kern.mode_switch_good::kernel 0.592843 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.016113 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.334790 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1393260500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.icache.replacements 103091 # number of replacements -system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use -system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits -system.cpu1.icache.overall_hits::total 5832136 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses -system.cpu1.icache.overall_misses::total 103630 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses +system.cpu1.kern.mode_ticks::idle 1867980072500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 473 # number of times the context was actually changed +system.cpu1.icache.replacements 104103 # number of replacements +system.cpu1.icache.tagsinuse 427.138444 # Cycle average of tags in use +system.cpu1.icache.total_refs 5865807 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 104615 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 56.070420 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868930362000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 427.138444 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.834255 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.834255 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5865807 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5865807 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5865807 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5865807 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5865807 # number of overall hits +system.cpu1.icache.overall_hits::total 5865807 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 104648 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 104648 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 104648 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 104648 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 104648 # number of overall misses +system.cpu1.icache.overall_misses::total 104648 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5970455 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5970455 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5970455 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5970455 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5970455 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5970455 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017528 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017528 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017528 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017528 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017528 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -686,63 +686,63 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62044 # number of replacements -system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.823365 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses -system.cpu1.dcache.overall_misses::total 67292 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses +system.cpu1.dcache.replacements 62444 # number of replacements +system.cpu1.dcache.tagsinuse 421.660465 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1845254 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62784 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 29.390514 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851113732500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 421.660465 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.823556 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.823556 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1114890 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1114890 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 711494 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 711494 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15278 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15278 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15743 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15743 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1826384 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1826384 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1826384 # number of overall hits +system.cpu1.dcache.overall_hits::total 1826384 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41651 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41651 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 26091 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 26091 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1291 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1291 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 751 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 751 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 67742 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67742 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67742 # number of overall misses +system.cpu1.dcache.overall_misses::total 67742 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1156541 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1156541 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 737585 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 737585 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 16569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16494 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 16494 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1894126 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1894126 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1894126 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1894126 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036013 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036013 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035374 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035374 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077917 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.077917 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.045532 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.045532 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035764 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035764 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035764 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035764 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,8 +751,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks -system.cpu1.dcache.writebacks::total 41012 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41317 # number of writebacks +system.cpu1.dcache.writebacks::total 41317 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index a50f49017..cf5c30619 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,132 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332258000 # Number of ticks simulated -final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.829331 # Number of seconds simulated +sim_ticks 1829330593000 # Number of ticks simulated +final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2962809 # Simulator instruction rate (inst/s) -host_op_rate 2962806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90274916526 # Simulator tick rate (ticks/s) -host_mem_usage 302384 # Number of bytes of host memory used -host_seconds 20.26 # Real time elapsed on the host -sim_insts 60038305 # Number of instructions simulated -sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory +host_inst_rate 2569577 # Simulator instruction rate (inst/s) +host_op_rate 2569575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78294086451 # Simulator tick rate (ticks/s) +host_mem_usage 295292 # Number of bytes of host memory used +host_seconds 23.37 # Real time elapsed on the host +sim_insts 60037737 # Number of instructions simulated +sim_ops 60037737 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 70349440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 992301 # number of replacements -system.cpu.l2cache.tagsinuse 65424.374305 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2433239 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1057464 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.301014 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks -system.cpu.l2cache.writebacks::total 74291 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.num_reads::total 1099210 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115799 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115799 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1449868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38456384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 41686 # number of replacements -system.iocache.tagsinuse 1.225570 # Cycle average of tags in use +system.iocache.tagsinuse 1.225558 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.076598 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1685780599067 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.225558 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.076597 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.076597 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -178,22 +98,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710427 # DTB read hits +system.cpu.dtb.read_hits 9710417 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352498 # DTB write hits +system.cpu.dtb.write_hits 6352487 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062925 # DTB hits +system.cpu.dtb.data_hits 16062904 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974648 # ITB hits +system.cpu.itb.fetch_hits 4974615 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979654 # ITB accesses +system.cpu.itb.fetch_accesses 4979621 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -206,51 +126,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.numCycles 3658661078 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038305 # Number of instructions committed -system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses +system.cpu.committedInsts 60037737 # Number of instructions committed +system.cpu.committedOps 60037737 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55912968 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913521 # number of integer instructions +system.cpu.num_func_calls 1484174 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7110641 # number of instructions that are conditional controls +system.cpu.num_int_insts 55912968 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written +system.cpu.num_int_register_reads 76953007 # number of times the integer registers were read +system.cpu.num_int_register_writes 41739788 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115709 # number of memory refs -system.cpu.num_load_insts 9747513 # Number of load instructions -system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles -system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles -system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983585 # Percentage of idle cycles +system.cpu.num_mem_refs 16115688 # number of memory refs +system.cpu.num_load_insts 9747503 # Number of load instructions +system.cpu.num_store_insts 6368185 # Number of store instructions +system.cpu.num_idle_cycles 3598606247.544791 # Number of idle cycles +system.cpu.num_busy_cycles 60054830.455209 # Number of busy cycles +system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983586 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211316 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182559 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811925911500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816366 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -289,7 +209,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175246 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -298,20 +218,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192180 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 192177 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches +system.cpu.kern.mode_switch::user 1735 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1735 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320444 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081506 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.389735 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26832734500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465059000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801032591000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -344,33 +264,33 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 919594 # number of replacements -system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use -system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. +system.cpu.icache.replacements 919577 # number of replacements +system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use +system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 920089 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 64.264839 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.215229 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits -system.cpu.icache.overall_hits::total 59129922 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses -system.cpu.icache.overall_misses::total 920221 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59129371 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129371 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59129371 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129371 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59129371 # number of overall hits +system.cpu.icache.overall_hits::total 59129371 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920204 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920204 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920204 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920204 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920204 # number of overall misses +system.cpu.icache.overall_misses::total 920204 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60049575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60049575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60049575 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60049575 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60049575 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60049575 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -386,55 +306,55 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042702 # number of replacements +system.cpu.dcache.replacements 2042708 # number of replacements system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038431 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043214 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870759 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14038404 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043220 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870726 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits -system.cpu.dcache.overall_hits::total 13655992 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7807768 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807768 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655967 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655967 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655967 # number of overall hits +system.cpu.dcache.overall_hits::total 13655967 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses -system.cpu.dcache.overall_misses::total 2026069 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses +system.cpu.dcache.overall_misses::total 2026075 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses @@ -450,5 +370,85 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 992297 # number of replacements +system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998466 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905248 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998466 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905248 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117115 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117115 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13404 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044755 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058159 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13404 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659058 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963407 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963407 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks +system.cpu.l2cache.writebacks::total 74287 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 181c5df24..ba361e6db 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962058 # Number of seconds simulated -sim_ticks 1962057812000 # Number of ticks simulated -final_tick 1962057812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.955746 # Number of seconds simulated +sim_ticks 1955746240500 # Number of ticks simulated +final_tick 1955746240500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1235183 # Simulator instruction rate (inst/s) -host_op_rate 1235183 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40819911602 # Simulator tick rate (ticks/s) -host_mem_usage 297060 # Number of bytes of host memory used -host_seconds 48.07 # Real time elapsed on the host -sim_insts 59370518 # Number of instructions simulated -sim_ops 59370518 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 834432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24593280 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 29312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 572992 # Number of bytes read from this memory -system.physmem.bytes_read::total 28680832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 834432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 29312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7715456 # Number of bytes written to this memory -system.physmem.bytes_written::total 7715456 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384270 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 458 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8953 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448138 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120554 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120554 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12534432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14939 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 292036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14617730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3932329 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3932329 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3932329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12534432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 292036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18550059 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 341238 # number of replacements -system.l2c.tagsinuse 65290.171288 # Cycle average of tags in use -system.l2c.total_refs 2492514 # Total number of references to valid blocks. -system.l2c.sampled_refs 406253 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.135374 # Average number of references to valid blocks. -system.l2c.warmup_cycle 7854344000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55481.148199 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4824.640956 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4855.323185 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 116.032373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 13.026576 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.846575 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073618 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.074086 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001771 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000199 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996249 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 902430 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 773977 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 31919 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1795074 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820361 # number of Writeback hits -system.l2c.Writeback_hits::total 820361 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 161 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 42 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 172410 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 12341 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 184751 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 902430 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 946387 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 86748 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 44260 # number of demand (read+write) hits -system.l2c.demand_hits::total 1979825 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 902430 # number of overall hits -system.l2c.overall_hits::cpu0.data 946387 # number of overall hits -system.l2c.overall_hits::cpu1.inst 86748 # number of overall hits -system.l2c.overall_hits::cpu1.data 44260 # number of overall hits -system.l2c.overall_hits::total 1979825 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13038 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271462 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 469 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 326 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285295 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2435 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 490 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 34 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 107 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113176 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8669 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121845 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13038 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 384638 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 469 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8995 # number of demand (read+write) misses -system.l2c.demand_misses::total 407140 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13038 # number of overall misses -system.l2c.overall_misses::cpu0.data 384638 # number of overall misses -system.l2c.overall_misses::cpu1.inst 469 # number of overall misses -system.l2c.overall_misses::cpu1.data 8995 # number of overall misses -system.l2c.overall_misses::total 407140 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 678189500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14120883000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 24328000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 17368000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14840768500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1412000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1560000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2972000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 156000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 364000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5885512000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 450808000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6336320000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 678189500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20006395000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 24328000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 468176000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21177088500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 678189500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20006395000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 24328000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 468176000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21177088500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 915468 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1045439 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 87217 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 32245 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2080369 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 820361 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 820361 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2596 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 547 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3143 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 55 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 94 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 149 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 285586 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 21010 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306596 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 915468 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1331025 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 87217 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 53255 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2386965 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 915468 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1331025 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 87217 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 53255 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2386965 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014242 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.259663 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005377 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.010110 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.137137 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937982 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.895795 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.930640 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.618182 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776596 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.718121 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.396294 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.412613 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.397412 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014242 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.288979 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005377 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.168904 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.170568 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014242 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.288979 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005377 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.168904 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.170568 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52016.375211 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.899374 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51872.068230 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 53276.073620 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52019.027673 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 579.876797 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3183.673469 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1016.068376 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4588.235294 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2849.315068 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3401.869159 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52003.180886 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52002.307071 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52003.118716 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52016.375211 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52013.568602 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51872.068230 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52048.471373 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52014.266591 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52016.375211 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52013.568602 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51872.068230 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52048.471373 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52014.266591 # average overall miss latency +host_inst_rate 1240365 # Simulator instruction rate (inst/s) +host_op_rate 1240364 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39831169965 # Simulator tick rate (ticks/s) +host_mem_usage 291792 # Number of bytes of host memory used +host_seconds 49.10 # Real time elapsed on the host +sim_insts 60902973 # Number of instructions simulated +sim_ops 60902973 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 830080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24726528 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 438464 # Number of bytes read from this memory +system.physmem.bytes_read::total 28681152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 830080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7699072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7699072 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12970 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386352 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6851 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448143 # 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number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses +system.iocache.demand_misses::total 41728 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses +system.iocache.overall_misses::total 41728 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11453563806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11453563806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11474577804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11474577804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11474577804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11474577804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -385,40 +385,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119325.831461 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275512.774499 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275512.774499 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 274846.556530 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 274846.556530 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199371000 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275644.103918 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275644.103918 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274985.089245 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274985.089245 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199825 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24657 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24712 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8085.776858 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.086152 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11983000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11983000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287247000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9287247000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9299230000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9299230000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9299230000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9299230000 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11861998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9292859806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9292859806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9304721804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9304721804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9304721804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9304721804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -427,14 +427,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223509.024836 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223509.024836 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67397.715909 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67397.715909 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223644.103918 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223644.103918 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8658368 # DTB read hits -system.cpu0.dtb.read_misses 7687 # DTB read misses -system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.write_hits 6036843 # DTB write hits -system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.data_hits 14695211 # DTB hits -system.cpu0.dtb.data_misses 8485 # DTB misses -system.cpu0.dtb.data_acv 289 # DTB access violations -system.cpu0.dtb.data_accesses 719860 # DTB accesses -system.cpu0.itb.fetch_hits 3948323 # ITB hits -system.cpu0.itb.fetch_misses 3841 # ITB misses -system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_accesses 3952164 # ITB accesses +system.cpu0.dtb.read_hits 7486542 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_acv 210 # DTB read access violations +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 5063820 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.write_acv 134 # DTB write access violations +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.data_hits 12550362 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.data_acv 344 # DTB access violations +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3500956 # ITB hits +system.cpu0.itb.fetch_misses 3871 # ITB misses +system.cpu0.itb.fetch_acv 184 # ITB acv +system.cpu0.itb.fetch_accesses 3504827 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,118 +480,117 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3924115624 # number of cpu cycles simulated +system.cpu0.numCycles 3910167080 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54116505 # Number of instructions committed -system.cpu0.committedOps 54116505 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50087098 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 302903 # Number of float alu accesses -system.cpu0.num_func_calls 1426970 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6243728 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50087098 # number of integer instructions -system.cpu0.num_fp_insts 302903 # number of float instructions -system.cpu0.num_int_register_reads 68610814 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37122288 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 149298 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 152355 # number of times the floating registers were written -system.cpu0.num_mem_refs 14741096 # number of memory refs -system.cpu0.num_load_insts 8689646 # Number of load instructions -system.cpu0.num_store_insts 6051450 # Number of store instructions -system.cpu0.num_idle_cycles 3676817171.998126 # Number of idle cycles -system.cpu0.num_busy_cycles 247298452.001874 # Number of busy cycles -system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles +system.cpu0.committedInsts 47719039 # Number of instructions committed +system.cpu0.committedOps 47719039 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44257119 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210954 # Number of float alu accesses +system.cpu0.num_func_calls 1200899 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5607083 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44257119 # number of integer instructions +system.cpu0.num_fp_insts 210954 # number of float instructions +system.cpu0.num_int_register_reads 60839484 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32982631 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102466 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104326 # number of times the floating registers were written +system.cpu0.num_mem_refs 12590587 # number of memory refs +system.cpu0.num_load_insts 7513713 # Number of load instructions +system.cpu0.num_store_insts 5076874 # Number of store instructions +system.cpu0.num_idle_cycles 3701181001.496715 # Number of idle cycles +system.cpu0.num_busy_cycles 208986078.503285 # Number of busy cycles +system.cpu0.not_idle_fraction 0.053447 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.946553 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202757 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72604 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104050 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178770 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71235 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71229 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144580 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900688314000 96.87% 96.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 102511500 0.01% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 795126500 0.04% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60465450000 3.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962056974000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6789 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164868 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56806 40.18% 40.18% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1972 1.39% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 420 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82040 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141369 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56268 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1972 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 420 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55848 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114639 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1899887304000 97.18% 97.18% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92906000 0.00% 97.18% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 760170500 0.04% 97.22% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 309335500 0.02% 97.24% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 54033794000 2.76% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1955083510000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990529 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684565 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808749 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed -system.cpu0.kern.syscall::6 30 13.39% 25.89% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 26.34% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.45% 26.79% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.46% 31.25% # number of syscalls executed -system.cpu0.kern.syscall::19 6 2.68% 33.93% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.79% 35.71% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.89% 36.61% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.79% 38.39% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.57% 41.96% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.89% 42.86% # number of syscalls executed -system.cpu0.kern.syscall::45 39 17.41% 60.27% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.79% 62.05% # number of syscalls executed -system.cpu0.kern.syscall::48 7 3.12% 65.18% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.02% 69.20% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 69.64% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.23% 71.88% # number of syscalls executed -system.cpu0.kern.syscall::71 32 14.29% 86.16% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.34% 87.50% # number of syscalls executed -system.cpu0.kern.syscall::74 9 4.02% 91.52% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 91.96% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.89% 92.86% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.12% 95.98% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.89% 96.87% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.89% 97.77% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.89% 98.66% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 224 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.680741 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810920 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3872 2.06% 2.11% # number of callpals executed -system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 171948 91.52% 93.66% # number of callpals executed -system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed -system.cpu0.kern.callpal::rti 4705 2.50% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 187881 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7233 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1235 # number of protection mode switches +system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3070 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.43% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134512 89.86% 92.29% # number of callpals executed +system.cpu0.kern.callpal::rdps 6676 4.46% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149688 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6889 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1285 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1234 -system.cpu0.kern.mode_good::user 1235 +system.cpu0.kern.mode_good::kernel 1285 +system.cpu0.kern.mode_good::user 1285 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.170607 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186529 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.291568 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958395542000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3661425000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314412 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1951516113500 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3347061000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3873 # number of times the context was actually changed +system.cpu0.kern.swap_context 3071 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -623,51 +622,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 914851 # number of replacements -system.cpu0.icache.tagsinuse 508.781994 # Cycle average of tags in use -system.cpu0.icache.total_refs 53209789 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915362 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.129777 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.781994 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53209789 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53209789 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53209789 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53209789 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53209789 # number of overall hits -system.cpu0.icache.overall_hits::total 53209789 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915491 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915491 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915491 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915491 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915491 # number of overall misses -system.cpu0.icache.overall_misses::total 915491 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13646549000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13646549000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13646549000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13646549000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13646549000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13646549000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54125280 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54125280 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54125280 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54125280 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54125280 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54125280 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016914 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016914 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016914 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016914 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016914 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016914 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.262323 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.262323 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14906.262323 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14906.262323 # average overall miss latency +system.cpu0.icache.replacements 698187 # number of replacements +system.cpu0.icache.tagsinuse 508.830635 # Cycle average of tags in use +system.cpu0.icache.total_refs 47028847 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 698699 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.309166 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 35739052000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.830635 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993810 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993810 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47028847 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47028847 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47028847 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47028847 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47028847 # number of overall hits +system.cpu0.icache.overall_hits::total 47028847 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses +system.cpu0.icache.overall_misses::total 698792 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9694162500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9694162500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9694162500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9694162500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9694162500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9694162500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47727639 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47727639 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47727639 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47727639 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47727639 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47727639 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014641 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014641 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014641 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014641 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014641 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014641 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13872.743964 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13872.743964 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13872.743964 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13872.743964 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,112 +675,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915491 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915491 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915491 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915491 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915491 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915491 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10899382500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10899382500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10899382500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10899382500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10899382500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10899382500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016914 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016914 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016914 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.504806 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8296578500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8296578500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8296578500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8296578500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8296578500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8296578500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014641 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11872.743964 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1337819 # number of replacements -system.cpu0.dcache.tagsinuse 506.532892 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13370103 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338331 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.990132 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 101834000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.532892 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989322 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989322 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7444463 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7444463 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5554933 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5554933 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175817 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 175817 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191182 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191182 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12999396 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12999396 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12999396 # number of overall hits -system.cpu0.dcache.overall_hits::total 12999396 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1037635 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1037635 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 289296 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 289296 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16772 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16772 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 445 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 445 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1326931 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326931 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326931 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326931 # 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number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 35076865000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482098 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8482098 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5844229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192589 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 192589 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191627 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191627 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14326327 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14326327 # 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miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092622 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092622 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092622 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.495926 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.495926 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30982.896411 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30982.896411 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14228.058669 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14228.058669 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10937.078652 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10937.078652 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26434.580999 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26434.580999 # average overall miss latency +system.cpu0.dcache.replacements 1180402 # number of replacements +system.cpu0.dcache.tagsinuse 505.183019 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11360683 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1180820 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.621012 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 99461000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.183019 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.986686 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.986686 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6406782 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6406782 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4655760 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4655760 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140286 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140286 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147915 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147915 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11062542 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11062542 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11062542 # number of overall hits +system.cpu0.dcache.overall_hits::total 11062542 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938249 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938249 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251643 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251643 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13638 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13638 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5458 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5458 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1189892 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1189892 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1189892 # number of overall misses +system.cpu0.dcache.overall_misses::total 1189892 # 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number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31723890000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7345031 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7345031 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4907403 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4907403 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153924 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 153924 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153373 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153373 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12252434 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12252434 # 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average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 679069 # number of writebacks +system.cpu0.dcache.writebacks::total 679069 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938249 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938249 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251643 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251643 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5458 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5458 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189892 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1189892 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189892 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1189892 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21646065000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21646065000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7698041000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7698041000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 120630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 120630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 56880500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56880500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29344106000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 29344106000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29344106000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 29344106000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465334500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465334500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2275733500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2275733500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3741068000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3741068000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127739 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127739 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051278 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051278 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088602 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088602 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035586 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035586 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097115 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097115 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23070.704046 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 23070.704046 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30591.119165 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30591.119165 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8845.138583 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8845.138583 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 10421.491389 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 10421.491389 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -857,22 +856,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1027530 # DTB read hits -system.cpu1.dtb.read_misses 2750 # DTB read misses -system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_accesses 205838 # DTB read accesses -system.cpu1.dtb.write_hits 663193 # DTB write hits -system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_accesses 97040 # DTB write accesses -system.cpu1.dtb.data_hits 1690723 # DTB hits -system.cpu1.dtb.data_misses 3106 # DTB misses -system.cpu1.dtb.data_acv 84 # DTB access violations -system.cpu1.dtb.data_accesses 302878 # DTB accesses -system.cpu1.itb.fetch_hits 1394871 # ITB hits -system.cpu1.itb.fetch_misses 1246 # ITB misses -system.cpu1.itb.fetch_acv 41 # ITB acv -system.cpu1.itb.fetch_accesses 1396117 # ITB accesses +system.cpu1.dtb.read_hits 2425080 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.write_hits 1761000 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.write_acv 29 # DTB write access violations +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.data_hits 4186080 # DTB hits +system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.data_acv 29 # DTB access violations +system.cpu1.dtb.data_accesses 344610 # DTB accesses +system.cpu1.itb.fetch_hits 1964871 # ITB hits +system.cpu1.itb.fetch_misses 1216 # ITB misses +system.cpu1.itb.fetch_acv 0 # ITB acv +system.cpu1.itb.fetch_accesses 1966087 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -885,150 +884,141 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923836552 # number of cpu cycles simulated +system.cpu1.numCycles 3911492481 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5254013 # Number of instructions committed -system.cpu1.committedOps 5254013 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4921025 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses -system.cpu1.num_func_calls 157600 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 506865 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4921025 # number of integer instructions -system.cpu1.num_fp_insts 25430 # number of float instructions -system.cpu1.num_int_register_reads 6827399 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3700117 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written -system.cpu1.num_mem_refs 1700348 # number of memory refs -system.cpu1.num_load_insts 1033584 # Number of load instructions -system.cpu1.num_store_insts 666764 # Number of store instructions -system.cpu1.num_idle_cycles 3903107404.303190 # Number of idle cycles -system.cpu1.num_busy_cycles 20729147.696810 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005283 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994717 # Percentage of idle cycles +system.cpu1.committedInsts 13183934 # Number of instructions committed +system.cpu1.committedOps 13183934 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12160396 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 172922 # Number of float alu accesses +system.cpu1.num_func_calls 412685 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1307407 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12160396 # number of integer instructions +system.cpu1.num_fp_insts 172922 # number of float instructions +system.cpu1.num_int_register_reads 16740645 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8924669 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90471 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92344 # number of times the floating registers were written +system.cpu1.num_mem_refs 4209624 # number of memory refs +system.cpu1.num_load_insts 2439377 # Number of load instructions +system.cpu1.num_store_insts 1770247 # Number of store instructions +system.cpu1.num_idle_cycles 3861803254.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49689226.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012703 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987297 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 35942 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17499 60.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28706 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1920766593500 97.90% 97.90% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 726074500 0.04% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 67017000 0.00% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 40358561000 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961918246000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78634 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26575 38.36% 38.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.84% 41.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 503 0.73% 41.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40225 58.07% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69270 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25736 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 503 0.94% 52.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25233 47.22% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53439 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909053778500 97.61% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705460500 0.04% 97.65% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 351339000 0.02% 97.67% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45634904500 2.33% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1955745482500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968429 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.516830 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.705184 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed -system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed -system.cpu1.kern.syscall::6 12 11.76% 25.49% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.90% 30.39% # number of syscalls executed -system.cpu1.kern.syscall::19 4 3.92% 34.31% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.96% 36.27% # number of syscalls executed -system.cpu1.kern.syscall::23 2 1.96% 38.24% # number of syscalls executed -system.cpu1.kern.syscall::24 2 1.96% 40.20% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.94% 43.14% # number of syscalls executed -system.cpu1.kern.syscall::45 15 14.71% 57.84% # number of syscalls executed -system.cpu1.kern.syscall::47 2 1.96% 59.80% # number of syscalls executed -system.cpu1.kern.syscall::48 3 2.94% 62.75% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.98% 63.73% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.96% 65.69% # number of syscalls executed -system.cpu1.kern.syscall::71 22 21.57% 87.25% # number of syscalls executed -system.cpu1.kern.syscall::74 7 6.86% 94.12% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.98% 95.10% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.96% 97.06% # number of syscalls executed -system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 102 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.627296 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771460 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed -system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24054 81.82% 83.15% # number of callpals executed -system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.52% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 90.53% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 90.53% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal::rti 2587 8.80% 99.34% # number of callpals executed -system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed -system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 420 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1995 2.79% 3.38% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63027 88.05% 91.44% # number of callpals executed +system.cpu1.kern.callpal::rdps 2168 3.03% 94.47% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.48% # number of callpals executed +system.cpu1.kern.callpal::rti 3772 5.27% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29399 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches -system.cpu1.kern.mode_switch::user 515 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 531 -system.cpu1.kern.mode_good::user 515 -system.cpu1.kern.mode_good::idle 16 -system.cpu1.kern.mode_switch_good::kernel 0.604096 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71584 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2065 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 891 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 427 +system.cpu1.kern.mode_switch_good::kernel 0.431477 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.007711 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.306140 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4075179000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1593973000 0.08% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1955466537000 99.71% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 366 # number of times the context was actually changed -system.cpu1.icache.replacements 86678 # number of replacements -system.cpu1.icache.tagsinuse 419.761864 # Cycle average of tags in use -system.cpu1.icache.total_refs 5169985 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 87190 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.295619 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1958463060000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.761864 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819847 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819847 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5169985 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5169985 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5169985 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5169985 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5169985 # number of overall hits -system.cpu1.icache.overall_hits::total 5169985 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 87218 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87218 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 87218 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87218 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 87218 # number of overall misses -system.cpu1.icache.overall_misses::total 87218 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1315004000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1315004000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1315004000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1315004000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1315004000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1315004000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5257203 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5257203 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5257203 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5257203 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5257203 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5257203 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016590 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016590 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016590 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016590 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016590 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15077.208833 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15077.208833 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15077.208833 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15077.208833 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.148573 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329817 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17893399500 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1709951500 0.09% 1.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1936142128000 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1996 # number of times the context was actually changed +system.cpu1.icache.replacements 316204 # number of replacements +system.cpu1.icache.tagsinuse 447.456269 # Cycle average of tags in use +system.cpu1.icache.total_refs 12870545 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 316716 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.637495 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1953875803000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 447.456269 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.873938 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.873938 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12870545 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12870545 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12870545 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12870545 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12870545 # number of overall hits +system.cpu1.icache.overall_hits::total 12870545 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316752 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316752 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316752 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316752 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316752 # number of overall misses +system.cpu1.icache.overall_misses::total 316752 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4179857000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4179857000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4179857000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4179857000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4179857000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4179857000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13187297 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13187297 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13187297 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13187297 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13187297 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13187297 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024019 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024019 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024019 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024019 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024019 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024019 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13195.992448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13195.992448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13195.992448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13195.992448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1037,112 +1027,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87218 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 87218 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 87218 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 87218 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 87218 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 87218 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1053316500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1053316500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1053316500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1053316500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1053316500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1053316500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016590 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12076.824738 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316752 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316752 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316752 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316752 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316752 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316752 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3546353000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3546353000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3546353000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3546353000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3546353000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3546353000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024019 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024019 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024019 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11195.992448 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 53530 # number of replacements -system.cpu1.dcache.tagsinuse 416.811223 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1627239 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 53938 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.168694 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1941569871000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 416.811223 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.814084 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.814084 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 982758 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 982758 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 626472 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 626472 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11310 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 11310 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11707 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 11707 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1609230 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1609230 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1609230 # number of overall hits -system.cpu1.dcache.overall_hits::total 1609230 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 35626 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 35626 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 22614 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 22614 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1003 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1003 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 544 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 544 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 58240 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 58240 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 58240 # number of overall misses -system.cpu1.dcache.overall_misses::total 58240 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484494000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 484494000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 694414000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 694414000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 12192000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 12192000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7087000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 7087000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1178908000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 1178908000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 1178908000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 1178908000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1018384 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1018384 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 649086 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 649086 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12313 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 12313 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12251 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 12251 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1667470 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1667470 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1667470 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1667470 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034983 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.034983 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034840 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034840 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081459 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081459 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044405 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044405 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034927 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034927 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034927 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034927 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13599.449840 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13599.449840 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30707.260989 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30707.260989 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12155.533400 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12155.533400 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13027.573529 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13027.573529 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20242.239011 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20242.239011 # average overall miss latency +system.cpu1.dcache.replacements 166318 # number of replacements +system.cpu1.dcache.tagsinuse 487.121043 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4017452 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 166830 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.081113 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 63885131000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.121043 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951408 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951408 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2260833 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2260833 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1643465 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1643465 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48243 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48243 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50839 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50839 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3904298 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3904298 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3904298 # number of overall hits +system.cpu1.dcache.overall_hits::total 3904298 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118301 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118301 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62725 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62725 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8915 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8915 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5846 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5846 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 181026 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 181026 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 181026 # number of overall misses +system.cpu1.dcache.overall_misses::total 181026 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440550500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1440550500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1113565500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1113565500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81445500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 81445500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 69062000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 69062000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2554116000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2554116000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2554116000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2554116000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2379134 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2379134 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1706190 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1706190 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56685 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56685 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4085324 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4085324 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4085324 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4085324 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049724 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049724 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036763 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036763 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155971 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155971 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103131 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103131 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044311 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044311 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044311 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044311 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12176.993432 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12176.993432 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17753.136708 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17753.136708 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.782389 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.782389 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11813.547725 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11813.547725 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14109.111398 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14109.111398 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1151,62 +1141,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 35195 # number of writebacks -system.cpu1.dcache.writebacks::total 35195 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35626 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 35626 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22614 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 22614 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1003 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1003 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 544 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 544 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 58240 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 58240 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 58240 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 58240 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377607005 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377607005 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626568004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626568004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9183000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9183000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5455000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5455000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004175009 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1004175009 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004175009 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1004175009 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20565000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20565000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534647000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534647000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555212000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555212000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034983 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034983 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034840 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034840 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044405 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044405 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034927 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034927 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10599.197356 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10599.197356 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27707.084284 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27707.084284 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9155.533400 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9155.533400 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10027.573529 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10027.573529 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 114265 # number of writebacks +system.cpu1.dcache.writebacks::total 114265 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118301 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118301 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62725 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62725 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8915 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8915 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5846 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5846 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 181026 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 181026 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 181026 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 181026 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203948500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203948500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 988115500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 988115500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63615500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63615500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57370000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57370000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2192064000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2192064000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2192064000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2192064000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713392500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713392500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732780000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732780000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049724 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049724 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036763 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036763 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155971 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155971 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103131 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103131 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044311 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044311 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10176.993432 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10176.993432 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15753.136708 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15753.136708 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.782389 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.782389 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9813.547725 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9813.547725 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 23658f386..369a1e336 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.914421 # Nu sim_ticks 1914420945000 # Number of ticks simulated final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1284205 # Simulator instruction rate (inst/s) -host_op_rate 1284205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43773036105 # Simulator tick rate (ticks/s) -host_mem_usage 295308 # Number of bytes of host memory used -host_seconds 43.74 # Real time elapsed on the host +host_inst_rate 1299276 # Simulator instruction rate (inst/s) +host_op_rate 1299275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44286723014 # Simulator tick rate (ticks/s) +host_mem_usage 288696 # Number of bytes of host memory used +host_seconds 43.23 # Real time elapsed on the host sim_insts 56164879 # Number of instructions simulated sim_ops 56164879 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory @@ -87,11 +87,11 @@ system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199052000 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 199052 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8086.942391 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.086942 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -105,14 +105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283200000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9283200000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9294876000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9294876000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9294876000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9294876000 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283350806 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9283350806 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9295027804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9295027804 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9295027804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9295027804 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -121,14 +121,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223411.628802 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223411.628802 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223415.258134 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223415.258134 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -649,14 +649,14 @@ system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000 system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16091377000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16091377500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16091377000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16091377500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles @@ -681,14 +681,14 @@ system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.350739 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.350739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.355018 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.355018 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 0ffcacbe4..0a013f420 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,75 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.207291 # Number of seconds simulated -sim_ticks 1207290627000 # Number of ticks simulated -final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.203695 # Number of seconds simulated +sim_ticks 1203694548000 # Number of ticks simulated +final_tick 1203694548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 648322 # Simulator instruction rate (inst/s) -host_op_rate 826248 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12731770448 # Simulator tick rate (ticks/s) -host_mem_usage 380152 # Number of bytes of host memory used -host_seconds 94.83 # Real time elapsed on the host -sim_insts 61477134 # Number of instructions simulated -sim_ops 78349023 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory -system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 610810 # Simulator instruction rate (inst/s) +host_op_rate 778429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11963163223 # Simulator tick rate (ticks/s) +host_mem_usage 383784 # Number of bytes of host memory used +host_seconds 100.62 # Real time elapsed on the host +sim_insts 61457649 # Number of instructions simulated +sim_ops 78322983 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -88,251 +29,292 @@ system.realview.nvmem.bw_inst_read::total 56 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69267 # number of replacements -system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use -system.l2c.total_refs 1645693 # Total number of references to valid blocks. -system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. +system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 354404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 364636 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5307760 # Number of bytes read from this memory +system.physmem.bytes_read::total 62191012 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 354404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 364636 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4163840 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7191184 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82960 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6655189 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65060 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 821896 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43120999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 294430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3538482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 302931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4409557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51666772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 294430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 302931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597361 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3459216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2500920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5974260 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3459216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43120999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 294430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3552606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 302931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6910477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57641032 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70187 # number of replacements +system.l2c.tagsinuse 53228.642974 # Cycle average of tags in use +system.l2c.total_refs 1643789 # Total number of references to valid blocks. +system.l2c.sampled_refs 135350 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.144728 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4213.259554 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40009.498417 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40089.798466 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40070.196166 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.606680 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40029.842942 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.831745 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40003.051908 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40020.615979 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40009.585810 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.813699 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40147.319169 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40087.526994 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -528,27 +498,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7076084 # DTB read hits -system.cpu0.dtb.read_misses 3743 # DTB read misses -system.cpu0.dtb.write_hits 5660386 # DTB write hits -system.cpu0.dtb.write_misses 804 # DTB write misses +system.cpu0.dtb.read_hits 4800541 # DTB read hits +system.cpu0.dtb.read_misses 2116 # DTB read misses +system.cpu0.dtb.write_hits 4101169 # DTB write hits +system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7079827 # DTB read accesses -system.cpu0.dtb.write_accesses 5661190 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 4802657 # DTB read accesses +system.cpu0.dtb.write_accesses 4101574 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12736470 # DTB hits -system.cpu0.dtb.misses 4547 # DTB misses -system.cpu0.dtb.accesses 12741017 # DTB accesses -system.cpu0.itb.inst_hits 29574655 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.dtb.hits 8901710 # DTB hits +system.cpu0.dtb.misses 2521 # DTB misses +system.cpu0.dtb.accesses 8904231 # DTB accesses +system.cpu0.itb.inst_hits 19425295 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -557,86 +527,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses -system.cpu0.itb.hits 29574655 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29576860 # DTB accesses -system.cpu0.numCycles 2414581254 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 19426645 # ITB inst accesses +system.cpu0.itb.hits 19425295 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 19426645 # DTB accesses +system.cpu0.numCycles 2405961611 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28876799 # Number of instructions committed -system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33114839 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241592 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373527 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33114839 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13404188 # number of memory refs -system.cpu0.num_load_insts 7413537 # Number of load instructions -system.cpu0.num_store_insts 5990651 # Number of store instructions -system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles -system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles +system.cpu0.committedInsts 19048182 # Number of instructions committed +system.cpu0.committedOps 25051772 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 22684080 # 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Number of idle cycles +system.cpu0.num_busy_cycles 104459206.176251 # Number of busy cycles +system.cpu0.not_idle_fraction 0.043417 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.956583 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed -system.cpu0.icache.replacements 408135 # number of replacements -system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use -system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # 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number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency +system.cpu0.kern.inst.quiesce 34020 # number of quiesce instructions executed +system.cpu0.icache.replacements 283184 # number of replacements +system.cpu0.icache.tagsinuse 509.502628 # Cycle average of tags in use +system.cpu0.icache.total_refs 19141582 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 283696 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.472160 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.502628 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 19141582 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 19141582 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19141582 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 19141582 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19141582 # number of overall hits +system.cpu0.icache.overall_hits::total 19141582 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 283696 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 283696 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 283696 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 283696 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 283696 # number of overall misses +system.cpu0.icache.overall_misses::total 283696 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929923500 # 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number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014604 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014604 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014604 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014604 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014604 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014604 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.586924 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13852.586924 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13852.586924 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13852.586924 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,120 +615,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 408647 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062733 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13596.209913 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13596.209913 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35907.261581 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35907.261581 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8916.687817 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8916.687817 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8618.227881 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8618.227881 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23502.313804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23502.313804 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,66 +737,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306480 # number of writebacks -system.cpu0.dcache.writebacks::total 306480 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228053 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228053 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141722 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141722 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 204960 # number of writebacks +system.cpu0.dcache.writebacks::total 204960 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146461 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 146461 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116958 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 116958 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7880 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7880 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7695 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7695 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 263419 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 263419 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 263419 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 263419 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698392500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698392500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965725500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965725500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54503500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54503500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5664118000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5664118000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5664118000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5664118000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130688000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130688000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324184500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324184500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6916.687817 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6916.687817 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6620.727745 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6620.727745 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -836,27 +806,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8318170 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5832653 # DTB write hits -system.cpu1.dtb.write_misses 1435 # DTB write misses +system.cpu1.dtb.read_hits 10590618 # DTB read hits +system.cpu1.dtb.read_misses 5230 # DTB read misses +system.cpu1.dtb.write_hits 7384755 # DTB write hits +system.cpu1.dtb.write_misses 1835 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8321833 # DTB read accesses -system.cpu1.dtb.write_accesses 5834088 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10595848 # DTB read accesses +system.cpu1.dtb.write_accesses 7386590 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14150823 # DTB hits -system.cpu1.dtb.misses 5098 # DTB misses -system.cpu1.dtb.accesses 14155921 # DTB accesses -system.cpu1.itb.inst_hits 33211066 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.dtb.hits 17975373 # DTB hits +system.cpu1.dtb.misses 7065 # DTB misses +system.cpu1.dtb.accesses 17982438 # DTB accesses +system.cpu1.itb.inst_hits 43340388 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -865,86 +835,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses -system.cpu1.itb.hits 33211066 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33213237 # DTB accesses -system.cpu1.numCycles 2413083038 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43343405 # ITB inst accesses +system.cpu1.itb.hits 43340388 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 43343405 # DTB accesses +system.cpu1.numCycles 2407389096 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32600335 # Number of instructions committed -system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 963082 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3735102 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37342001 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14689113 # number of memory refs -system.cpu1.num_load_insts 8640454 # Number of load instructions -system.cpu1.num_store_insts 6048659 # Number of store instructions -system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles -system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles -system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles +system.cpu1.committedInsts 42409467 # Number of instructions committed +system.cpu1.committedOps 53271211 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47739499 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1335008 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5483103 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47739499 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 274842107 # number of times the integer registers were read +system.cpu1.num_int_register_writes 51975033 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 18684058 # number of memory refs +system.cpu1.num_load_insts 11000639 # Number of load instructions +system.cpu1.num_store_insts 7683419 # Number of store instructions +system.cpu1.num_idle_cycles 1827105047.254482 # Number of idle cycles +system.cpu1.num_busy_cycles 580284048.745518 # Number of busy cycles +system.cpu1.not_idle_fraction 0.241043 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.758957 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed -system.cpu1.icache.replacements 455071 # number of replacements -system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use -system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits -system.cpu1.icache.overall_hits::total 32755479 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses -system.cpu1.icache.overall_misses::total 455583 # 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average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency +system.cpu1.kern.inst.quiesce 56706 # number of quiesce instructions executed +system.cpu1.icache.replacements 582628 # number of replacements +system.cpu1.icache.tagsinuse 479.068937 # Cycle average of tags in use +system.cpu1.icache.total_refs 42757244 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 583140 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 73.322434 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 479.068937 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935682 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935682 # 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Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.022077 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 84382221000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 473.304740 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.924423 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.924423 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 9101949 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9101949 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6323711 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6323711 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111853 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 111853 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114473 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 114473 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15425660 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15425660 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15425660 # number of overall hits +system.cpu1.dcache.overall_hits::total 15425660 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 253200 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 253200 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 178129 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 178129 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13100 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13100 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10404 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10404 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 431329 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 431329 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 431329 # number of overall misses +system.cpu1.dcache.overall_misses::total 431329 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3278248500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3278248500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5660664500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5660664500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115759000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 115759000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63020500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 63020500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8938913000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8938913000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8938913000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8938913000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9355149 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9355149 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6501840 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6501840 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124953 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 124953 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124877 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 124877 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 15856989 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 15856989 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 15856989 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 15856989 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027065 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027065 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027397 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027397 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104839 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104839 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083314 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083314 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027201 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027201 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027201 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027201 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.268957 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.268957 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31778.455501 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31778.455501 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8836.564885 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8836.564885 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6057.333718 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6057.333718 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20724.117785 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20724.117785 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1075,62 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 266100 # number of writebacks -system.cpu1.dcache.writebacks::total 266100 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170988 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170988 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150171 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150171 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 366483 # number of writebacks +system.cpu1.dcache.writebacks::total 366483 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253200 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 253200 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178129 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 178129 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13100 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13100 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 431329 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 431329 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 431329 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 431329 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2771848500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2771848500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5304406500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5304406500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89559000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89559000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8076255000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8076255000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8076255000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8076255000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40377042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40377042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027397 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027397 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083274 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083274 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027201 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6836.564885 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6836.564885 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 567076826640 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 07e356a30..e07e69ea6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,28 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.624688 # Number of seconds simulated -sim_ticks 2624688029000 # Number of ticks simulated -final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2624688000000 # Number of ticks simulated +final_tick 2624688000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 388710 # Simulator instruction rate (inst/s) -host_op_rate 494628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16947208284 # Simulator tick rate (ticks/s) -host_mem_usage 385844 # Number of bytes of host memory used -host_seconds 154.87 # Real time elapsed on the host +host_inst_rate 509092 # Simulator instruction rate (inst/s) +host_op_rate 647812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22195691402 # Simulator tick rate (ticks/s) +host_mem_usage 379628 # Number of bytes of host memory used +host_seconds 118.25 # Real time elapsed on the host sim_insts 60201138 # Number of instructions simulated sim_ops 76605123 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory @@ -60,7 +48,19 @@ system.physmem.bw_total::cpu.dtb.walker 122 # To system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53608356 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -109,7 +109,7 @@ system.cpu.itb.inst_accesses 61499578 # IT system.cpu.itb.hits 61495107 # DTB hits system.cpu.itb.misses 4471 # DTB misses system.cpu.itb.accesses 61499578 # DTB accesses -system.cpu.numCycles 5249376058 # number of cpu cycles simulated +system.cpu.numCycles 5249376000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60201138 # Number of instructions committed @@ -121,14 +121,14 @@ system.cpu.num_conditional_control_insts 7948064 # nu system.cpu.num_int_insts 68872510 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read -system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written +system.cpu.num_int_register_writes 74180711 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written system.cpu.num_mem_refs 27395681 # number of memory refs system.cpu.num_load_insts 15660705 # Number of load instructions system.cpu.num_store_insts 11734976 # Number of store instructions -system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles -system.cpu.num_busy_cycles 675707863.387743 # Number of busy cycles +system.cpu.num_idle_cycles 4573668198.612257 # Number of idle cycles +system.cpu.num_busy_cycles 675707801.387743 # Number of busy cycles system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles system.cpu.idle_fraction 0.871278 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -154,12 +154,12 @@ system.cpu.icache.demand_misses::cpu.inst 856390 # n system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses system.cpu.icache.overall_misses::total 856390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565472500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11565472500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11565472500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11565472500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11565472500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11565472500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565531500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11565531500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11565531500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11565531500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11565531500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11565531500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses @@ -172,12 +172,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.913065 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13504.913065 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13504.913065 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13504.913065 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.981959 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13504.981959 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13504.981959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13504.981959 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -192,12 +192,12 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 856390 system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852692500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9852692500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852692500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9852692500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852692500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9852692500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9852751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9852751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852751500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9852751500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles @@ -208,58 +208,58 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.913065 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.913065 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.981959 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.981959 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627202 # number of replacements +system.cpu.dcache.replacements 627203 # number of replacements system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use -system.cpu.dcache.total_refs 23656924 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627714 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.687425 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 23656923 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627715 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.687363 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13196261 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196261 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13196260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13196260 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23170044 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23170044 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23170044 # number of overall hits -system.cpu.dcache.overall_hits::total 23170044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368703 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 23170043 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23170043 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23170043 # number of overall hits +system.cpu.dcache.overall_hits::total 23170043 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368704 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368704 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619213 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619213 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619213 # number of overall misses -system.cpu.dcache.overall_misses::total 619213 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201080500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5201080500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8976707500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8976707500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 619214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619214 # number of overall misses +system.cpu.dcache.overall_misses::total 619214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201105500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5201105500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8977284500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8977284500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14177788000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14177788000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14177788000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14177788000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14178390000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14178390000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14178390000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14178390000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses) @@ -282,16 +282,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.423056 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.423056 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35833.729192 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35833.729192 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.452602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.452602 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35836.032494 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35836.032494 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22896.463737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22896.463737 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22897.398961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22897.398961 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,32 +302,32 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks system.cpu.dcache.writebacks::total 595968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368703 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368703 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368704 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368704 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619213 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619213 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619213 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619213 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8475687500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8475687500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 619214 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619214 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619214 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619214 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463697500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463697500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8476264500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8476264500 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131994000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131994000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939362000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12939362000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939362000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12939362000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162796000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162796000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387867000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387867000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223550663000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 223550663000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939962000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12939962000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939962000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12939962000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162296000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162296000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387676000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387676000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223549972000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 223549972000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # mshr miss rate for WriteReq accesses @@ -338,16 +338,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026029 system.cpu.dcache.demand_mshr_miss_rate::total 0.026029 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.423056 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.423056 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33833.729192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33833.729192 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.452602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.452602 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33836.032494 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33836.032494 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -356,16 +356,16 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 61913 # number of replacements -system.cpu.l2cache.tagsinuse 50867.983375 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1683054 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 50867.983864 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1683055 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.221682 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2574063802000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37864.330216 # Average occupied blocks per requestor +system.cpu.l2cache.avg_refs 13.221690 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2574063892000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37864.330390 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6985.667758 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6014.098399 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 6985.667850 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6014.098622 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.577764 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -375,8 +375,8 @@ system.cpu.l2cache.occ_percent::total 0.776184 # Av system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8765 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 844136 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370245 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226697 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 370246 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226698 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 595968 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 595968 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits @@ -386,13 +386,13 @@ system.cpu.l2cache.ReadExReq_hits::total 114435 # nu system.cpu.l2cache.demand_hits::cpu.dtb.walker 8765 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 844136 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484680 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1341132 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 484681 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1341133 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 8765 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 844136 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484680 # number of overall hits -system.cpu.l2cache.overall_hits::total 1341132 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 484681 # number of overall hits +system.cpu.l2cache.overall_hits::total 1341133 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses @@ -414,28 +414,28 @@ system.cpu.l2cache.overall_misses::cpu.data 143034 # system.cpu.l2cache.overall_misses::total 153657 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553303500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513115500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1066836500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553362500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513127500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1066907500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6933900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6933900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6934471000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6934471000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 553303500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7447015500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8000736500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 553362500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7447598500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8001378500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 553303500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7447015500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8000736500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 553362500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7447598500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8001378500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8770 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3554 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 854751 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380103 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247178 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 380104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1247179 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 595968 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 595968 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses) @@ -445,13 +445,13 @@ system.cpu.l2cache.ReadExReq_accesses::total 247611 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8770 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3554 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 854751 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627714 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494789 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627715 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494790 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8770 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3554 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 854751 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627714 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494789 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627715 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494790 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000844 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses @@ -473,23 +473,23 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.227865 system.cpu.l2cache.overall_miss_rate::total 0.102795 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52124.682054 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52050.669507 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.082564 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52130.240226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52051.886792 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52092.549192 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 361.990950 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 361.990950 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52065.687511 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52065.687511 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52069.975071 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52069.975071 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52068.805847 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52072.983984 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52068.805847 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52072.983984 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -521,31 +521,31 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 143034 system.cpu.l2cache.overall_mshr_misses::total 153657 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425853000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394738000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820911000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115017000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115017000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5335717000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5335717000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425912000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394750500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820982500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115023000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115023000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5336288000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5336288000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425853000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5730455000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6156628000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425912000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5731038500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6157270500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425853000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5730455000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6156628000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425912000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5731038500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6157270500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763232500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028072500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856015000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856015000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198619247500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198884087500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses @@ -567,23 +567,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40123.598681 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40043.670116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40085.078854 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40035.851027 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40035.851027 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.441941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40069.441941 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1359273920420 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1359273920420 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 5a613cfa1..551274795 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,184 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112043 # Number of seconds simulated -sim_ticks 5112043255000 # Number of ticks simulated -final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112041 # Number of seconds simulated +sim_ticks 5112040968500 # Number of ticks simulated +final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011485 # Simulator instruction rate (inst/s) -host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25877843451 # Simulator tick rate (ticks/s) -host_mem_usage 397304 # Number of bytes of host memory used -host_seconds 197.55 # Real time elapsed on the host -sim_insts 199813914 # Number of instructions simulated -sim_ops 409133298 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory +host_inst_rate 923075 # Simulator instruction rate (inst/s) +host_op_rate 1890063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23616389220 # Simulator tick rate (ticks/s) +host_mem_usage 353316 # Number of bytes of host memory used +host_seconds 216.46 # Real time elapsed on the host +sim_insts 199810236 # Number of instructions simulated +sim_ops 409125915 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory -system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory +system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory -system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory +system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 106561 # number of replacements -system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits -system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses -system.cpu.l2cache.overall_misses::total 179910 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks -system.cpu.l2cache.writebacks::total 98533 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47570 # number of replacements -system.iocache.tagsinuse 0.042409 # Cycle average of tags in use +system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) +system.iocache.replacements 47569 # number of replacements +system.iocache.tagsinuse 0.042402 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses +system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses -system.iocache.demand_misses::total 47625 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses -system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses +system.iocache.demand_misses::total 47624 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses +system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -200,7 +92,7 @@ system.iocache.writebacks::total 46667 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -210,57 +102,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224086531 # number of cpu cycles simulated +system.cpu.numCycles 10224081960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199813914 # Number of instructions committed -system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses +system.cpu.committedInsts 199810236 # Number of instructions committed +system.cpu.committedOps 409125915 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374289906 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls -system.cpu.num_int_insts 374297264 # number of integer instructions +system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls +system.cpu.num_int_insts 374289906 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915470380 # number of times the integer registers were read -system.cpu.num_int_register_writes 480331069 # number of times the integer registers were written +system.cpu.num_int_register_reads 915450684 # number of times the integer registers were read +system.cpu.num_int_register_writes 480322735 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35626517 # number of memory refs -system.cpu.num_load_insts 27217782 # Number of load instructions -system.cpu.num_store_insts 8408735 # Number of store instructions -system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles -system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles -system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955646 # Percentage of idle cycles +system.cpu.num_mem_refs 35624588 # number of memory refs +system.cpu.num_load_insts 27216588 # Number of load instructions +system.cpu.num_store_insts 8408000 # Number of store instructions +system.cpu.num_idle_cycles 9770609605.299961 # Number of idle cycles +system.cpu.num_busy_cycles 453472354.700038 # Number of busy cycles +system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955647 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790793 # number of replacements +system.cpu.icache.replacements 790732 # number of replacements system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use -system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks. +system.cpu.icache.total_refs 243360722 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.567226 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits -system.cpu.icache.overall_hits::total 243365779 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses -system.cpu.icache.overall_misses::total 791312 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243360722 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243360722 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243360722 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243360722 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243360722 # number of overall hits +system.cpu.icache.overall_hits::total 243360722 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses +system.cpu.icache.overall_misses::total 791251 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244151973 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244151973 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244151973 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244151973 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244151973 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244151973 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses @@ -277,14 +169,14 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3335 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use +system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.warmup_cycle 5102019603000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -324,39 +216,39 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7598 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses +system.cpu.dtb_walker_cache.replacements 7597 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101206381500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -368,39 +260,39 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621273 # number of replacements +system.cpu.dcache.replacements 1621135 # number of replacements system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use -system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20140429 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.419737 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits -system.cpu.dcache.overall_hits::total 20139960 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses -system.cpu.dcache.overall_misses::total 1624057 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8082226 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8082226 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20138167 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20138167 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20138167 # number of overall hits +system.cpu.dcache.overall_hits::total 20138167 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses +system.cpu.dcache.overall_misses::total 1623919 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8398054 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8398054 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21762086 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21762086 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21762086 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21762086 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses @@ -417,8 +309,116 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks -system.cpu.dcache.writebacks::total 1534981 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks +system.cpu.dcache.writebacks::total 1534848 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 106558 # number of replacements +system.cpu.l2cache.tagsinuse 64822.149249 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.994085 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.564956 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits +system.cpu.l2cache.overall_hits::total 2241638 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses +system.cpu.l2cache.overall_misses::total 179909 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks +system.cpu.l2cache.writebacks::total 98530 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 358803d5d..b8216d15c 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.187896 # Nu sim_ticks 5187896410000 # Number of ticks simulated final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 834857 # Simulator instruction rate (inst/s) -host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33766110220 # Simulator tick rate (ticks/s) -host_mem_usage 354356 # Number of bytes of host memory used -host_seconds 153.64 # Real time elapsed on the host +host_inst_rate 812782 # Simulator instruction rate (inst/s) +host_op_rate 1566838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32873266023 # Simulator tick rate (ticks/s) +host_mem_usage 347504 # Number of bytes of host memory used +host_seconds 157.82 # Real time elapsed on the host sim_insts 128269216 # Number of instructions simulated sim_ops 247270559 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory @@ -59,14 +59,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130086932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130086932 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10826250092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10826250092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10826250092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10826250092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -83,19 +83,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155235.002387 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155235.002387 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227643.090374 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227643.090374 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 90078 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.170340 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -109,14 +109,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86510932 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86510932 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266723160 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8266723160 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8353234092 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8353234092 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -125,14 +125,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103235.002387 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 103235.002387 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176941.848459 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176941.848459 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -437,14 +437,14 @@ system.cpu.dcache.demand_misses::cpu.data 1621067 # n system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses system.cpu.dcache.overall_misses::total 1621067 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175236500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18175236500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175237000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18175237000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27078679000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27078679000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27078679000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27078679000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27078679500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27078679500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27078679500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27078679500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses) @@ -461,14 +461,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074870 system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843616 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843999 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843999 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16704.231842 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16704.231842 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16704.232151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16704.232151 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,20 +487,20 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1621067 system.cpu.dcache.demand_mshr_misses::total 1621067 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1621067 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1621067 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562696500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562696500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562697000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8273848500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8273848500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23836545000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23836545000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23836545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23836545500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94146954000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94146954000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469435000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469435000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616389000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616389000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469434500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469434500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616388500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616388500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098224 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098224 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037687 # mshr miss rate for WriteReq accesses @@ -509,14 +509,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074870 system.cpu.dcache.demand_mshr_miss_rate::total 0.074870 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074870 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843616 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843616 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843999 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26283.123727 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26283.123727 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -672,21 +672,21 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 12922 system.cpu.l2cache.overall_mshr_misses::cpu.data 141498 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 154425 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144074500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661603500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144100000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661629500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677130500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6194660000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677130500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6194660000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles @@ -710,21 +710,21 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.785637 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40516.325519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40365.103850 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |