diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref')
7 files changed, 3417 insertions, 3393 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index d7e6fcfdf..8acd582b2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm +boot_loader=/dist/m5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -49,7 +49,7 @@ panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh +readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -99,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img +image_file=/dist/m5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -157,10 +157,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -174,6 +174,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -186,15 +187,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.dstage2_mmu] type=ArmStage2MMU @@ -254,10 +256,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -271,6 +273,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu0.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -283,15 +286,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu0.interrupts] type=ArmInterrupts @@ -386,10 +390,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -403,6 +407,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu0.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -445,15 +450,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu0.toL2Bus] type=CoherentXBar @@ -535,10 +541,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -552,6 +558,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -564,15 +571,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.dstage2_mmu] type=ArmStage2MMU @@ -632,10 +640,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -649,6 +657,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu1.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -661,15 +670,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu1.interrupts] type=ArmInterrupts @@ -764,10 +774,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -781,6 +791,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu1.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -823,15 +834,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu1.toL2Bus] type=CoherentXBar @@ -911,10 +923,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=50 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 @@ -928,6 +940,7 @@ response_latency=50 sequential_access=false size=1024 system=system +tag_latency=50 tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 @@ -940,15 +953,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=50 default_p_state=UNDEFINED eventq_index=0 -hit_latency=50 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1024 +tag_latency=50 [system.l2c] type=Cache @@ -957,10 +971,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -974,6 +988,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 @@ -986,15 +1001,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.membus] type=CoherentXBar diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index c41a1ac7e..f67601b8a 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:54:49 -gem5 executing on e108600-lin, pid 17501 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +gem5 compiled Nov 29 2016 19:03:48 +gem5 started Nov 29 2016 19:04:20 +gem5 executing on zizzer, pid 5756 +command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2870822663000 because m5_exit instruction encountered +Exiting @ tick 2870988926500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 4b2087469..51aad138d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.870823 # Number of seconds simulated -sim_ticks 2870822663000 # Number of ticks simulated -final_tick 2870822663000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.870989 # Number of seconds simulated +sim_ticks 2870988926500 # Number of ticks simulated +final_tick 2870988926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1048966 # Simulator instruction rate (inst/s) -host_op_rate 1268757 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22889064818 # Simulator tick rate (ticks/s) -host_mem_usage 618276 # Number of bytes of host memory used -host_seconds 125.42 # Real time elapsed on the host -sim_insts 131564747 # Number of instructions simulated -sim_ops 159131669 # Number of ops (including micro ops) simulated +host_inst_rate 334502 # Simulator instruction rate (inst/s) +host_op_rate 404603 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7301303629 # Simulator tick rate (ticks/s) +host_mem_usage 607968 # Number of bytes of host memory used +host_seconds 393.22 # Real time elapsed on the host +sim_insts 131531628 # Number of instructions simulated +sim_ops 159096162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 1180196 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1289828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8538816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 149012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 568660 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 388160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1293924 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8559616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 153620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 569684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 405184 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12116336 # Number of bytes read from this memory +system.physmem.bytes_read::total 12163760 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 1180196 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 149012 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1329208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8714368 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu1.inst 153620 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1333816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8766400 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8731932 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8783964 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 26894 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20673 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2483 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20737 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2555 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8922 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6331 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198466 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 136162 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199207 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 136975 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140553 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 201 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 141366 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 411100 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 449289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2974345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 198083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 135209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 411076 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 450689 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2981417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 198428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 141130 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4220510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 411100 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 463006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3035495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4236784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 411076 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464584 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3053443 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3041613 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3035495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3059560 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3053443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 411100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 455393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2974345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 198097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 135209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 411076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 456793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2981417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 198442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 141130 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7262123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198466 # Number of read requests accepted -system.physmem.writeReqs 140553 # Number of write requests accepted -system.physmem.readBursts 198466 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140553 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12692032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue -system.physmem.bytesWritten 8744000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12116336 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8731932 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7296344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199207 # Number of read requests accepted +system.physmem.writeReqs 141366 # Number of write requests accepted +system.physmem.readBursts 199207 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141366 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12740608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue +system.physmem.bytesWritten 8796800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12163760 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8783964 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11821 # Per bank write bursts -system.physmem.perBankRdBursts::1 11810 # Per bank write bursts -system.physmem.perBankRdBursts::2 12062 # Per bank write bursts -system.physmem.perBankRdBursts::3 12027 # Per bank write bursts -system.physmem.perBankRdBursts::4 20473 # Per bank write bursts -system.physmem.perBankRdBursts::5 12098 # Per bank write bursts -system.physmem.perBankRdBursts::6 12277 # Per bank write bursts -system.physmem.perBankRdBursts::7 12432 # Per bank write bursts -system.physmem.perBankRdBursts::8 12179 # Per bank write bursts -system.physmem.perBankRdBursts::9 12459 # Per bank write bursts -system.physmem.perBankRdBursts::10 11810 # Per bank write bursts -system.physmem.perBankRdBursts::11 11367 # Per bank write bursts -system.physmem.perBankRdBursts::12 11535 # Per bank write bursts -system.physmem.perBankRdBursts::13 11583 # Per bank write bursts -system.physmem.perBankRdBursts::14 11073 # Per bank write bursts -system.physmem.perBankRdBursts::15 11307 # Per bank write bursts -system.physmem.perBankWrBursts::0 8516 # Per bank write bursts -system.physmem.perBankWrBursts::1 8730 # Per bank write bursts -system.physmem.perBankWrBursts::2 8955 # Per bank write bursts -system.physmem.perBankWrBursts::3 8735 # Per bank write bursts -system.physmem.perBankWrBursts::4 8248 # Per bank write bursts -system.physmem.perBankWrBursts::5 8655 # Per bank write bursts -system.physmem.perBankWrBursts::6 8964 # Per bank write bursts -system.physmem.perBankWrBursts::7 8852 # Per bank write bursts -system.physmem.perBankWrBursts::8 8742 # Per bank write bursts -system.physmem.perBankWrBursts::9 8980 # Per bank write bursts -system.physmem.perBankWrBursts::10 8644 # Per bank write bursts -system.physmem.perBankWrBursts::11 8478 # Per bank write bursts -system.physmem.perBankWrBursts::12 8438 # Per bank write bursts -system.physmem.perBankWrBursts::13 8004 # Per bank write bursts -system.physmem.perBankWrBursts::14 7925 # Per bank write bursts -system.physmem.perBankWrBursts::15 7759 # Per bank write bursts +system.physmem.perBankRdBursts::0 11688 # Per bank write bursts +system.physmem.perBankRdBursts::1 11970 # Per bank write bursts +system.physmem.perBankRdBursts::2 12095 # Per bank write bursts +system.physmem.perBankRdBursts::3 12159 # Per bank write bursts +system.physmem.perBankRdBursts::4 20723 # Per bank write bursts +system.physmem.perBankRdBursts::5 12090 # Per bank write bursts +system.physmem.perBankRdBursts::6 12329 # Per bank write bursts +system.physmem.perBankRdBursts::7 12246 # Per bank write bursts +system.physmem.perBankRdBursts::8 12200 # Per bank write bursts +system.physmem.perBankRdBursts::9 12543 # Per bank write bursts +system.physmem.perBankRdBursts::10 11897 # Per bank write bursts +system.physmem.perBankRdBursts::11 11487 # Per bank write bursts +system.physmem.perBankRdBursts::12 11682 # Per bank write bursts +system.physmem.perBankRdBursts::13 11835 # Per bank write bursts +system.physmem.perBankRdBursts::14 11042 # Per bank write bursts +system.physmem.perBankRdBursts::15 11086 # Per bank write bursts +system.physmem.perBankWrBursts::0 8412 # Per bank write bursts +system.physmem.perBankWrBursts::1 8881 # Per bank write bursts +system.physmem.perBankWrBursts::2 9049 # Per bank write bursts +system.physmem.perBankWrBursts::3 8857 # Per bank write bursts +system.physmem.perBankWrBursts::4 8522 # Per bank write bursts +system.physmem.perBankWrBursts::5 8714 # Per bank write bursts +system.physmem.perBankWrBursts::6 9020 # Per bank write bursts +system.physmem.perBankWrBursts::7 8690 # Per bank write bursts +system.physmem.perBankWrBursts::8 8720 # Per bank write bursts +system.physmem.perBankWrBursts::9 9031 # Per bank write bursts +system.physmem.perBankWrBursts::10 8698 # Per bank write bursts +system.physmem.perBankWrBursts::11 8602 # Per bank write bursts +system.physmem.perBankWrBursts::12 8645 # Per bank write bursts +system.physmem.perBankWrBursts::13 8180 # Per bank write bursts +system.physmem.perBankWrBursts::14 7869 # Per bank write bursts +system.physmem.perBankWrBursts::15 7560 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 91 # Number of times write queue was full causing retry -system.physmem.totGap 2870821632000 # Total gap between requests +system.physmem.numWrRetry 78 # Number of times write queue was full causing retry +system.physmem.totGap 2870987895000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188706 # Read request sizes (log2) +system.physmem.readPktSize::6 189447 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136162 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 135157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 136975 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 135724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5078 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -181,178 +181,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8175 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 236 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 84864 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 252.592006 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.738576 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.804055 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42330 49.88% 49.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18020 21.23% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6191 7.30% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3740 4.41% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2680 3.16% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1634 1.93% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 923 1.09% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 980 1.15% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8366 9.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 84864 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6753 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.364283 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 566.459907 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6751 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::30 9504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 232 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 85540 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.780968 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.250026 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.334701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42821 50.06% 50.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18143 21.21% 71.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6218 7.27% 78.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3674 4.30% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2664 3.11% 85.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1727 2.02% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 953 1.11% 89.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 967 1.13% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8373 9.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 85540 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6799 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.279453 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 564.517669 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6797 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6753 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6753 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.231749 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.531627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.015829 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5781 85.61% 85.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 288 4.26% 89.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 56 0.83% 90.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 54 0.80% 91.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 265 3.92% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 16 0.24% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.25% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 13 0.19% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.15% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.16% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 146 2.16% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.09% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.18% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.06% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.04% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.09% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6753 # Writes before turning the bus around for reads -system.physmem.totQLat 9353740299 # Total ticks spent queuing -system.physmem.totMemAccLat 13072109049 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 991565000 # Total ticks spent in databus transfers -system.physmem.avgQLat 47166.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6799 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6799 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.216208 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.546976 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.866150 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5813 85.50% 85.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 291 4.28% 89.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 61 0.90% 90.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 49 0.72% 91.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 268 3.94% 95.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.29% 95.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 11 0.16% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 22 0.32% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.18% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.10% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.16% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 154 2.27% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.04% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 7 0.10% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.06% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.07% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.06% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.13% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 4 0.06% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6799 # Writes before turning the bus around for reads +system.physmem.totQLat 9415943788 # Total ticks spent queuing +system.physmem.totMemAccLat 13148543788 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 995360000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47299.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 65916.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 66049.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing -system.physmem.readRowHits 165583 # Number of row buffer hits during reads -system.physmem.writeRowHits 84490 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.83 # Row buffer hit rate for writes -system.physmem.avgGap 8468025.78 # Average gap between requests -system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 311268300 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 165439230 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 749700000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 363599100 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6175288080.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5556148530 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 353114880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 11660360040 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 9231007680 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 675128481165 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 709697287665 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.210424 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2857712170474 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 646078467 # Time in different power states -system.physmem_0.memoryStateTime::REF 2625372000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2808102138000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 24039125004 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9838978559 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 25570970970 # Time in different power states -system.physmem_1.actEnergy 294667800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 156619650 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 666254820 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 349583400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6182663760.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5620280370 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 353139840 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11082999060 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 9548118720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 675230388855 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 709488226485 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.137601 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2857213980946 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 650996744 # Time in different power states -system.physmem_1.memoryStateTime::REF 2628804000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2808400306500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 24864927177 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9973048810 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 24304579769 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing +system.physmem.readRowHits 166164 # Number of row buffer hits during reads +system.physmem.writeRowHits 84817 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.70 # Row buffer hit rate for writes +system.physmem.avgGap 8429875.22 # Average gap between requests +system.physmem.pageHitRate 74.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 312774840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 166239975 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 751842000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 366156900 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6214010400.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5556704280 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 357731520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11629133730 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 9364882080 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 675113260110 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 709836228825 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.244502 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2857863952057 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 659296177 # Time in different power states +system.physmem_0.memoryStateTime::REF 2641884000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2807973624000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 24387714557 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9823730266 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25502677500 # Time in different power states +system.physmem_1.actEnergy 297987900 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 158384325 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 669532080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 351332100 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6199259040.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5628324780 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 351060000 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11278473150 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 9521383680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 675168861345 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 709627419000 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.171771 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2857510482171 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 643430972 # Time in different power states +system.physmem_1.memoryStateTime::REF 2635632000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2808196835750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 24795240087 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9984355357 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24733432334 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -371,9 +372,9 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -381,7 +382,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -411,59 +412,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 7793 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7793 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1456 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6337 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7793 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7793 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7793 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6399 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12413.189561 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11268.612574 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 10437.446912 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 6392 99.89% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 4 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6399 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1181299500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1181299500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1181299500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4982 77.86% 77.86% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1417 22.14% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6399 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7793 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 7799 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7799 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1450 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6349 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7799 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7799 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7799 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6405 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12453.161593 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11389.819011 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6523.003169 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 5861 91.51% 91.51% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 469 7.32% 98.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 66 1.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6405 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1181300000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1181300000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1181300000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4994 77.97% 77.97% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1411 22.03% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6405 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7799 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7793 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7799 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6405 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6399 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14192 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6405 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14204 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25156364 # DTB read hits +system.cpu0.dtb.read_hits 25116933 # DTB read hits system.cpu0.dtb.read_misses 6669 # DTB read misses -system.cpu0.dtb.write_hits 18748845 # DTB write hits -system.cpu0.dtb.write_misses 1124 # DTB write misses +system.cpu0.dtb.write_hits 18718433 # DTB write hits +system.cpu0.dtb.write_misses 1130 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3378 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3389 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1745 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1753 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25163033 # DTB read accesses -system.cpu0.dtb.write_accesses 18749969 # DTB write accesses +system.cpu0.dtb.read_accesses 25123602 # DTB read accesses +system.cpu0.dtb.write_accesses 18719563 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43905209 # DTB hits -system.cpu0.dtb.misses 7793 # DTB misses -system.cpu0.dtb.accesses 43913002 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 43835366 # DTB hits +system.cpu0.dtb.misses 7799 # DTB misses +system.cpu0.dtb.accesses 43843165 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -493,44 +496,44 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3349 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 3348 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12610.587227 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11657.853110 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5955.666994 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 437 18.73% 18.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1604 68.75% 87.48% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 228 9.77% 97.26% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 98.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 1.03% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3049 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12654.159520 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11787.335553 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5848.484815 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 389 16.68% 16.68% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1671 71.66% 88.34% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 217 9.31% 97.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 27 1.16% 98.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 21 0.90% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.13% 99.87% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2033 87.18% 87.18% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 119019454 # ITB inst hits -system.cpu0.itb.inst_misses 3349 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 118797664 # ITB inst hits +system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -539,674 +542,674 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2086 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 119022803 # ITB inst accesses -system.cpu0.itb.hits 119019454 # DTB hits -system.cpu0.itb.misses 3349 # DTB misses -system.cpu0.itb.accesses 119022803 # DTB accesses -system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1460468935.028877 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23678191319.145061 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1076 57.54% 57.54% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 789 42.19% 99.73% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 118801012 # ITB inst accesses +system.cpu0.itb.hits 118797664 # DTB hits +system.cpu0.itb.misses 3348 # DTB misses +system.cpu0.itb.accesses 118801012 # DTB accesses +system.cpu0.numPwrStateTransitions 3664 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1832 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1490824715.864083 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23921725256.931263 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1059 57.81% 57.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 768 41.92% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499962822056 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 139745754496 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731076908504 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5741645326 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499964287288 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1832 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 139798047037 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731190879463 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 5741977853 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed -system.cpu0.committedInsts 115354991 # Number of instructions committed -system.cpu0.committedOps 139381682 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 123361088 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 9690 # Number of float alu accesses -system.cpu0.num_func_calls 12675511 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15701045 # number of instructions that are conditional controls -system.cpu0.num_int_insts 123361088 # number of integer instructions -system.cpu0.num_fp_insts 9690 # number of float instructions -system.cpu0.num_int_register_reads 227079516 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85717450 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 7430 # number of times the floating registers were read +system.cpu0.kern.inst.quiesce 1832 # number of quiesce instructions executed +system.cpu0.committedInsts 115134358 # Number of instructions committed +system.cpu0.committedOps 139131175 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123155389 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses +system.cpu0.num_func_calls 12669084 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15658471 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123155389 # number of integer instructions +system.cpu0.num_fp_insts 9755 # number of float instructions +system.cpu0.num_int_register_reads 226724524 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85578914 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 504946337 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52296035 # number of times the CC registers were written -system.cpu0.num_mem_refs 45041487 # number of memory refs -system.cpu0.num_load_insts 25408167 # Number of load instructions -system.cpu0.num_store_insts 19633320 # Number of store instructions -system.cpu0.num_idle_cycles 5462153817.006098 # Number of idle cycles -system.cpu0.num_busy_cycles 279491508.993903 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048678 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951322 # Percentage of idle cycles -system.cpu0.Branches 29114863 # Number of branches fetched +system.cpu0.num_cc_register_reads 504070716 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52161373 # number of times the CC registers were written +system.cpu0.num_mem_refs 44970744 # number of memory refs +system.cpu0.num_load_insts 25368600 # Number of load instructions +system.cpu0.num_store_insts 19602144 # Number of store instructions +system.cpu0.num_idle_cycles 5462381758.924097 # Number of idle cycles +system.cpu0.num_busy_cycles 279596094.075903 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048693 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951307 # Percentage of idle cycles +system.cpu0.Branches 29063879 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 97984598 68.45% 68.45% # Class of executed instruction -system.cpu0.op_class::IntMult 109968 0.08% 68.53% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8149 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::IntAlu 97803517 68.44% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 109759 0.08% 68.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8141 0.01% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::MemRead 25405911 17.75% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 19625890 13.71% 99.99% # Class of executed instruction +system.cpu0.op_class::MemRead 25366344 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19594649 13.71% 99.99% # Class of executed instruction system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 7430 0.01% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143146475 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 692883 # number of replacements -system.cpu0.dcache.tags.tagsinuse 489.706194 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43033783 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693395 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 62.062436 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1207347000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.706194 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956457 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.956457 # Average percentage of cache occupancy +system.cpu0.op_class::total 142894434 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 691910 # number of replacements +system.cpu0.dcache.tags.tagsinuse 491.841324 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42965158 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 692422 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.050539 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1207348000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.841324 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.960628 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.960628 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88447658 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88447658 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 23895020 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23895020 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18016527 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18016527 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319201 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 319201 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365698 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365698 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362461 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362461 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 41911547 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41911547 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42230748 # number of overall hits -system.cpu0.dcache.overall_hits::total 42230748 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 396353 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396353 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 325830 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325830 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127542 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127542 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21311 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21311 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19654 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19654 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 722183 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 722183 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 849725 # number of overall misses -system.cpu0.dcache.overall_misses::total 849725 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5544958500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5544958500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6307912000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6307912000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337776000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 337776000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 461133500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 461133500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1598000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1598000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11852870500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11852870500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11852870500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11852870500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291373 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24291373 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18342357 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18342357 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446743 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446743 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387009 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387009 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382115 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382115 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42633730 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42633730 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43080473 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43080473 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016317 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016317 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017764 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017764 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285493 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285493 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055066 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055066 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051435 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051435 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016939 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016939 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019724 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019724 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13989.949616 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13989.949616 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19359.518767 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19359.518767 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15849.842804 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15849.842804 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.577592 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.577592 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88306903 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88306903 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 23857214 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23857214 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17987587 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17987587 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319351 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 319351 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364951 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 364951 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361858 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361858 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41844801 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41844801 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42164152 # number of overall hits +system.cpu0.dcache.overall_hits::total 42164152 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 395864 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 395864 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 325028 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 325028 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 126936 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 126936 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21386 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21386 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19587 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19587 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 720892 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 720892 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 847828 # number of overall misses +system.cpu0.dcache.overall_misses::total 847828 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519668500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5519668500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6305983500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6305983500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336140000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 336140000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 459598500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 459598500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1175500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1175500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11825652000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11825652000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11825652000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11825652000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24253078 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24253078 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18312615 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18312615 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446287 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446287 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386337 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386337 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381445 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381445 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42565693 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42565693 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43011980 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43011980 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016322 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016322 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017749 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017749 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284427 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284427 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055356 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055356 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016936 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016936 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13943.345442 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13943.345442 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19401.354653 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19401.354653 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15717.759282 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15717.759282 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23464.466228 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23464.466228 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16412.558174 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16412.558174 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13949.066463 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13949.066463 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16404.193693 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16404.193693 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13948.173450 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13948.173450 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 692883 # number of writebacks -system.cpu0.dcache.writebacks::total 692883 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25228 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25228 # number of ReadReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 691910 # number of writebacks +system.cpu0.dcache.writebacks::total 691910 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25218 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25218 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15026 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15026 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25229 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25229 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25229 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25229 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371125 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 371125 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325829 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325829 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100399 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100399 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6285 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6285 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19654 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19654 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 696954 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 696954 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 797353 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 797353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31790 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60254 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4765649500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4765649500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5981552000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5981552000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664266000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664266000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 99162500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 99162500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 441526500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 441526500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1551000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1551000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10747201500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10747201500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12411467500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12411467500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6632422500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6632422500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6632422500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6632422500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015278 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015278 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224735 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224735 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016240 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016240 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051435 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051435 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016347 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016347 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018508 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018508 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.089929 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.089929 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18357.948494 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18357.948494 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16576.519686 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16576.519686 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15777.645187 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15777.645187 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.968963 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.968963 # average StoreCondReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15019 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15019 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25219 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25219 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25219 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25219 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370646 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 370646 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325027 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325027 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99914 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 99914 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6367 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6367 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19587 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19587 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 695673 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 695673 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 795587 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 795587 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31782 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28454 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60236 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4741194000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741194000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5980473000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5980473000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1654728000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1654728000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97962000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97962000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440045500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440045500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1141500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1141500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10721667000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10721667000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12376395000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12376395000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6631909500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6631909500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6631909500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6631909500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015282 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015282 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017749 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017749 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223878 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223878 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016480 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016480 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051349 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051349 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016344 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016344 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12791.704214 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12791.704214 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18399.926775 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18399.926775 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16561.522910 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16561.522910 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15385.896026 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15385.896026 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22466.202073 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22466.202073 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15420.245095 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15420.245095 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15565.837841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15565.837841 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208632.352941 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208632.352941 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110074.393401 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110074.393401 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1103683 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.436898 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 117915250 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1104195 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 106.788430 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14180312000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436898 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15411.934918 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15411.934918 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15556.306224 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15556.306224 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208668.727582 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208668.727582 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110098.769839 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110098.769839 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1101405 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.436911 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117695738 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1101917 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.809985 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14178985000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436911 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 239143112 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 239143112 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 117915250 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 117915250 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 117915250 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 117915250 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 117915250 # number of overall hits -system.cpu0.icache.overall_hits::total 117915250 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1104204 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1104204 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1104204 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1104204 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1104204 # number of overall misses -system.cpu0.icache.overall_misses::total 1104204 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11911095000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11911095000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11911095000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11911095000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11911095000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11911095000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 119019454 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 119019454 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 119019454 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 119019454 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 119019454 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 119019454 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009278 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009278 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009278 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009278 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009278 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009278 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10787.042068 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10787.042068 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10787.042068 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10787.042068 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10787.042068 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10787.042068 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 238697254 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 238697254 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 117695738 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117695738 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117695738 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117695738 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117695738 # number of overall hits +system.cpu0.icache.overall_hits::total 117695738 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1101926 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1101926 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1101926 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1101926 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1101926 # number of overall misses +system.cpu0.icache.overall_misses::total 1101926 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11884591500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11884591500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11884591500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11884591500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11884591500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11884591500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 118797664 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 118797664 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 118797664 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 118797664 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 118797664 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 118797664 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009276 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009276 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009276 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009276 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10785.290029 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10785.290029 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10785.290029 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10785.290029 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10785.290029 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10785.290029 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1103683 # number of writebacks -system.cpu0.icache.writebacks::total 1103683 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104204 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1104204 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104204 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1104204 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104204 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1104204 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1101405 # number of writebacks +system.cpu0.icache.writebacks::total 1101405 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1101926 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1101926 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1101926 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1101926 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1101926 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1101926 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11358993000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11358993000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11358993000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11358993000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11358993000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11358993000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11333628500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11333628500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11333628500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11333628500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11333628500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11333628500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009278 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009278 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009278 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10287.042068 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10287.042068 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10287.042068 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009276 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009276 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10285.290029 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10285.290029 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10285.290029 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1852661 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1852734 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1842335 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1842343 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236762 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 259898 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15638.452129 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1682248 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 275540 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.105277 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 236049 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 259510 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15639.759609 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1683263 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 275158 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.117442 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14455.048208 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.347817 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.124083 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1181.932022 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.882266 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.072139 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.954495 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 340 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15293 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 30 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 149 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 154 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 821 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6084 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6238 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1977 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020752 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933411 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 61320295 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 61320295 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9508 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4316 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 13824 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 476285 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 476285 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1292383 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1292383 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227392 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 227392 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1042059 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1042059 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376265 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 376265 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9508 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4316 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1042059 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 603657 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1659540 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9508 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4316 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1042059 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 603657 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1659540 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 306 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 159 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 465 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55222 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55222 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19651 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19651 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43215 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 43215 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62145 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 62145 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101544 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 101544 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 306 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 159 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 62145 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 144759 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 207369 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 306 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 159 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 62145 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 144759 # number of overall misses -system.cpu0.l2cache.overall_misses::total 207369 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8941000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3729500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 12670500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 32046500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 32046500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9591500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9591500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1480500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1480500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2734835500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2734835500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3426232500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3426232500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3359763500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3359763500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8941000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3729500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3426232500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6094599000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 9533502000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8941000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3729500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3426232500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6094599000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 9533502000 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 9814 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4475 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 14289 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476285 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 476285 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1292383 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1292383 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55222 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55222 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19651 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19651 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270607 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 270607 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104204 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1104204 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477809 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 477809 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 9814 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4475 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1104204 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 748416 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1866909 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 9814 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4475 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1104204 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 748416 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1866909 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035531 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.032543 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 14465.018905 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.607944 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.119153 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1173.013607 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.882875 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000098 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071595 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954575 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 297 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15346 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 36 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 136 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 119 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 812 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6453 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1818 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018127 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936646 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 61207036 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 61207036 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9838 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4464 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14302 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 475527 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 475527 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1289984 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1289984 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227136 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 227136 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1039867 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1039867 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376033 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 376033 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9838 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4464 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1039867 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 603169 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1657338 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9838 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4464 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1039867 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 603169 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1657338 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 303 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 441 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54610 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 54610 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19582 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19582 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43281 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 43281 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62059 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 62059 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100894 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 100894 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 303 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 62059 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 144175 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 206675 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 303 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 62059 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 144175 # number of overall misses +system.cpu0.l2cache.overall_misses::total 206675 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8179000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3277000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 11456000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 32137500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 32137500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 8911500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 8911500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1089999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1089999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2751603000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2751603000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3417541500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3417541500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3327393000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3327393000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8179000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3277000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3417541500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 6078996000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 9507993500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8179000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3277000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3417541500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 6078996000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 9507993500 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10141 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4602 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 14743 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 475527 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 475527 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1289984 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1289984 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54610 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 54610 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19582 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19582 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270417 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 270417 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1101926 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1101926 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476927 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 476927 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10141 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4602 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1101926 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 747344 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1864013 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10141 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4602 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1101926 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 747344 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1864013 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029987 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.029913 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159697 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159697 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056280 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056280 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212520 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212520 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035531 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056280 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193421 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.111076 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035531 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056280 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193421 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.111076 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23455.974843 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27248.387097 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 580.321249 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 580.321249 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 488.092209 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 488.092209 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 493500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 493500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63284.403564 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63284.403564 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55132.874728 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55132.874728 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33086.775191 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33086.775191 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23455.974843 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55132.874728 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42101.693159 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 45973.612256 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23455.974843 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55132.874728 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42101.693159 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 45973.612256 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.160053 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.160053 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056319 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056319 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211550 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211550 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029987 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056319 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.192917 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.110876 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029987 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056319 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.192917 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.110876 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23746.376812 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25977.324263 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 588.491119 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 588.491119 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 455.086304 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 455.086304 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 217999.800000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 217999.800000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63575.310182 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63575.310182 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55069.232505 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55069.232505 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32979.096874 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32979.096874 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23746.376812 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55069.232505 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42164.009017 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 46004.565139 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23746.376812 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55069.232505 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42164.009017 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 46004.565139 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 10606 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 227429 # number of writebacks -system.cpu0.l2cache.writebacks::total 227429 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1561 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1561 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 33 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 33 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1594 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1594 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1594 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1594 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 306 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 159 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 465 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264666 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 264666 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55222 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55222 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19651 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19651 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41654 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 41654 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62145 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62145 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101511 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101511 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 306 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 159 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62145 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 143165 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 205775 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 306 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 159 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62145 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 143165 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264666 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 470441 # number of overall MSHR misses +system.cpu0.l2cache.unused_prefetches 10584 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 226675 # number of writebacks +system.cpu0.l2cache.writebacks::total 226675 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1590 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1590 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1620 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1620 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1620 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1620 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 303 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 138 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 441 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262593 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 262593 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54610 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54610 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19582 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19582 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41691 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41691 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62059 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62059 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100864 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100864 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 303 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 138 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62059 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142555 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 205055 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 303 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 138 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62059 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142555 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262593 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 467648 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40812 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40804 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28454 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69276 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2775500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9880500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16752910842 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 946229000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 946229000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 294413000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 294413000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1198500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1198500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2205065500 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2205065500 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3053362500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3053362500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2745598500 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2745598500 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2775500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3053362500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4950664000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 8013907000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2775500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3053362500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4950664000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 24766817842 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69258 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2449000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 8810000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16813897141 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16813897141 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 934853500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 934853500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 293341500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 293341500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 885999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 885999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2209696500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2209696500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3045187500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3045187500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2716829000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2716829000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2449000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3045187500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4926525500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 7980523000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2449000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3045187500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4926525500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16813897141 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 24794420141 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377687500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7173328000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377241500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7172882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377687500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7173328000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032543 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377241500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7172882000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029913 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1215,118 +1218,118 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153928 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153928 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056280 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212451 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212451 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110222 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154173 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154173 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056319 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211487 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211487 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.190749 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110007 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.190749 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251989 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21248.387097 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63298.311238 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17135.000543 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17135.000543 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14982.087426 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14982.087426 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 399500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 399500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52937.665050 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52937.665050 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49132.874728 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27047.300293 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27047.300293 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38944.998178 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52645.959519 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.250882 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19977.324263 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64030.256484 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17118.723677 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17118.723677 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14980.160351 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14980.160351 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 177199.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 177199.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53001.762970 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53001.762970 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49069.232505 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26935.566704 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26935.566704 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34558.770299 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38918.938821 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34558.770299 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53019.408061 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200619.298522 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175765.167108 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200655.764269 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175788.697187 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105846.707273 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103547.087014 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 3736636 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1884055 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27898 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 214108 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212409 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 61364 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1691356 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28464 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28464 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 703950 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1320281 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 79590 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 311154 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41858 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112323 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 289865 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 286282 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104204 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 563680 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3258 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330135 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561187 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10874 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23944 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5926140 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141340856 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96515744 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17900 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39256 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 237913756 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 888922 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18673228 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 2798771 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.091578 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.290526 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105870.932665 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103567.558982 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 3728751 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1879521 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27804 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 211480 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209803 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1677 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 61377 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1688185 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28454 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28454 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 702444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1317788 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 79827 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 309039 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 86996 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41768 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111544 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 289661 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 286091 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1101926 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562800 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3273 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3323301 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2556545 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10999 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24289 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5915134 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141049272 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96382808 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18408 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40564 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 237491052 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 885699 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18622452 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 2792086 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.090598 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.289121 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2544165 90.90% 90.90% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 252907 9.04% 99.94% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1699 0.06% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2540806 91.00% 91.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 249603 8.94% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1677 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2798771 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3717731500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2792086 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3710834999 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114379544 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114296030 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1665328000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1661911000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1206139485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1204165985 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6397000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14135489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14154986 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1356,67 +1359,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 3333 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3333 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 662 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2671 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3333 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3333 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3333 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2563 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11950.253609 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10994.949142 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5354.487249 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.12% 0.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 723 28.21% 28.33% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1059 41.32% 69.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 482 18.81% 88.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 76 2.97% 91.42% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 147 5.74% 97.15% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 46 1.79% 98.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 15 0.59% 99.53% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-36863 4 0.16% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 2 0.08% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::53248-57343 2 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2563 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1936423828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1936423828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1936423828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1909 74.48% 74.48% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 654 25.52% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2563 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3333 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 3359 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 669 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2589 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12693.897258 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11812.728196 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5453.033399 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 2 0.08% 0.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 579 22.36% 22.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1101 42.53% 64.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 577 22.29% 87.25% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 84 3.24% 90.50% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 148 5.72% 96.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 49 1.89% 98.11% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 18 0.70% 98.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-36863 23 0.89% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 2 0.08% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-45055 4 0.15% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2589 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1937787828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1937787828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1937787828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1928 74.47% 74.47% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 661 25.53% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3333 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2563 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2563 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5896 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3943012 # DTB read hits -system.cpu1.dtb.read_misses 2827 # DTB read misses -system.cpu1.dtb.write_hits 3420749 # DTB write hits -system.cpu1.dtb.write_misses 506 # DTB write misses +system.cpu1.dtb.read_hits 3975776 # DTB read hits +system.cpu1.dtb.read_misses 2856 # DTB read misses +system.cpu1.dtb.write_hits 3446428 # DTB write hits +system.cpu1.dtb.write_misses 503 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1972 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1973 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 323 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 329 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3945839 # DTB read accesses -system.cpu1.dtb.write_accesses 3421255 # DTB write accesses +system.cpu1.dtb.read_accesses 3978632 # DTB read accesses +system.cpu1.dtb.write_accesses 3446931 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7363761 # DTB hits -system.cpu1.dtb.misses 3333 # DTB misses -system.cpu1.dtb.accesses 7367094 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7422204 # DTB hits +system.cpu1.dtb.misses 3359 # DTB misses +system.cpu1.dtb.accesses 7425563 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1446,7 +1449,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1746 # Table walker walks requested system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate @@ -1455,24 +1458,24 @@ system.cpu1.itb.walker.walkWaitTime::samples 1746 system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12715.898826 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11637.572785 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6041.889650 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 210 18.97% 18.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 573 51.76% 70.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 161 14.54% 85.28% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 52 4.70% 94.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.90% 98.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.19% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13066.847335 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12198.452511 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5775.216215 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 143 12.92% 12.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 638 57.63% 70.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 167 15.09% 85.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 51 4.61% 90.24% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 51 4.61% 94.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.53% 97.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 98.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.09% 99.01% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.45% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.27% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1937292828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1937292828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1937292828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::samples -1938367828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1938367828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1938367828 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated @@ -1483,7 +1486,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16565425 # ITB inst hits +system.cpu1.itb.inst_hits 16753470 # ITB inst hits system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1500,661 +1503,661 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16567171 # ITB inst accesses -system.cpu1.itb.hits 16565425 # DTB hits +system.cpu1.itb.inst_accesses 16755216 # ITB inst accesses +system.cpu1.itb.hits 16753470 # DTB hits system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 16567171 # DTB accesses -system.cpu1.numPwrStateTransitions 5507 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2754 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1032876592.840595 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25746480816.391750 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1963 71.28% 71.28% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 785 28.50% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 16755216 # DTB accesses +system.cpu1.numPwrStateTransitions 5461 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2731 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1041523757.275357 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25854556705.104488 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1955 71.59% 71.59% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 770 28.19% 99.78% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 929980503556 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2754 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 26280526317 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844542136683 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 5740713090 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 929980418584 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2731 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 26587545381 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844401381119 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 5741033861 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2754 # number of quiesce instructions executed -system.cpu1.committedInsts 16209756 # Number of instructions committed -system.cpu1.committedOps 19749987 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17811459 # Number of integer alu accesses +system.cpu1.kern.inst.quiesce 2731 # number of quiesce instructions executed +system.cpu1.committedInsts 16397270 # Number of instructions committed +system.cpu1.committedOps 19964987 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17986629 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 1029227 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1814790 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17811459 # number of integer instructions +system.cpu1.num_func_calls 1033857 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1854028 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17986629 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 32322640 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12491718 # number of times the integer registers were written +system.cpu1.num_int_register_reads 32622652 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12608250 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 72198073 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6423445 # number of times the CC registers were written -system.cpu1.num_mem_refs 7597281 # number of memory refs -system.cpu1.num_load_insts 4054552 # Number of load instructions -system.cpu1.num_store_insts 3542729 # Number of store instructions -system.cpu1.num_idle_cycles 5688160571.384175 # Number of idle cycles -system.cpu1.num_busy_cycles 52552518.615825 # Number of busy cycles -system.cpu1.not_idle_fraction 0.009154 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.990846 # Percentage of idle cycles -system.cpu1.Branches 2922489 # Number of branches fetched +system.cpu1.num_cc_register_reads 72946565 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6544066 # number of times the CC registers were written +system.cpu1.num_mem_refs 7656991 # number of memory refs +system.cpu1.num_load_insts 4087327 # Number of load instructions +system.cpu1.num_store_insts 3569664 # Number of store instructions +system.cpu1.num_idle_cycles 5687867512.323336 # Number of idle cycles +system.cpu1.num_busy_cycles 53166348.676665 # Number of busy cycles +system.cpu1.not_idle_fraction 0.009261 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.990739 # Percentage of idle cycles +system.cpu1.Branches 2968001 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12473914 62.06% 62.06% # Class of executed instruction -system.cpu1.op_class::IntMult 26414 0.13% 62.19% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3315 0.02% 62.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::MemRead 4054036 20.17% 82.37% # Class of executed instruction -system.cpu1.op_class::MemWrite 3541453 17.62% 99.99% # Class of executed instruction +system.cpu1.op_class::IntAlu 12630695 62.17% 62.17% # Class of executed instruction +system.cpu1.op_class::IntMult 26529 0.13% 62.30% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatMisc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3311 0.02% 62.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.31% # Class of executed instruction +system.cpu1.op_class::MemRead 4086811 20.11% 82.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 3568388 17.56% 99.99% # Class of executed instruction system.cpu1.op_class::FloatMemRead 516 0.00% 99.99% # Class of executed instruction system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 20100990 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 186832 # number of replacements -system.cpu1.dcache.tags.tagsinuse 467.596388 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7094042 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 187196 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.896333 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 105561729000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.596388 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913274 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.913274 # Average percentage of cache occupancy +system.cpu1.op_class::total 20317592 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 188214 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.650282 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7155880 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 188578 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.946526 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105561245500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.650282 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917286 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.917286 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14946466 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14946466 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3631076 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3631076 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3232073 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3232073 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48864 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48864 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70916 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70916 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6863149 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6863149 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6912013 # number of overall hits -system.cpu1.dcache.overall_hits::total 6912013 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133685 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133685 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 91868 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 91868 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30333 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30333 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17012 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17012 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23235 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23235 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 225553 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 225553 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 255886 # number of overall misses -system.cpu1.dcache.overall_misses::total 255886 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2037941500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2037941500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2527681500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2527681500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319638500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 319638500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545121500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 545121500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1812500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1812500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4565623000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4565623000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4565623000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4565623000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3764761 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3764761 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3323941 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3323941 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79197 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79197 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95985 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95985 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94151 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94151 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7088702 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7088702 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7167899 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7167899 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035510 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035510 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027638 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027638 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.383007 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.383007 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177236 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177236 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031819 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031819 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035699 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035699 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.354266 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.354266 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27514.275918 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 27514.275918 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18789.001881 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18789.001881 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23461.222294 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23461.222294 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 15064679 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15064679 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3662279 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3662279 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3257080 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3257080 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49206 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49206 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79332 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79332 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71298 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71298 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6919359 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6919359 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6968565 # number of overall hits +system.cpu1.dcache.overall_hits::total 6968565 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 134376 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 134376 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92202 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92202 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30516 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30516 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17009 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17009 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23197 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23197 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 226578 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 226578 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 257094 # number of overall misses +system.cpu1.dcache.overall_misses::total 257094 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2053970000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2053970000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2521876000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2521876000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321694000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 321694000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544347500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 544347500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1836500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1836500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4575846000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4575846000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4575846000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4575846000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3796655 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3796655 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3349282 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3349282 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79722 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79722 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96341 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96341 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94495 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94495 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7145937 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7145937 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7225659 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7225659 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035393 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035393 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027529 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027529 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382780 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382780 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176550 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176550 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.245484 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.245484 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031707 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031707 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035581 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035581 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15285.244389 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15285.244389 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27351.640962 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27351.640962 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18913.163619 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18913.163619 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23466.288744 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23466.288744 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20241.907667 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20241.907667 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17842.410292 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17842.410292 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20195.455870 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20195.455870 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17798.338351 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17798.338351 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 186832 # number of writebacks -system.cpu1.dcache.writebacks::total 186832 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 254 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12014 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12014 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 254 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 254 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 254 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133431 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133431 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91868 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91868 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29599 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29599 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4998 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4998 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23235 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23235 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254898 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254898 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3096 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5547 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1895035500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1895035500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2435813500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2435813500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 504348000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 504348000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87440500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87440500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521927500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521927500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1771500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1771500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4330849000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4330849000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4835197000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4835197000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443722000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443722000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443722000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443722000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027638 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027638 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373739 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373739 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052071 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052071 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246784 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246784 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031783 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031783 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035561 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14202.363019 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14202.363019 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26514.275918 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26514.275918 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17039.359438 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17039.359438 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17495.098039 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17495.098039 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22462.986873 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22462.986873 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 188214 # number of writebacks +system.cpu1.dcache.writebacks::total 188214 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 253 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 253 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12043 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12043 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 253 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 253 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 253 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 253 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134123 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 134123 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92202 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92202 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29799 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29799 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4966 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4966 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23197 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23197 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 226325 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 226325 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 256124 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 256124 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3085 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3085 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2441 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5526 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5526 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1909849500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1909849500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2429674000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2429674000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 508192000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 508192000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89547000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89547000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521193500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521193500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1793500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4339523500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4339523500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4847715500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4847715500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443097000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443097000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443097000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443097000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035327 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035327 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027529 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027529 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373786 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373786 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051546 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051546 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.245484 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.245484 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031672 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031672 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035446 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035446 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14239.537589 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14239.537589 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26351.640962 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26351.640962 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17053.995101 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17053.995101 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18032.017720 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18032.017720 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22468.142432 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22468.142432 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19222.672981 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19222.672981 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18969.144521 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18969.144521 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143321.059432 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143321.059432 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79993.149450 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79993.149450 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 505764 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.454577 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 16059144 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 506276 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.720137 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 85411536000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.454577 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973544 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973544 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19173.858389 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19173.858389 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18927.220799 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18927.220799 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143629.497569 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143629.497569 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80184.039088 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80184.039088 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 506865 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.456606 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16246088 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 507377 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 32.019757 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 85409397000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.456606 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973548 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973548 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 389 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33637116 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33637116 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 16059144 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16059144 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16059144 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16059144 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16059144 # number of overall hits -system.cpu1.icache.overall_hits::total 16059144 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 506276 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 506276 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 506276 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 506276 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 506276 # number of overall misses -system.cpu1.icache.overall_misses::total 506276 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4773110000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4773110000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4773110000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4773110000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4773110000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4773110000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16565420 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16565420 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16565420 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16565420 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16565420 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16565420 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030562 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030562 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030562 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030562 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030562 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030562 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9427.881235 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9427.881235 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9427.881235 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9427.881235 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 34014307 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 34014307 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 16246088 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16246088 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16246088 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16246088 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16246088 # number of overall hits +system.cpu1.icache.overall_hits::total 16246088 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 507377 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 507377 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 507377 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 507377 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 507377 # number of overall misses +system.cpu1.icache.overall_misses::total 507377 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4790701000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4790701000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4790701000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4790701000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4790701000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4790701000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16753465 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16753465 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16753465 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16753465 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16753465 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16753465 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030285 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030285 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030285 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030285 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030285 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030285 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9442.093355 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9442.093355 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9442.093355 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9442.093355 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9442.093355 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9442.093355 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 505764 # number of writebacks -system.cpu1.icache.writebacks::total 505764 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506276 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 506276 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 506276 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 506276 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 506276 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 506276 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 506865 # number of writebacks +system.cpu1.icache.writebacks::total 506865 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 507377 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 507377 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 507377 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 507377 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 507377 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 507377 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4519972000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4519972000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4519972000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4519972000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4519972000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4519972000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17010500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17010500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17010500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 17010500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030562 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030562 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030562 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8927.881235 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96104.519774 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96104.519774 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 197759 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 197759 # number of prefetch candidates identified +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4537012500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4537012500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4537012500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4537012500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4537012500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4537012500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17068500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17068500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17068500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 17068500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030285 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030285 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030285 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8942.093355 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8942.093355 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8942.093355 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 202159 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 202159 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59073 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 42341 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14550.545082 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 605184 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 56718 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.670052 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 59833 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 43683 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14553.446834 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 604546 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 57834 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 10.453124 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14134.079332 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.459040 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.079959 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 410.926752 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.862676 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000211 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025081 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.888095 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 333 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 35 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 296 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2799 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10333 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020325 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24327160 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24327160 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3447 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1877 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 5324 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 114448 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 114448 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 567034 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 567034 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27676 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27676 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 485156 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 485156 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98414 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 98414 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3447 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1877 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 485156 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 126090 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 616570 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3447 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1877 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 485156 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 126090 # number of overall hits -system.cpu1.l2cache.overall_hits::total 616570 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 422 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 327 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 749 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29541 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29541 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23233 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23233 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34651 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34651 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21120 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 21120 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69614 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 69614 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 422 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 327 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 21120 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 104265 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 126134 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 422 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 327 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 21120 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 104265 # number of overall misses -system.cpu1.l2cache.overall_misses::total 126134 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8582000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6568500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 15150500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13749500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 13749500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16999500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16999500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1709500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1709500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1487134000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1487134000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 835278500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 835278500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1591067500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1591067500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8582000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6568500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 835278500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3078201500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3928630500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8582000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6568500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 835278500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3078201500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3928630500 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3869 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2204 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 6073 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114448 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 114448 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 567034 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 567034 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29541 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29541 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23233 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23233 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62327 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 62327 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 506276 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 506276 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168028 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 168028 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3869 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2204 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 506276 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 230355 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 742704 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3869 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2204 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 506276 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 230355 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 742704 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.148367 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.123333 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 14136.855711 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.245443 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.035798 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 412.309882 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.862845 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000137 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025165 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.888272 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 316 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13825 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 293 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1016 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2429 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10380 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019287 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.843811 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 24413579 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24413579 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3816 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2015 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5831 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 114934 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 114934 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 568988 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 568988 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27893 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27893 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 485948 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 485948 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99069 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 99069 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3816 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2015 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 485948 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 126962 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 618741 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3816 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2015 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 485948 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 126962 # number of overall hits +system.cpu1.l2cache.overall_hits::total 618741 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 441 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 325 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 766 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29445 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29445 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23189 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23189 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34864 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 34864 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21429 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 21429 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69819 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 69819 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 441 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 325 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 21429 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 104683 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 126878 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 441 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 325 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 21429 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 104683 # number of overall misses +system.cpu1.l2cache.overall_misses::total 126878 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9097000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6572000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 15669000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14547500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 14547500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17306000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17306000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1729000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1729000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1479795000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1479795000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 845906500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 845906500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1606277000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1606277000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9097000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6572000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 845906500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3086072000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3947647500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9097000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6572000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 845906500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3086072000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3947647500 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4257 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2340 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6597 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114934 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 114934 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 568988 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 568988 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29445 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29445 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23189 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23189 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62757 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 62757 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 507377 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 507377 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168888 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 168888 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4257 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2340 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 507377 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 231645 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 745619 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4257 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2340 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 507377 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 231645 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 745619 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138889 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.116113 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555955 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555955 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.041716 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.041716 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414300 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414300 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.148367 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.041716 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452627 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.169831 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.148367 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.041716 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452627 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.169831 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20087.155963 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20227.636849 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 465.437866 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 465.437866 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 731.696294 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 731.696294 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 854750 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 854750 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42917.491559 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42917.491559 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39549.171402 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39549.171402 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22855.567846 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22855.567846 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20087.155963 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39549.171402 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29522.864816 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 31146.483105 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20087.155963 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39549.171402 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29522.864816 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 31146.483105 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555540 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555540 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042235 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042235 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.413404 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.413404 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138889 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042235 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.451911 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.170165 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138889 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042235 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.451911 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.170165 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20221.538462 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20455.613577 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 494.056716 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 494.056716 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 746.302126 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 746.302126 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 216125 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 216125 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42444.785452 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42444.785452 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39474.847170 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39474.847170 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23006.302009 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23006.302009 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20221.538462 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39474.847170 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29480.163923 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31113.727360 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20221.538462 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39474.847170 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29480.163923 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31113.727360 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 833 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 32020 # number of writebacks -system.cpu1.l2cache.writebacks::total 32020 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 87 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 87 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 87 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 87 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 422 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 327 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25249 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 25249 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29541 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29541 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23233 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23233 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34564 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34564 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21120 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21120 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69614 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69614 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 422 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 327 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21120 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104178 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 126047 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 422 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 327 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21120 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104178 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25249 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 151296 # number of overall MSHR misses +system.cpu1.l2cache.unused_prefetches 815 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 32960 # number of writebacks +system.cpu1.l2cache.writebacks::total 32960 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 84 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 84 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 84 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 84 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 84 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 441 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 325 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 766 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25865 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 25865 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29445 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29445 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23189 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23189 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34780 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34780 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21429 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21429 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69819 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69819 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 441 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 325 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21429 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104599 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 126794 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 441 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 325 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21429 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104599 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25865 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 152659 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3273 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3085 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3262 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2441 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5724 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4606500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10656500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 879904235 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 451017000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 451017000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347632000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347632000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1463500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1463500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1270463000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1270463000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 708558500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 708558500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1173383500 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1173383500 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4606500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 708558500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2443846500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3163061500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4606500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 708558500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2443846500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4042965735 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15683000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418607000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 434290000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15683000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418607000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 434290000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.123333 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5526 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5703 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4622000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11073000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 943203517 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 943203517 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 450885000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 450885000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347198000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347198000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1471000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1471000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1260374500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1260374500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 717332500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 717332500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1187363000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1187363000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4622000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 717332500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2447737500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3176143000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4622000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 717332500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2447737500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 943203517 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4119346517 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15741000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418070500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 433811500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15741000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418070500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 433811500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.116113 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2163,118 +2166,118 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554559 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554559 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041716 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414300 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414300 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.169714 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554201 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554201 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042235 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.413404 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.413404 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.451549 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170052 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.451549 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.203710 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14227.636849 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 34849.072637 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15267.492637 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15267.492637 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14962.854560 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.854560 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 731750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 731750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36756.827913 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36756.827913 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33549.171402 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16855.567846 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16855.567846 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25094.302125 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26722.224877 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135208.979328 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132688.664833 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75465.476834 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75871.767994 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1488382 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751796 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 112776 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104479 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8297 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 12601 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 724485 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2451 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2451 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 147576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 578148 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 27257 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30156 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71390 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40982 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85466 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69531 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66980 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506276 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263615 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 248 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518670 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839199 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5528 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9873 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2373270 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64771268 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29426964 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8816 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15476 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94222524 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 331491 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4839132 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1057684 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.131012 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.359912 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.204741 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14455.613577 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36466.403132 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15312.786551 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15312.786551 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14972.530079 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.530079 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183875 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183875 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36238.484761 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36238.484761 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33474.847170 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17006.302009 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17006.302009 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23401.155843 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25049.631686 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23401.155843 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26983.974197 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135517.179903 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132989.423666 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75655.175534 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76067.245309 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1493074 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 754096 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11157 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 112771 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 12635 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 726264 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2441 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2441 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 148991 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 580145 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 27848 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30881 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70910 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40918 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85257 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69946 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67407 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 507377 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 264100 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 245 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1521973 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 842546 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5664 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10306 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2380489 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64912196 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29583168 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9360 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17028 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94521752 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 332142 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4881760 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1061400 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.130546 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.359362 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 927412 87.68% 87.68% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 121975 11.53% 99.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8297 0.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 931138 87.73% 87.73% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 121963 11.49% 99.22% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8299 0.78% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1057684 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1442349000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1061400 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1447209000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79817806 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79433455 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 759591000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 761242500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 376283000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 378138998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6005497 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6050996 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution @@ -2325,66 +2328,66 @@ system.iobus.pkt_size_system.bridge.master::total 162796 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48719500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 48592000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 318500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 615500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 46500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6166000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6203500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32044000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32039500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187769062 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187757841 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.383154 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.377097 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 289903742000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.383154 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.898947 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.898947 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290025611000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.377097 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898569 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898569 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328311 # Number of tag accesses system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2393,14 +2396,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 40888377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 40888377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4391190685 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4391190685 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4432079062 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4432079062 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4432079062 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4432079062 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 40988875 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 40988875 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4375977966 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4375977966 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4416966841 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4416966841 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4416966841 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4416966841 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2417,19 +2420,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 160346.576471 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 160346.576471 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121223.241083 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 121223.241083 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121496.725842 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121496.725842 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 160740.686275 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160740.686275 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120803.278655 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120803.278655 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 121082.454042 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121082.454042 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 121082.454042 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121082.454042 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.333333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -2441,14 +2444,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 28138377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 28138377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2577641992 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2577641992 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2605780369 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2605780369 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2605780369 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2605780369 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 28238875 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 28238875 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2562446714 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2562446714 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2590685589 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2590685589 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2590685589 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2590685589 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2457,565 +2460,565 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110346.576471 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110346.576471 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71158.403048 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71158.403048 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 71432.341046 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 71432.341046 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 71432.341046 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 71432.341046 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 136024 # number of replacements -system.l2c.tags.tagsinuse 65074.400284 # Cycle average of tags in use -system.l2c.tags.total_refs 524979 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 201414 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.606467 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 103030494000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6378.541377 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.901261 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.045973 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7223.294710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6923.893951 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37646.371687 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1427.225105 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3211.431328 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2259.694892 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.097329 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110740.686275 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 110740.686275 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70738.922096 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70738.922096 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 71018.547356 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 71018.547356 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 71018.547356 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 71018.547356 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 137086 # number of replacements +system.l2c.tags.tagsinuse 65074.643000 # Cycle average of tags in use +system.l2c.tags.total_refs 524868 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 202455 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.592517 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 103102985000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6607.466111 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.944223 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7194.422354 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6927.905114 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37164.228779 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1475.884148 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3147.084233 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2554.669060 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.100822 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.110219 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.105650 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.574438 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.049003 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034480 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.992957 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 34321 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.109778 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.105711 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.567081 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.022520 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.048021 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.038981 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.992960 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 34101 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31064 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4958 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29180 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31263 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29155 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29816 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.523697 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30056 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.520340 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.473999 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6089608 # Number of tag accesses -system.l2c.tags.data_accesses 6089608 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 259449 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 259449 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 40103 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4906 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 45009 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2386 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2218 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4604 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4006 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1413 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5419 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 142 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 81 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 44259 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 52827 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45774 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 38 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 20 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 18793 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 10825 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5311 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 178070 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 142 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 81 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 44259 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 56833 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45774 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 18793 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12238 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5311 # number of demand (read+write) hits -system.l2c.demand_hits::total 183489 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 142 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 81 # number of overall hits -system.l2c.overall_hits::cpu0.inst 44259 # number of overall hits -system.l2c.overall_hits::cpu0.data 56833 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45774 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits -system.l2c.overall_hits::cpu1.inst 18793 # number of overall hits -system.l2c.overall_hits::cpu1.data 12238 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5311 # number of overall hits -system.l2c.overall_hits::total 183489 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 592 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 252 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 844 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 118 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 92 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 210 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11217 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8015 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19232 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 9 # number of ReadSharedReq misses +system.l2c.tags.occ_task_id_percent::1024 0.477036 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6098343 # Number of tag accesses +system.l2c.tags.data_accesses 6098343 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 259635 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 259635 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 39907 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4995 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 44902 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2353 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2177 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4530 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1485 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5463 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 146 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 44179 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 52512 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45683 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 56 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 30 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 19035 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 10985 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5208 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 177905 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 44179 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 56490 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 45683 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 56 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 30 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 19035 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12470 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5208 # number of demand (read+write) hits +system.l2c.demand_hits::total 183368 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits +system.l2c.overall_hits::cpu0.inst 44179 # number of overall hits +system.l2c.overall_hits::cpu0.data 56490 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 45683 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 56 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 30 # number of overall hits +system.l2c.overall_hits::cpu1.inst 19035 # number of overall hits +system.l2c.overall_hits::cpu1.data 12470 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5208 # number of overall hits +system.l2c.overall_hits::total 183368 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 508 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 339 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 847 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 113 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 106 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 219 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11276 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7954 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19230 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 17886 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9091 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2327 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 875 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 169844 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17880 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9100 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133915 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 952 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6331 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 170581 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17886 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20308 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 133589 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2327 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8890 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6065 # number of demand (read+write) misses -system.l2c.demand_misses::total 189076 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses +system.l2c.demand_misses::cpu0.inst 17880 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20376 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 133915 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8906 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 6331 # number of demand (read+write) misses +system.l2c.demand_misses::total 189811 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17886 # number of overall misses -system.l2c.overall_misses::cpu0.data 20308 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 133589 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2327 # number of overall misses -system.l2c.overall_misses::cpu1.data 8890 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6065 # number of overall misses -system.l2c.overall_misses::total 189076 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 9921500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 813500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 10735000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 614000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 361000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 975000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1635531500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 824298500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2459830000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1956500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 180000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1955907500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 1124374000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261946000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 108772000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 20157534022 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1956500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 180000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1955907500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 2759905500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 261946000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 933070500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22617364022 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1956500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 180000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1955907500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 2759905500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 261946000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 933070500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22617364022 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 259449 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 259449 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 40695 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5158 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 45853 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2504 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2310 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4814 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15223 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9428 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24651 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 151 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 83 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 62145 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 61918 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179363 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 38 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 21120 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 11700 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11376 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 347914 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 151 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 83 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 62145 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 77141 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179363 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 38 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 21120 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 21128 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11376 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 372565 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 151 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 83 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 62145 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 77141 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179363 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 38 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 21120 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 21128 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11376 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 372565 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.014547 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.048856 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.018407 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.047125 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.039827 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.043623 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.736846 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.850127 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.780171 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.024096 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.287811 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146823 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.110180 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.074786 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.488178 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.024096 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.287811 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.263258 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.110180 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.420769 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.507498 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.024096 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.287811 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.263258 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.110180 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.420769 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.507498 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16759.290541 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3228.174603 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 12719.194313 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5203.389831 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3923.913043 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4642.857143 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145808.282072 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102844.479102 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 127902.974210 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109354.103768 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123679.903201 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112568.113451 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 124310.857143 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 118682.638315 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 109354.103768 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 135902.378373 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 112568.113451 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 104957.311586 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 119620.491347 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 109354.103768 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 135902.378373 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 112568.113451 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 104957.311586 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 119620.491347 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 873 # number of cycles access was blocked +system.l2c.overall_misses::cpu0.inst 17880 # number of overall misses +system.l2c.overall_misses::cpu0.data 20376 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 133915 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses +system.l2c.overall_misses::cpu1.data 8906 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 6331 # number of overall misses +system.l2c.overall_misses::total 189811 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 9776500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1123500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 10900000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 603500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 259000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 862500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1642507500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 809344500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2451852000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1270000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 179500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1949692500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106153000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 265577500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 121124000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 20274349932 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1270000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 179500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1949692500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 2748660500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 265577500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 930468500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22726201932 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1270000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 179500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1949692500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 2748660500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 265577500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 930468500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22726201932 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 259635 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 259635 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 40415 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5334 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 45749 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2466 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2283 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4749 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15254 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9439 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 24693 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 153 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 73 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 62059 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 61612 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179598 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 56 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 21429 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 11937 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11539 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 348486 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 153 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 62059 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 76866 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179598 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 56 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 21429 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 21376 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11539 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 373179 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 153 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 62059 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 76866 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179598 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 56 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 21429 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 21376 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11539 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 373179 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012570 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.063555 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.018514 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.045823 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.046430 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.046115 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.739216 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.842674 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.778763 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027397 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.288113 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.147699 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.111718 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.079752 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.489492 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.027397 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.288113 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.265085 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.111718 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.416635 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.508633 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.027397 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.288113 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.265085 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.111718 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.416635 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.508633 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19245.078740 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3314.159292 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 12868.949233 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5340.707965 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2443.396226 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3938.356164 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145664.020929 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101753.143073 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 127501.404056 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89750 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109043.204698 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121555.274725 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110934.628237 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 127231.092437 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 118854.678610 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 109043.204698 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 134896.962112 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 110934.628237 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 104476.588817 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 119730.689644 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 109043.204698 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 134896.962112 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 110934.628237 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 104476.588817 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 119730.689644 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 109.125000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 99972 # number of writebacks -system.l2c.writebacks::total 99972 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 3644 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 3644 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 592 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 252 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 844 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 118 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 92 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 210 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11217 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8015 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19232 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadSharedReq MSHR misses +system.l2c.writebacks::writebacks 100785 # number of writebacks +system.l2c.writebacks::total 100785 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 5 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 3664 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 3664 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 508 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 339 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 847 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 113 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 106 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 219 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11276 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7954 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19230 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17879 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9091 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2318 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 875 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 169828 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9100 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2390 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 952 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 170576 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 17879 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20308 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2318 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8890 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 189060 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20376 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2390 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8906 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 189806 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 17879 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20308 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2318 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8890 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 189060 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20376 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2390 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8906 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 189806 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3093 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 44082 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30915 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3082 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 44063 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30895 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5544 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 74997 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13698000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5474500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 19172500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3092000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2171500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 5263500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1523361500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 744148500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2267510000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 160000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1775966000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1033464000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 238288500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 100021501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 18457620033 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1775966000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2556825500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 238288500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 844170001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 20725130033 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 160000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1775966000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2556825500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 238288500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 844170001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 20725130033 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5523 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 74958 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 11966500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 7400000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 19366500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2957500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2539000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 5496500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1529747500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 729804500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2259552000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 159500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1770876500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1015153000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 241454001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 111604000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 18568333447 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 159500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1770876500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2544900500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 241454001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 841408500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 20827885447 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 159500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1770876500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2544900500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 241454001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 841408500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 20827885447 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 633244000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5805450500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12497000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362875500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6814067000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5805153000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12555000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362546500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6813498500 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 633244000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5805450500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12497000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362875500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6814067000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5805153000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12555000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362546500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6813498500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014547 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.048856 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.018407 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.047125 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.039827 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.043623 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.736846 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850127 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.780171 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146823 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.074786 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.488132 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.507455 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.507455 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23138.513514 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21724.206349 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22716.232227 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26203.389831 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23603.260870 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25064.285714 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135808.282072 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92844.479102 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117902.974210 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113679.903201 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 114310.286857 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108684.198324 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012570 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.063555 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.018514 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.045823 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.046430 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.046115 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739216 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842674 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.778763 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.147699 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.079752 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.489477 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.265085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.416635 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.508619 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.265085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.416635 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.508619 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23556.102362 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21828.908555 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22864.817001 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26172.566372 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23952.830189 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25098.173516 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135664.020929 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 91753.143073 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117501.404056 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111555.274725 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 117231.092437 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108856.658891 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 124896.962112 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94476.588817 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 109732.492371 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 124896.962112 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94476.588817 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 109732.492371 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182618.763762 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117321.532493 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154577.083617 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182655.370965 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117633.517197 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154630.835395 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96349.628240 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65453.733766 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 90857.860981 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 501880 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 282396 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96373.480975 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65643.038204 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 90897.549294 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 503139 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 282937 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 589 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 44082 # Transaction distribution -system.membus.trans_dist::ReadResp 214165 # Transaction distribution -system.membus.trans_dist::WriteReq 30915 # Transaction distribution -system.membus.trans_dist::WriteResp 30915 # Transaction distribution -system.membus.trans_dist::WritebackDirty 136162 # Transaction distribution -system.membus.trans_dist::CleanEvict 16178 # Transaction distribution -system.membus.trans_dist::UpgradeReq 65137 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38197 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 39788 # Transaction distribution -system.membus.trans_dist::ReadExResp 19211 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 170083 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 44063 # Transaction distribution +system.membus.trans_dist::ReadResp 214894 # Transaction distribution +system.membus.trans_dist::WriteReq 30895 # Transaction distribution +system.membus.trans_dist::WriteResp 30895 # Transaction distribution +system.membus.trans_dist::WritebackDirty 136975 # Transaction distribution +system.membus.trans_dist::CleanEvict 16276 # Transaction distribution +system.membus.trans_dist::UpgradeReq 64763 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38177 # Transaction distribution +system.membus.trans_dist::UpgradeResp 17 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 39789 # Transaction distribution +system.membus.trans_dist::ReadExResp 19204 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170831 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 645838 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 767530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 769460 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 840469 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842399 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18531148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18721496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18630604 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18820796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21038616 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123440 # Total snoops (count) +system.membus.pkt_size::total 21137916 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123039 # Total snoops (count) system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 424426 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012207 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.109809 # Request fanout histogram +system.membus.snoop_fanout::samples 424743 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012198 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.109769 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 419245 98.78% 98.78% # Request fanout histogram +system.membus.snoop_fanout::0 419562 98.78% 98.78% # Request fanout histogram system.membus.snoop_fanout::1 5181 1.22% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 424426 # Request fanout histogram -system.membus.reqLayer0.occupancy 88263500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 424743 # Request fanout histogram +system.membus.reqLayer0.occupancy 88158500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11456000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11394500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 968117274 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 971210962 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1108847564 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1112716909 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1391627 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1441377 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3047,77 +3050,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1012066 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 538478 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 175231 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 28833 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 27811 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1022 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 44085 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 510917 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30915 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30915 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 359421 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 118152 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 110125 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42801 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 152926 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50897 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50897 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 466834 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4575 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1272193 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 313311 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1585504 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35206412 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5504908 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 40711320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 388372 # Total snoops (count) -system.toL2Bus.snoopTraffic 15694348 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 886366 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.396986 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.491624 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1012483 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 538775 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 174846 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 29019 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 27944 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1075 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 44066 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 511105 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30895 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30895 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 360420 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 118997 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109639 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42707 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 152346 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50919 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50919 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 467041 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4574 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1269868 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316423 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1586291 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35149508 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5612856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 40762364 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 388626 # Total snoops (count) +system.toL2Bus.snoopTraffic 15721036 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 887021 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.395992 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.491535 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 535513 60.42% 60.42% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 349831 39.47% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1022 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 536843 60.52% 60.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 349103 39.36% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1075 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 886366 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 892357874 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 887021 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 892902016 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360373 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360623 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 676996738 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 675868420 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 237913566 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 239041660 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal index 263610058..d38aec98b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal @@ -159,9 +159,9 @@ ata1.00: configured for UDMA/33 scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
sd 0:0:0:0: [sda] Write Protect is off
-sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+sd 0:0:0:0: Attached scsi generic sg0 type 0
sda: sda1
sd 0:0:0:0: [sda] Attached SCSI disk
e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 5d8ec5a8f..731f3d8f9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm +boot_loader=/dist/m5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -49,7 +49,7 @@ panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh +readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -99,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img +image_file=/dist/m5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -157,10 +157,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -174,6 +174,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -186,15 +187,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -254,10 +256,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -271,6 +273,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -283,15 +286,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -386,10 +390,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -403,6 +407,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -415,15 +420,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -503,10 +509,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=50 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 @@ -520,6 +526,7 @@ response_latency=50 sequential_access=false size=1024 system=system +tag_latency=50 tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 @@ -532,15 +539,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=50 default_p_state=UNDEFINED eventq_index=0 -hit_latency=50 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1024 +tag_latency=50 [system.membus] type=CoherentXBar diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 03ec36b9d..acd6681ee 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:01:25 -gem5 executing on e108600-lin, pid 17555 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing +gem5 compiled Nov 29 2016 19:03:48 +gem5 started Nov 29 2016 19:06:57 +gem5 executing on zizzer, pid 5768 +command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 +info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2905297782500 because m5_exit instruction encountered +Exiting @ tick 2905317504500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 954602a38..507baa590 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.905298 # Number of seconds simulated -sim_ticks 2905297782500 # Number of ticks simulated -final_tick 2905297782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.905318 # Number of seconds simulated +sim_ticks 2905317504500 # Number of ticks simulated +final_tick 2905317504500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1078702 # Simulator instruction rate (inst/s) -host_op_rate 1300576 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27866902585 # Simulator tick rate (ticks/s) -host_mem_usage 582552 # Number of bytes of host memory used -host_seconds 104.26 # Real time elapsed on the host -sim_insts 112461365 # Number of instructions simulated -sim_ops 135593151 # Number of ops (including micro ops) simulated +host_inst_rate 372777 # Simulator instruction rate (inst/s) +host_op_rate 449455 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9630563349 # Simulator tick rate (ticks/s) +host_mem_usage 568288 # Number of bytes of host memory used +host_seconds 301.68 # Real time elapsed on the host +sim_insts 112458065 # Number of instructions simulated +sim_ops 135590016 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1184612 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8933156 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8969508 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10119304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1184612 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1184612 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7531136 # Number of bytes written to this memory +system.physmem.bytes_read::total 10157576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7562112 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7548660 # Number of bytes written to this memory +system.physmem.bytes_written::total 7579636 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140668 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 167087 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117674 # Number of write requests responded to by this memory +system.physmem.num_reads::total 167685 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118158 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122055 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122539 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 407742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3074782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 408400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3087273 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3483052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 407742 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407742 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2592208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3496202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 408400 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 408400 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2602852 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6032 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2598240 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2592208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2608884 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2602852 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 407742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3080813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 408400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3093305 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6081292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 167087 # Number of read requests accepted -system.physmem.writeReqs 122055 # Number of write requests accepted -system.physmem.readBursts 167087 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122055 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10685312 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue -system.physmem.bytesWritten 7561344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10119304 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7548660 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6105086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 167685 # Number of read requests accepted +system.physmem.writeReqs 122539 # Number of write requests accepted +system.physmem.readBursts 167685 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122539 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10724096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue +system.physmem.bytesWritten 7592512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10157576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7579636 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9954 # Per bank write bursts -system.physmem.perBankRdBursts::1 9813 # Per bank write bursts -system.physmem.perBankRdBursts::2 10094 # Per bank write bursts -system.physmem.perBankRdBursts::3 9518 # Per bank write bursts -system.physmem.perBankRdBursts::4 18811 # Per bank write bursts -system.physmem.perBankRdBursts::5 10188 # Per bank write bursts -system.physmem.perBankRdBursts::6 10467 # Per bank write bursts -system.physmem.perBankRdBursts::7 10858 # Per bank write bursts -system.physmem.perBankRdBursts::8 9262 # Per bank write bursts -system.physmem.perBankRdBursts::9 10094 # Per bank write bursts -system.physmem.perBankRdBursts::10 9505 # Per bank write bursts -system.physmem.perBankRdBursts::11 9184 # Per bank write bursts -system.physmem.perBankRdBursts::12 9983 # Per bank write bursts -system.physmem.perBankRdBursts::13 9847 # Per bank write bursts -system.physmem.perBankRdBursts::14 9958 # Per bank write bursts -system.physmem.perBankRdBursts::15 9422 # Per bank write bursts -system.physmem.perBankWrBursts::0 7103 # Per bank write bursts -system.physmem.perBankWrBursts::1 7218 # Per bank write bursts -system.physmem.perBankWrBursts::2 7869 # Per bank write bursts -system.physmem.perBankWrBursts::3 7374 # Per bank write bursts -system.physmem.perBankWrBursts::4 7424 # Per bank write bursts -system.physmem.perBankWrBursts::5 7558 # Per bank write bursts -system.physmem.perBankWrBursts::6 7579 # Per bank write bursts -system.physmem.perBankWrBursts::7 7921 # Per bank write bursts -system.physmem.perBankWrBursts::8 6916 # Per bank write bursts -system.physmem.perBankWrBursts::9 7516 # Per bank write bursts -system.physmem.perBankWrBursts::10 7047 # Per bank write bursts -system.physmem.perBankWrBursts::11 7122 # Per bank write bursts -system.physmem.perBankWrBursts::12 7779 # Per bank write bursts -system.physmem.perBankWrBursts::13 7383 # Per bank write bursts -system.physmem.perBankWrBursts::14 7451 # Per bank write bursts -system.physmem.perBankWrBursts::15 6886 # Per bank write bursts +system.physmem.perBankRdBursts::0 9872 # Per bank write bursts +system.physmem.perBankRdBursts::1 9614 # Per bank write bursts +system.physmem.perBankRdBursts::2 9963 # Per bank write bursts +system.physmem.perBankRdBursts::3 9595 # Per bank write bursts +system.physmem.perBankRdBursts::4 18744 # Per bank write bursts +system.physmem.perBankRdBursts::5 9936 # Per bank write bursts +system.physmem.perBankRdBursts::6 10635 # Per bank write bursts +system.physmem.perBankRdBursts::7 11205 # Per bank write bursts +system.physmem.perBankRdBursts::8 9589 # Per bank write bursts +system.physmem.perBankRdBursts::9 10033 # Per bank write bursts +system.physmem.perBankRdBursts::10 9283 # Per bank write bursts +system.physmem.perBankRdBursts::11 8863 # Per bank write bursts +system.physmem.perBankRdBursts::12 10202 # Per bank write bursts +system.physmem.perBankRdBursts::13 10190 # Per bank write bursts +system.physmem.perBankRdBursts::14 10325 # Per bank write bursts +system.physmem.perBankRdBursts::15 9515 # Per bank write bursts +system.physmem.perBankWrBursts::0 7135 # Per bank write bursts +system.physmem.perBankWrBursts::1 7022 # Per bank write bursts +system.physmem.perBankWrBursts::2 7742 # Per bank write bursts +system.physmem.perBankWrBursts::3 7365 # Per bank write bursts +system.physmem.perBankWrBursts::4 7465 # Per bank write bursts +system.physmem.perBankWrBursts::5 7289 # Per bank write bursts +system.physmem.perBankWrBursts::6 7716 # Per bank write bursts +system.physmem.perBankWrBursts::7 8300 # Per bank write bursts +system.physmem.perBankWrBursts::8 7184 # Per bank write bursts +system.physmem.perBankWrBursts::9 7439 # Per bank write bursts +system.physmem.perBankWrBursts::10 6836 # Per bank write bursts +system.physmem.perBankWrBursts::11 6804 # Per bank write bursts +system.physmem.perBankWrBursts::12 7947 # Per bank write bursts +system.physmem.perBankWrBursts::13 7681 # Per bank write bursts +system.physmem.perBankWrBursts::14 7752 # Per bank write bursts +system.physmem.perBankWrBursts::15 6956 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 65 # Number of times write queue was full causing retry -system.physmem.totGap 2905297420500 # Total gap between requests +system.physmem.numWrRetry 62 # Number of times write queue was full causing retry +system.physmem.totGap 2905317142500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157515 # Read request sizes (log2) +system.physmem.readPktSize::6 158113 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117674 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 166128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118158 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 166730 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 263 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -160,178 +160,175 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 57323 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.311882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.988870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.470779 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 20402 35.59% 35.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14531 25.35% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5716 9.97% 70.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3104 5.41% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2370 4.13% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1421 2.48% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1241 2.16% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 946 1.65% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7592 13.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 57323 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5761 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.979865 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 590.542998 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5760 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 129 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.389430 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 186.497805 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.903414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20578 35.66% 35.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14720 25.51% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5637 9.77% 70.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3163 5.48% 76.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2413 4.18% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1394 2.42% 83.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1275 2.21% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 905 1.57% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7625 13.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57710 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5794 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.919917 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 588.859232 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5793 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5761 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5761 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.507898 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.546505 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 15.055833 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5040 87.48% 87.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 23 0.40% 87.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 68 1.18% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 38 0.66% 89.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 294 5.10% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 33 0.57% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.03% 95.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 6 0.10% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.05% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.03% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.09% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 158 2.74% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.10% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.17% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 11 0.19% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.14% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.12% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.07% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5794 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5794 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.475147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.526106 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.995822 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5070 87.50% 87.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 36 0.62% 88.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 58 1.00% 89.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 41 0.71% 89.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 290 5.01% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 32 0.55% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 5 0.09% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.14% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 5 0.09% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.03% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.09% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 158 2.73% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.12% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.09% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 8 0.14% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.09% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 9 0.16% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.16% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.09% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 6 0.10% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.09% 99.79% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.05% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5761 # Writes before turning the bus around for reads -system.physmem.totQLat 4504540500 # Total ticks spent queuing -system.physmem.totMemAccLat 7635003000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 834790000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26980.08 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5794 # Writes before turning the bus around for reads +system.physmem.totQLat 4573778750 # Total ticks spent queuing +system.physmem.totMemAccLat 7715603750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 837820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27295.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45730.08 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.68 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46045.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing -system.physmem.readRowHits 138094 # Number of row buffer hits during reads -system.physmem.writeRowHits 89686 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.90 # Row buffer hit rate for writes -system.physmem.avgGap 10047995.17 # Average gap between requests -system.physmem.pageHitRate 79.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 210115920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 111679260 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 640479420 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 313440120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6609223920.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4735061820 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 414343200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13903412640 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 9310120320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 682719565725 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 718969243965 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.468348 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2893307612500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 778413000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2810438000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2839095824500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 24245244750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7877734000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 30490128250 # Time in different power states -system.physmem_1.actEnergy 199177440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 105861525 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 551600700 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 303282000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6621516720.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4536550200 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 409678080 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13514783790 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 9490661760 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 682993594335 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 718728215280 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.385386 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2894278953000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 777246000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2816412000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2839926040500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 24715420500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7425105000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 29637558500 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing +system.physmem.readRowHits 138574 # Number of row buffer hits during reads +system.physmem.writeRowHits 89912 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.78 # Row buffer hit rate for writes +system.physmem.avgGap 10010602.65 # Average gap between requests +system.physmem.pageHitRate 79.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 209951700 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 111591975 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 639486960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 313377480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6673146480.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4797272190 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 415271520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13955015310 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 9412509120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 682622001540 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 719151899205 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.529538 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2893187374000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 780943500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2837778000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2838595786500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 24511740750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7987774000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 30603481750 # Time in different power states +system.physmem_1.actEnergy 202104840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 107417475 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 556920000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 305886780 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6671302560.000002 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4519380090 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 410434080 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13655969940 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 9525025920 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 682931246265 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 718886718750 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.438264 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2894335381000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 777927000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2837694000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2839583336000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 24804588750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7366436500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 29947522250 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -344,9 +341,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -354,7 +351,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -384,58 +381,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 9547 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9547 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1253 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8294 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9547 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9547 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9547 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7383 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9942.435324 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8397.692517 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6587.109188 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6605 89.46% 89.46% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 773 10.47% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 9553 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9553 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1256 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8297 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9553 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9553 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9553 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7389 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10013.804304 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8464.395211 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6610.536044 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6588 89.16% 89.16% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 796 10.77% 99.93% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7383 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7389 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 1003066500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 1003066500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6177 83.67% 83.67% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1206 16.33% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7383 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9547 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6180 83.64% 83.64% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1209 16.36% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7389 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9553 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9547 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7383 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9553 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7389 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7383 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16930 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7389 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16942 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24520121 # DTB read hits -system.cpu.dtb.read_misses 8133 # DTB read misses -system.cpu.dtb.write_hits 19605715 # DTB write hits -system.cpu.dtb.write_misses 1414 # DTB write misses +system.cpu.dtb.read_hits 24519779 # DTB read hits +system.cpu.dtb.read_misses 8140 # DTB read misses +system.cpu.dtb.write_hits 19605270 # DTB write hits +system.cpu.dtb.write_misses 1413 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4209 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1628 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24528254 # DTB read accesses -system.cpu.dtb.write_accesses 19607129 # DTB write accesses +system.cpu.dtb.read_accesses 24527919 # DTB read accesses +system.cpu.dtb.write_accesses 19606683 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44125836 # DTB hits -system.cpu.dtb.misses 9547 # DTB misses -system.cpu.dtb.accesses 44135383 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44125049 # DTB hits +system.cpu.dtb.misses 9553 # DTB misses +system.cpu.dtb.accesses 44134602 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,7 +462,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 4763 # Table walker walks requested system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate @@ -474,12 +471,12 @@ system.cpu.itb.walker.walkWaitTime::samples 4763 # system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10156.853282 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8221.468352 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7284.204444 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10180.341055 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8232.055098 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7311.468363 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 769 24.74% 83.33% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 516 16.60% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 761 24.49% 83.08% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 524 16.86% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency @@ -496,7 +493,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115559307 # ITB inst hits +system.cpu.itb.inst_hits 115555925 # ITB inst hits system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -513,55 +510,55 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115564070 # ITB inst accesses -system.cpu.itb.hits 115559307 # DTB hits +system.cpu.itb.inst_accesses 115560688 # ITB inst accesses +system.cpu.itb.hits 115555925 # DTB hits system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115564070 # DTB accesses -system.cpu.numPwrStateTransitions 6066 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887205638.526871 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17463817933.974155 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state +system.cpu.itb.accesses 115560688 # DTB accesses +system.cpu.numPwrStateTransitions 6064 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3032 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887473047.745383 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17466686250.192787 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2968 97.89% 97.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499962880972 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 214403080848 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2690894701652 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5810595565 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 499963437276 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3032 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 214499223736 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2690818280764 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5810635009 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.committedInsts 112461365 # Number of instructions committed -system.cpu.committedOps 135593151 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119897812 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11226 # Number of float alu accesses -system.cpu.num_func_calls 9894928 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15231225 # number of instructions that are conditional controls -system.cpu.num_int_insts 119897812 # number of integer instructions -system.cpu.num_fp_insts 11226 # number of float instructions -system.cpu.num_int_register_reads 218061607 # number of times the integer registers were read -system.cpu.num_int_register_writes 82648736 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8514 # number of times the floating registers were read +system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed +system.cpu.committedInsts 112458065 # Number of instructions committed +system.cpu.committedOps 135590016 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119895072 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses +system.cpu.num_func_calls 9894802 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15230859 # number of instructions that are conditional controls +system.cpu.num_int_insts 119895072 # number of integer instructions +system.cpu.num_fp_insts 11290 # number of float instructions +system.cpu.num_int_register_reads 218056824 # number of times the integer registers were read +system.cpu.num_int_register_writes 82647475 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489758493 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51897030 # number of times the CC registers were written -system.cpu.num_mem_refs 45406070 # number of memory refs -system.cpu.num_load_insts 24842315 # Number of load instructions -system.cpu.num_store_insts 20563755 # Number of store instructions -system.cpu.num_idle_cycles 5381789403.302147 # Number of idle cycles -system.cpu.num_busy_cycles 428806161.697852 # Number of busy cycles -system.cpu.not_idle_fraction 0.073797 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.926203 # Percentage of idle cycles -system.cpu.Branches 25920117 # Number of branches fetched +system.cpu.num_cc_register_reads 489748178 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51895154 # number of times the CC registers were written +system.cpu.num_mem_refs 45405351 # number of memory refs +system.cpu.num_load_insts 24842092 # Number of load instructions +system.cpu.num_store_insts 20563259 # Number of store instructions +system.cpu.num_idle_cycles 5381636561.526148 # Number of idle cycles +system.cpu.num_busy_cycles 428998447.473852 # Number of busy cycles +system.cpu.not_idle_fraction 0.073830 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.926170 # Percentage of idle cycles +system.cpu.Branches 25919628 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93182494 67.18% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114558 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93180053 67.18% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114520 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -587,504 +584,504 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8431 0.01% 67.27% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8439 0.01% 67.27% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu.op_class::MemRead 24839607 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20555241 14.82% 99.99% # Class of executed instruction +system.cpu.op_class::MemRead 24839384 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20554681 14.82% 99.99% # Class of executed instruction system.cpu.op_class::FloatMemRead 2708 0.00% 99.99% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 8514 0.01% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 8578 0.01% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138713890 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 821351 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.816254 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43232645 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821863 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.603226 # Average number of references to valid blocks. +system.cpu.op_class::total 138710700 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 821158 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.816175 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43232098 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821670 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.614916 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1078145500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.816254 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.816175 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999641 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177108261 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177108261 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23111024 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23111024 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18823159 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18823159 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392414 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392414 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443071 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443071 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460161 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460161 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41934183 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41934183 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42326597 # number of overall hits -system.cpu.dcache.overall_hits::total 42326597 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 401452 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 401452 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298737 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298737 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118712 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118712 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22861 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22861 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177104923 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177104923 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23110979 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23110979 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18822589 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18822589 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392473 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392473 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443107 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443107 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460141 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460141 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41933568 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41933568 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42326041 # number of overall hits +system.cpu.dcache.overall_hits::total 42326041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 401142 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 401142 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298882 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298882 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118684 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118684 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22807 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22807 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 700189 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 700189 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 818901 # number of overall misses -system.cpu.dcache.overall_misses::total 818901 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6440957000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6440957000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14361709000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14361709000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 300793500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 300793500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 700024 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 700024 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 818708 # number of overall misses +system.cpu.dcache.overall_misses::total 818708 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6437634500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6437634500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14441729500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14441729500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297474000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 297474000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20802666000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20802666000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20802666000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20802666000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23512476 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23512476 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19121896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19121896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511126 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511126 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465932 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465932 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460163 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460163 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42634372 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42634372 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43145498 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43145498 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017074 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017074 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015623 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015623 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232256 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.232256 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.049065 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.049065 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 20879364000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20879364000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20879364000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20879364000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19121471 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19121471 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511157 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511157 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460143 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460143 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42633592 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42633592 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43144749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43144749 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017061 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232187 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.232187 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048951 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016423 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016423 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018980 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018980 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16044.152227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16044.152227 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48074.758065 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48074.758065 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13157.495298 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13157.495298 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016420 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016420 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018976 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018976 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16048.268444 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16048.268444 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48319.167765 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48319.167765 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13043.100802 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13043.100802 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29710.072566 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29710.072566 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25403.151297 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25403.151297 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29826.640229 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29826.640229 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25502.821519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25502.821519 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 685561 # number of writebacks -system.cpu.dcache.writebacks::total 685561 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 705 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14335 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14335 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 705 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 705 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 705 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 705 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400747 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 400747 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298737 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298737 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116693 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 116693 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8526 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 685618 # number of writebacks +system.cpu.dcache.writebacks::total 685618 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 708 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14278 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14278 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 708 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 708 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 708 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 708 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400434 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 400434 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298882 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298882 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116661 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 116661 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8529 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8529 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 699484 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 699484 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 816177 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 816177 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 699316 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 699316 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 815977 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 815977 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14062972000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14062972000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1582474000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1582474000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 120274000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 120274000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6011986000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6011986000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14142847500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14142847500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1587073500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1587073500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118989500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118989500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20078891500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20078891500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21661365500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21661365500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284842500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284842500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284842500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6284842500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228306 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228306 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018299 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018299 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20154833500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20154833500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21741907000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21741907000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284829000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284829000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284829000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6284829000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017031 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017031 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228229 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228229 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018306 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018306 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016407 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016407 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018917 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15011.764280 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15011.764280 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47074.758065 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47074.758065 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13561.001945 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13561.001945 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14106.732348 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14106.732348 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016403 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016403 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018913 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018913 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15013.675162 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15013.675162 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47319.167765 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47319.167765 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13604.147916 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13604.147916 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13951.166608 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13951.166608 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28705.290614 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28705.290614 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26540.034208 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26540.034208 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201838.348642 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201838.348642 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.938938 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.938938 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1700003 # number of replacements -system.cpu.icache.tags.tagsinuse 510.693079 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113858786 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1700515 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.955473 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28820.781306 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28820.781306 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26645.244903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26645.244903 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201837.915088 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201837.915088 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.709061 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.709061 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1700061 # number of replacements +system.cpu.icache.tags.tagsinuse 510.693087 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113855346 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1700573 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 66.951166 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 26307743500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.693079 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.693087 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997447 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997447 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117259828 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117259828 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 113858786 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113858786 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113858786 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113858786 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113858786 # number of overall hits -system.cpu.icache.overall_hits::total 113858786 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1700521 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1700521 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1700521 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1700521 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1700521 # number of overall misses -system.cpu.icache.overall_misses::total 1700521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24021238000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24021238000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24021238000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24021238000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24021238000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24021238000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115559307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115559307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115559307 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115559307 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115559307 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115559307 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014716 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014716 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014716 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014716 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014716 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014716 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14125.810854 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14125.810854 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14125.810854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14125.810854 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117256504 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117256504 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 113855346 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113855346 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113855346 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113855346 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113855346 # number of overall hits +system.cpu.icache.overall_hits::total 113855346 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1700579 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1700579 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1700579 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1700579 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1700579 # number of overall misses +system.cpu.icache.overall_misses::total 1700579 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24045189500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24045189500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24045189500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24045189500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24045189500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24045189500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115555925 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115555925 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115555925 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115555925 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115555925 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115555925 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014717 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014717 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014717 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014717 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014717 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014717 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.413400 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14139.413400 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.413400 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14139.413400 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.413400 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14139.413400 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1700003 # number of writebacks -system.cpu.icache.writebacks::total 1700003 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700521 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1700521 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1700521 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1700521 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1700521 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1700521 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1700061 # number of writebacks +system.cpu.icache.writebacks::total 1700061 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700579 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1700579 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1700579 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1700579 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1700579 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1700579 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22320717000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22320717000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22320717000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22320717000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22320717000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22320717000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22344610500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22344610500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22344610500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22344610500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22344610500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22344610500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 745203000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 745203000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 745203000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 745203000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014716 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014716 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014716 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13125.810854 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13125.810854 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13125.810854 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13125.810854 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13125.810854 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13125.810854 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014717 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014717 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014717 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.413400 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.413400 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.413400 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.413400 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.413400 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.413400 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 88035 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65011.446283 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4854285 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 153426 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 31.639259 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 146352515000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050747 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041160 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9651.725117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55356.629260 # Average occupied blocks per requestor +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 88597 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65011.992500 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4854150 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 154024 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 31.515543 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 147534324000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050681 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041157 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9634.970202 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55373.930460 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000047 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147274 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.844675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.991996 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147018 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.844939 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992004 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65386 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65422 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60952 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4349 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60996 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997711 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40277345 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40277345 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 4991 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2669 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7660 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 685561 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 685561 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1667726 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1667726 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2795 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2795 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 168131 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 168131 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682557 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1682557 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513829 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 513829 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 4991 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2669 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1682557 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 681960 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2372177 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 4991 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2669 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1682557 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 681960 # number of overall hits -system.cpu.l2cache.overall_hits::total 2372177 # number of overall hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998260 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40276407 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40276407 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5063 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2684 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7747 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 685618 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 685618 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1667781 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1667781 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2789 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2789 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 167649 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 167649 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682585 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1682585 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513552 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 513552 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 5063 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2684 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1682585 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 681201 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2371533 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 5063 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2684 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1682585 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 681201 # number of overall hits +system.cpu.l2cache.overall_hits::total 2371533 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 127792 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 127792 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17948 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 17948 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12137 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 12137 # number of ReadSharedReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 128426 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 128426 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17978 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 17978 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12072 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 12072 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 17948 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 139929 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 157886 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 17978 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140498 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 158485 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 17948 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 139929 # number of overall misses -system.cpu.l2cache.overall_misses::total 157886 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 17978 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 140498 # number of overall misses +system.cpu.l2cache.overall_misses::total 158485 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1334500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 555500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 555500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1334000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 525000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 525000 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11816022500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11816022500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2043061500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2043061500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1517166500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1517166500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11900828000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11900828000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066597500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066597500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1519988500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1519988500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 180000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2043061500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13333189000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15377585000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2066597500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13420816500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15488748000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 180000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2043061500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13333189000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15377585000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 4998 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2671 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7669 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 685561 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 685561 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1667726 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1667726 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2814 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2814 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 2066597500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13420816500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15488748000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5070 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2686 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7756 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 685618 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 685618 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1667781 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1667781 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2807 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2807 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 295923 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 295923 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700505 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1700505 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 525966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 4998 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2671 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1700505 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 821889 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530063 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 4998 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2671 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1700505 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 821889 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530063 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001401 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000749 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001174 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006752 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006752 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296075 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296075 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700563 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1700563 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525624 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 525624 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5070 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2686 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1700563 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 821699 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530018 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5070 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2686 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1700563 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 821699 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530018 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000745 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001160 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006413 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006413 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.431842 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.431842 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010555 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010555 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023076 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023076 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001401 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000749 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010555 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.170253 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062404 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001401 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000749 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010555 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.170253 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062404 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164928.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433762 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.433762 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010572 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010572 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.022967 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.022967 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001381 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000745 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010572 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.170985 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062642 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001381 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000745 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010572 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.170985 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062642 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164857.142857 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 90000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 148277.777778 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29236.842105 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29236.842105 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 148222.222222 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29166.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29166.666667 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92462.928039 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92462.928039 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 113832.265433 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 113832.265433 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125003.419296 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125003.419296 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164928.571429 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92666.812016 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92666.812016 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114951.468461 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114951.468461 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125910.246852 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125910.246852 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 113832.265433 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95285.387589 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 97396.760954 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164928.571429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114951.468461 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95523.185383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 97730.056472 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 113832.265433 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95285.387589 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97396.760954 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114951.468461 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95523.185383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 97730.056472 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 81484 # number of writebacks -system.cpu.l2cache.writebacks::total 81484 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 81968 # number of writebacks +system.cpu.l2cache.writebacks::total 81968 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127792 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 127792 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17948 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17948 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12137 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12137 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128426 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 128426 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17978 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17978 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12072 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12072 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 17948 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 139929 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 157886 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 17978 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140498 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 158485 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 17948 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 139929 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 157886 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 17978 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140498 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 158485 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable @@ -1093,145 +1090,145 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 365500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 365500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10538102500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10538102500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1863581500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1863581500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1395796500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1395796500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10616568000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10616568000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886817500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886817500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1399268500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1399268500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1863581500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11933899000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13798725000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886817500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12015836500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13903898000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1863581500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11933899000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13798725000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886817500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12015836500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13903898000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 632428000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895497500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527925500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895484000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527912000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 632428000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5895497500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6527925500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001174 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006752 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006752 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5895484000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6527912000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001160 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006413 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006413 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.431842 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.431842 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010555 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023076 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023076 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062404 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062404 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433762 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433762 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010572 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.022967 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.022967 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170985 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062642 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170985 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062642 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138277.777778 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19236.842105 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19236.842105 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138222.222222 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19166.666667 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82462.928039 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82462.928039 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 103832.265433 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 103832.265433 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115003.419296 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115003.419296 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82666.812016 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82666.812016 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104951.468461 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104951.468461 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115910.246852 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115910.246852 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104951.468461 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85523.185383 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87730.056472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104951.468461 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85523.185383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87730.056472 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.494829 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.945717 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.061276 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.609562 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100388.194527 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.566119 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5065968 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543576 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 219 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 219 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100387.964650 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.366854 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5065624 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543364 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39292 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 222 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 222 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 67217 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2293895 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 67226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2293620 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 767045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1700003 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 142341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 767586 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1700061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 142169 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2807 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700521 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 526163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2809 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296075 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296075 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700579 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 525821 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119073 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2588406 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11887 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22839 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7742205 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217668600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96672157 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10684 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 19992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 314371433 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112178 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5305776 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2712615 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021718 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.145761 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587819 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22920 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7741888 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217676024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96663645 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 314370693 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112662 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5336440 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2713047 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.145674 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2653703 97.83% 97.83% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 58912 2.17% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2654197 97.83% 97.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 58850 2.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2712615 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4970051500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2713047 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4970034000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 347876 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 347377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2559803500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2559890500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1279174000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1278885500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17841000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17850000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30159 # Transaction distribution system.iobus.trans_dist::ReadResp 30159 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1282,7 +1279,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480037 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46336000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1316,32 +1313,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6292000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6289000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187581870 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187558131 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36692000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36400 # number of replacements -system.iocache.tags.tagsinuse 1.079755 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.079865 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36416 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 310620847000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.079755 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067485 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067485 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 310617748000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.079865 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067492 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067492 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327906 # Number of tag accesses system.iocache.tags.data_accesses 327906 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 210 # number of ReadReq misses system.iocache.ReadReq_misses::total 210 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1350,14 +1347,14 @@ system.iocache.demand_misses::realview.ide 36434 # system.iocache.demand_misses::total 36434 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36434 # number of overall misses system.iocache.overall_misses::total 36434 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4367688494 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4367688494 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4401754870 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4401754870 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4401754870 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4401754870 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 34063377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 34063377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4369997754 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4369997754 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4404061131 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4404061131 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4404061131 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4404061131 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 210 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 210 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1374,19 +1371,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120574.439432 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120574.439432 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120814.482901 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120814.482901 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 162206.557143 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162206.557143 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120638.188880 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120638.188880 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120877.782593 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120877.782593 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120877.782593 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120877.782593 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -1398,14 +1395,14 @@ system.iocache.demand_mshr_misses::realview.ide 36434 system.iocache.demand_mshr_misses::total 36434 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36434 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36434 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2554457612 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2554457612 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2578023988 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2578023988 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2578023988 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2578023988 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 23563377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 23563377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2556779983 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2556779983 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2580343360 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2580343360 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2580343360 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2580343360 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1414,90 +1411,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70518.374890 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70518.374890 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 318841 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 128997 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112206.557143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112206.557143 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70582.486280 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70582.486280 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70822.401054 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70822.401054 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70822.401054 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70822.401054 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 319998 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 129556 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70464 # Transaction distribution +system.membus.trans_dist::ReadResp 70429 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117674 # Transaction distribution -system.membus.trans_dist::CleanEvict 6761 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118158 # Transaction distribution +system.membus.trans_dist::CleanEvict 6839 # Transaction distribution system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 127683 # Transaction distribution -system.membus.trans_dist::ReadExResp 127683 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30304 # Transaction distribution +system.membus.trans_dist::ReadExReq 128316 # Transaction distribution +system.membus.trans_dist::ReadExResp 128316 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30269 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431348 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 538940 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540698 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 611789 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 613547 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15350844 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15514197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583445 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17831317 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17900565 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 474 # Total snoops (count) system.membus.snoopTraffic 30208 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 262090 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018417 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.134455 # Request fanout histogram +system.membus.snoop_fanout::samples 262688 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018375 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134305 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 257263 98.16% 98.16% # Request fanout histogram +system.membus.snoop_fanout::0 257861 98.16% 98.16% # Request fanout histogram system.membus.snoop_fanout::1 4827 1.84% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 262090 # Request fanout histogram -system.membus.reqLayer0.occupancy 90471500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 262688 # Request fanout histogram +system.membus.reqLayer0.occupancy 90466500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1726500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1724500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 819732726 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 822811335 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 945419750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 948647750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1085624 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1085623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1529,28 +1526,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |