diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref')
20 files changed, 0 insertions, 10765 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini deleted file mode 100644 index 55e1410b6..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ /dev/null @@ -1,1442 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges=0:134217727 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu0.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu0.tracer -width=1 -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - -[system.cpu0.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu0.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu0.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu1.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu1.interrupts -isa=system.cpu1.isa -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu1.tracer -width=1 -workload= -dcache_port=system.cpu1.dcache.cpu_side -icache_port=system.cpu1.icache.cpu_side - -[system.cpu1.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[3] - -[system.cpu1.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu1.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[2] - -[system.cpu1.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu1.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu1.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu0 -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr deleted file mode 100755 index 25e6a47e4..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout deleted file mode 100755 index a53acdd5f..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ /dev/null @@ -1,16 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:26 -gem5 executing on e108600-lin, pid 39599 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 97861500 -Exiting @ tick 1869357999000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt deleted file mode 100644 index 54bff4f85..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ /dev/null @@ -1,1010 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869358054000 # Number of ticks simulated -final_tick 1869358054000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2951277 # Simulator instruction rate (inst/s) -host_op_rate 2951276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84876880961 # Simulator tick rate (ticks/s) -host_mem_usage 336132 # Number of bytes of host memory used -host_seconds 22.02 # Real time elapsed on the host -sim_insts 64999904 # Number of instructions simulated -sim_ops 64999904 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66535744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 766400 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68167488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 106112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7837888 # Number of bytes written to this memory -system.physmem.bytes_written::total 7837888 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1039621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11975 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065117 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122467 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122467 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35592830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 409980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36465720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4192823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4192823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4192823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35592830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 409980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40658544 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7758808 # DTB read hits -system.cpu0.dtb.read_misses 7155 # DTB read misses -system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_accesses 531148 # DTB read accesses -system.cpu0.dtb.write_hits 4740251 # DTB write hits -system.cpu0.dtb.write_misses 732 # DTB write misses -system.cpu0.dtb.write_acv 102 # DTB write access violations -system.cpu0.dtb.write_accesses 201714 # DTB write accesses -system.cpu0.dtb.data_hits 12499059 # DTB hits -system.cpu0.dtb.data_misses 7887 # DTB misses -system.cpu0.dtb.data_acv 254 # DTB access violations -system.cpu0.dtb.data_accesses 732862 # DTB accesses -system.cpu0.itb.fetch_hits 3525726 # ITB hits -system.cpu0.itb.fetch_misses 3572 # ITB misses -system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3529298 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 271506712.952752 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 434955679.637595 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 21000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 24741446199 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616607801 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3738722903 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222787000 99.14% 99.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869357846500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed -system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed -system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed -system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed -system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 135929 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1172 -system.cpu0.kern.mode_good::user 1173 -system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349218500 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2744 # number of times the context was actually changed -system.cpu0.committedInsts 49477745 # Number of instructions committed -system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124633 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46201705 # number of integer instructions -system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536107 # number of memory refs -system.cpu0.num_load_insts 7783754 # Number of load instructions -system.cpu0.num_store_insts 4752353 # Number of store instructions -system.cpu0.num_idle_cycles 3689239920.666412 # Number of idle cycles -system.cpu0.num_busy_cycles 49482982.333588 # Number of busy cycles -system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530826 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction -system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7859946 15.88% 88.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 4676411 9.45% 98.30% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 85644 0.17% 98.47% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 81881 0.17% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49485886 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1781367 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187332 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187332 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4360096 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4360096 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132871 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 132871 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10428981 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10428981 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10428981 # number of overall hits -system.cpu0.dcache.overall_hits::total 10428981 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 236527 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 236527 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6899 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 6899 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796592 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796592 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796592 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796592 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051457 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051457 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049360 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049360 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 633925 # number of writebacks -system.cpu0.dcache.writebacks::total 633925 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 618292 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits -system.cpu0.icache.overall_hits::total 48866947 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses -system.cpu0.icache.overall_misses::total 618939 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 618292 # number of writebacks -system.cpu0.icache.writebacks::total 618292 # number of writebacks -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2831559 # DTB read hits -system.cpu1.dtb.read_misses 3191 # DTB read misses -system.cpu1.dtb.read_acv 58 # DTB read access violations -system.cpu1.dtb.read_accesses 198160 # DTB read accesses -system.cpu1.dtb.write_hits 2101673 # DTB write hits -system.cpu1.dtb.write_misses 412 # DTB write misses -system.cpu1.dtb.write_acv 55 # DTB write access violations -system.cpu1.dtb.write_accesses 90619 # DTB write accesses -system.cpu1.dtb.data_hits 4933232 # DTB hits -system.cpu1.dtb.data_misses 3603 # DTB misses -system.cpu1.dtb.data_acv 113 # DTB access violations -system.cpu1.dtb.data_accesses 288779 # DTB accesses -system.cpu1.itb.fetch_hits 1950883 # ITB hits -system.cpu1.itb.fetch_misses 1451 # ITB misses -system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1952334 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5407 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2704 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 688459953.587278 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 437290552.872181 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2704 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 976035500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2704 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 7762339500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595714500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3738296719 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856123556500 99.30% 99.30% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869146994500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed -system.cpu1.kern.callpal::tbi 14 0.02% 3.59% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.60% # number of callpals executed -system.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed -system.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.00% 94.91% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.92% # number of callpals executed -system.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed -system.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed -system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 84542 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2548 # number of protection mode switches -system.cpu1.kern.mode_switch::user 564 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 1106 -system.cpu1.kern.mode_good::user 564 -system.cpu1.kern.mode_good::idle 542 -system.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102446500 99.66% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2507 # number of times the context was actually changed -system.cpu1.committedInsts 15522159 # Number of instructions committed -system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses -system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295544 # number of integer instructions -system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961786 # number of memory refs -system.cpu1.num_load_insts 2849090 # Number of load instructions -system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722773781.474732 # Number of idle cycles -system.cpu1.num_busy_cycles 15522937.525268 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214163 # Number of branches fetched -system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction -system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction -system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2842559 18.31% 83.05% # Class of executed instruction -system.cpu1.op_class::MemWrite 2023248 13.03% 96.08% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 94457 0.61% 96.69% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 90649 0.58% 97.27% # Class of executed instruction -system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525875 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 201757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.601957 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601957 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1954647 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1954647 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64211 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 64211 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4587335 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4587335 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4587335 # number of overall hits -system.cpu1.dcache.overall_hits::total 4587335 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 78313 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 78313 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7304 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 7304 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 219198 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 219198 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 219198 # number of overall misses -system.cpu1.dcache.overall_misses::total 219198 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038522 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.038522 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102132 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102132 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045604 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.045604 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.045604 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.045604 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 144832 # number of writebacks -system.cpu1.dcache.writebacks::total 144832 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 380647 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.133721 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859777228500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133721 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits -system.cpu1.icache.overall_hits::total 15144687 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses -system.cpu1.icache.overall_misses::total 381188 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 380647 # number of writebacks -system.cpu1.icache.writebacks::total 380647 # number of writebacks -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7628 # Transaction distribution -system.iobus.trans_dist::ReadResp 7628 # Transaction distribution -system.iobus.trans_dist::WriteReq 56140 # Transaction distribution -system.iobus.trans_dist::WriteResp 56140 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787164517 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375579 # Number of tag accesses -system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses -system.iocache.ReadReq_misses::total 179 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses -system.iocache.demand_misses::total 41731 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses -system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 999962 # number of replacements -system.l2c.tags.tagsinuse 65520.418445 # Cycle average of tags in use -system.l2c.tags.total_refs 4560627 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1065470 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.280390 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 304.654012 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4865.757484 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58473.870624 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.171542 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1700.964784 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074246 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.892240 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.025955 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.999762 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65508 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 674 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2411 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2462 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9328 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50633 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999573 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46077150 # Number of tag accesses -system.l2c.tags.data_accesses 46077150 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 778757 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 778757 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 721479 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 721479 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3102 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2744 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5846 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1187 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1121 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2308 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111978 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56627 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168605 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626251 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 128790 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755041 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185417 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910246 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits -system.l2c.overall_hits::cpu0.data 738229 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits -system.l2c.overall_hits::cpu1.data 185417 # number of overall hits -system.l2c.overall_hits::total 1910246 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 4 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113307 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11044 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124351 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1658 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13506 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 926616 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1036 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 927652 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1039923 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1658 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12080 # number of demand (read+write) misses -system.l2c.demand_misses::total 1065509 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses -system.l2c.overall_misses::cpu0.data 1039923 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses -system.l2c.overall_misses::cpu1.data 12080 # number of overall misses -system.l2c.overall_misses::total 1065509 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 778757 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 778757 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 721479 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 721479 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3106 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2746 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5852 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1187 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1122 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225285 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292956 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1552867 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 129826 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1682693 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778152 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197497 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2975755 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778152 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197497 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2975755 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001288 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000728 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.001025 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.000891 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.000433 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.502950 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.163201 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.424470 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596713 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007980 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551290 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584834 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061165 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358063 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584834 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061165 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358063 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 80947 # number of writebacks -system.l2c.writebacks::total 80947 # number of writebacks -system.membus.snoop_filter.tot_requests 2174394 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1068314 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 544 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948786 # Transaction distribution -system.membus.trans_dist::WriteReq 14588 # Transaction distribution -system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122467 # Transaction distribution -system.membus.trans_dist::CleanEvict 918018 # Transaction distribution -system.membus.trans_dist::UpgradeReq 13880 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11895 # Transaction distribution -system.membus.trans_dist::UpgradeResp 135 # Transaction distribution -system.membus.trans_dist::ReadExReq 125245 # Transaction distribution -system.membus.trans_dist::ReadExResp 124223 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941337 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3156480 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3200554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3325715 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73364992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73451154 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76119890 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2196431 # Request fanout histogram -system.membus.snoop_fanout::mean 0.000560 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.023658 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2195201 99.94% 99.94% # Request fanout histogram -system.membus.snoop_fanout::1 1230 0.06% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2196431 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 6035809 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3010644 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 386637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1627 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1537 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 778757 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1204367 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 19598 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14203 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 33801 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450061 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9133629 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155817595 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23377367 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 307135186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1001076 # Total snoops (count) -system.toL2Bus.snoopTraffic 5203008 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7058756 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.107956 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.310579 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6297275 89.21% 89.21% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 760929 10.78% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 550 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7058756 # Request fanout histogram -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal deleted file mode 100644 index 6129834bd..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal +++ /dev/null @@ -1,112 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 -
Got Configuration 623 -
memsize 8000000 pages 4000 -
First free page after ROM 0xFFFFFC0000018000 -
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 -
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 -
CPU Clock at 2000 MHz IntrClockFrequency=1024 -
Booting with 2 processor(s) -
KSP: 0x20043FE8 PTBR 0x20 -
KSP: 0x20043FE8 PTBR 0x20 -
Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 -
Memory cluster 0 [0 - 392] -
Memory cluster 1 [392 - 15992] -
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 -
ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 -
Bootstraping CPU 1 with sp=0xFFFFFC0000076000 -
unix_boot_mem ends at FFFFFC0000078000 -
k_argc = 0 -
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) -
CallbackFixup 0 18000, t7=FFFFFC000070C000 -
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 -
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 -
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM -
Major Options: SMP LEGACY_START VERBOSE_MCHECK -
Command line: root=/dev/hda1 console=ttyS0 -
memcluster 0, usage 1, start 0, end 392 -
memcluster 1, usage 0, start 392, end 16384 -
freeing pages 1069:16384 -
reserving pages 1069:1070 -
SMP: 2 CPUs probed -- cpu_present_mask = 3 -
Built 1 zonelists -
Kernel command line: root=/dev/hda1 console=ttyS0 -
PID hash table entries: 1024 (order: 10, 32768 bytes) -
Using epoch = 1900 -
Console: colour dummy device 80x25 -
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) -
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) -
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) -
Mount-cache hash table entries: 512 -
SMP starting up secondaries. -
Slave CPU 1 console command START
-SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 -
Brought up 2 CPUs -
SMP: Total of 2 processors activated (8000.15 BogoMIPS). -
NET: Registered protocol family 16 -
EISA bus registered -
pci: enabling save/restore of SRM state -
SCSI subsystem initialized -
srm_env: version 0.0.5 loaded successfully -
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). -
Initializing Cryptographic API -
rtc: Standard PC (1900) epoch (1900) detected -
Real Time Clock Driver v1.12 -
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled -
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 -
io scheduler noop registered -
io scheduler anticipatory registered -
io scheduler deadline registered -
io scheduler cfq registered -
loop: loaded (max 8 devices) -
nbd: registered device at major 43 -
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. -
PCI: Setting latency timer of device 0000:00:01.0 to 64 -
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 -
eth0: enabling optical transceiver -
eth0: using 64 bit addressing. -
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg -
tun: Universal TUN/TAP device driver, 1.6 -
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> -
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 -
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -
PIIX4: IDE controller at PCI slot 0000:00:00.0 -
PIIX4: chipset revision 0 -
PIIX4: 100% native mode on irq 31 -
PCI: Setting latency timer of device 0000:00:00.0 to 64 -
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA -
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA -
hda: M5 IDE Disk, ATA DISK drive -
hdb: M5 IDE Disk, ATA DISK drive -
ide0 at 0x8410-0x8417,0x8422 on irq 31 -
hda: max request size: 128KiB -
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) -
hda: cache flushes not supported -
hda: hda1 -
hdb: max request size: 128KiB -
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) -
hdb: cache flushes not supported -
hdb: unknown partition table -
mice: PS/2 mouse device common for all mice -
NET: Registered protocol family 2 -
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) -
TCP established hash table entries: 16384 (order: 5, 262144 bytes) -
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) -
TCP: Hash tables configured (established 16384 bind 16384) -
TCP reno registered -
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack -
ip_tables: (C) 2000-2002 Netfilter core team -
arp_tables: (C) 2002 David S. Miller -
TCP bic registered -
Initializing IPsec netlink socket -
NET: Registered protocol family 1 -
NET: Registered protocol family 17 -
NET: Registered protocol family 15 -
Bridge firewalling registered -
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> -
All bugs added by David S. Miller <davem@redhat.com> -
VFS: Mounted root (ext2 filesystem) readonly. -
Freeing unused kernel memory: 224k freed -
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script...
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini deleted file mode 100644 index 4ec6fe954..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ /dev/null @@ -1,1278 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges=0:134217727 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr deleted file mode 100755 index 8aa036613..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout deleted file mode 100755 index 9ca182ddf..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:27 -gem5 executing on e108600-lin, pid 39612 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1829331993500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt deleted file mode 100644 index 50044fb27..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ /dev/null @@ -1,656 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332014500 # Number of ticks simulated -final_tick 1829332014500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3082632 # Simulator instruction rate (inst/s) -host_op_rate 3082630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93925630949 # Simulator tick rate (ticks/s) -host_mem_usage 334080 # Number of bytes of host memory used -host_seconds 19.48 # Real time elapsed on the host -sim_insts 60038469 # Number of instructions simulated -sim_ops 60038469 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory -system.physmem.bytes_written::total 7415744 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36535233 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36535233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710423 # DTB read hits -system.cpu.dtb.read_misses 10329 # DTB read misses -system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352496 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062919 # DTB hits -system.cpu.dtb.data_misses 11471 # DTB misses -system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974637 # ITB hits -system.cpu.itb.fetch_misses 5006 # ITB misses -system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979643 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12714 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 283043478.877143 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 441371901.217911 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307395222 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3658670387 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811929148500 99.05% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829331807000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed -system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192179 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1737 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801033420500 98.45% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.committedInsts 60038469 # Number of instructions committed -system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913692 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115703 # number of memory refs -system.cpu.num_load_insts 9747509 # Number of load instructions -system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621044.088899 # Number of idle cycles -system.cpu.num_busy_cycles 60049342.911101 # Number of busy cycles -system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983587 # Percentage of idle cycles -system.cpu.Branches 9064428 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction -system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9830448 16.37% 87.56% # Class of executed instruction -system.cpu.op_class::MemWrite 6236007 10.38% 97.95% # Class of executed instruction -system.cpu.op_class::FloatMemRead 144629 0.24% 98.19% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 138108 0.23% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050307 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2042708 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038419 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043220 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870733 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369781 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369781 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848209 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848209 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655980 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655980 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655980 # number of overall hits -system.cpu.dcache.overall_hits::total 13655980 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses -system.cpu.dcache.overall_misses::total 2026075 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 833476 # number of writebacks -system.cpu.dcache.writebacks::total 833476 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 919605 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59130075 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.263648 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970539 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970539 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 59130075 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59130075 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59130075 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59130075 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59130075 # number of overall hits -system.cpu.icache.overall_hits::total 59130075 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses -system.cpu.icache.overall_misses::total 920232 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 919605 # number of writebacks -system.cpu.icache.writebacks::total 919605 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 992419 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65520.104764 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4865571 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057941 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.599095 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 264.552906 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4852.732204 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819654 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004037 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074047 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.921674 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 606 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3042 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6629 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55077 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48449706 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48449706 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 833476 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 833476 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187293 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187293 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998523 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905448 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998523 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905448 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117054 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117054 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044698 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1057987 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044698 # number of overall misses -system.cpu.l2cache.overall_misses::total 1057987 # number of overall misses -system.cpu.l2cache.WritebackDirty_accesses::writebacks 833476 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 833476 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963435 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963435 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384607 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384607 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357014 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357014 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks -system.cpu.l2cache.writebacks::total 74359 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 5925782 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962349 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2666290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 833476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 919605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304347 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304347 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163226 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8923295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154734 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 301904302 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 993442 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4779456 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6936088 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000848 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.029106 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6930207 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5881 0.08% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6936088 # Request fanout histogram -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7358 # Transaction distribution -system.iobus.trans_dist::ReadResp 7358 # Transaction distribution -system.iobus.trans_dist::WriteReq 51390 # Transaction distribution -system.iobus.trans_dist::WriteResp 51390 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685780588017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks -system.membus.snoop_filter.tot_requests 2132776 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1034104 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7184 # Transaction distribution -system.membus.trans_dist::ReadResp 948291 # Transaction distribution -system.membus.trans_dist::WriteReq 9838 # Transaction distribution -system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution -system.membus.trans_dist::CleanEvict 917188 # Transaction distribution -system.membus.trans_dist::UpgradeReq 133 # Transaction distribution -system.membus.trans_dist::UpgradeResp 133 # Transaction distribution -system.membus.trans_dist::ReadExReq 116925 # Transaction distribution -system.membus.trans_dist::ReadExResp 116925 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107355 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141399 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3266537 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2149798 # Request fanout histogram -system.membus.snoop_fanout::mean 0.000529 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.023002 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2148660 99.95% 99.95% # Request fanout histogram -system.membus.snoop_fanout::1 1138 0.05% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2149798 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal deleted file mode 100644 index f17158b67..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal +++ /dev/null @@ -1,107 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 -
Got Configuration 623 -
memsize 8000000 pages 4000 -
First free page after ROM 0xFFFFFC0000018000 -
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 -
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 -
CPU Clock at 2000 MHz IntrClockFrequency=1024 -
Booting with 1 processor(s) -
KSP: 0x20043FE8 PTBR 0x20 -
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 -
Memory cluster 0 [0 - 392] -
Memory cluster 1 [392 - 15992] -
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 -
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 -
unix_boot_mem ends at FFFFFC0000076000 -
k_argc = 0 -
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) -
CallbackFixup 0 18000, t7=FFFFFC000070C000 -
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 -
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM -
Major Options: SMP LEGACY_START VERBOSE_MCHECK -
Command line: root=/dev/hda1 console=ttyS0 -
memcluster 0, usage 1, start 0, end 392 -
memcluster 1, usage 0, start 392, end 16384 -
freeing pages 1069:16384 -
reserving pages 1069:1070 -
SMP: 1 CPUs probed -- cpu_present_mask = 1 -
Built 1 zonelists -
Kernel command line: root=/dev/hda1 console=ttyS0 -
PID hash table entries: 1024 (order: 10, 32768 bytes) -
Using epoch = 1900 -
Console: colour dummy device 80x25 -
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) -
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) -
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) -
Mount-cache hash table entries: 512 -
SMP mode deactivated. -
Brought up 1 CPUs -
SMP: Total of 1 processors activated (4002.20 BogoMIPS). -
NET: Registered protocol family 16 -
EISA bus registered -
pci: enabling save/restore of SRM state -
SCSI subsystem initialized -
srm_env: version 0.0.5 loaded successfully -
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). -
Initializing Cryptographic API -
rtc: Standard PC (1900) epoch (1900) detected -
Real Time Clock Driver v1.12 -
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled -
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 -
io scheduler noop registered -
io scheduler anticipatory registered -
io scheduler deadline registered -
io scheduler cfq registered -
loop: loaded (max 8 devices) -
nbd: registered device at major 43 -
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. -
PCI: Setting latency timer of device 0000:00:01.0 to 64 -
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 -
eth0: enabling optical transceiver -
eth0: using 64 bit addressing. -
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg -
tun: Universal TUN/TAP device driver, 1.6 -
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> -
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 -
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -
PIIX4: IDE controller at PCI slot 0000:00:00.0 -
PIIX4: chipset revision 0 -
PIIX4: 100% native mode on irq 31 -
PCI: Setting latency timer of device 0000:00:00.0 to 64 -
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA -
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA -
hda: M5 IDE Disk, ATA DISK drive -
hdb: M5 IDE Disk, ATA DISK drive -
ide0 at 0x8410-0x8417,0x8422 on irq 31 -
hda: max request size: 128KiB -
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) -
hda: cache flushes not supported -
hda: hda1 -
hdb: max request size: 128KiB -
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) -
hdb: cache flushes not supported -
hdb: unknown partition table -
mice: PS/2 mouse device common for all mice -
NET: Registered protocol family 2 -
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) -
TCP established hash table entries: 16384 (order: 5, 262144 bytes) -
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) -
TCP: Hash tables configured (established 16384 bind 16384) -
TCP reno registered -
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack -
ip_tables: (C) 2000-2002 Netfilter core team -
arp_tables: (C) 2002 David S. Miller -
TCP bic registered -
Initializing IPsec netlink socket -
NET: Registered protocol family 1 -
NET: Registered protocol family 17 -
NET: Registered protocol family 15 -
Bridge firewalling registered -
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> -
All bugs added by David S. Miller <davem@redhat.com> -
VFS: Mounted root (ext2 filesystem) readonly. -
Freeing unused kernel memory: 224k freed -
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script...
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini deleted file mode 100644 index 7dde96a20..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ /dev/null @@ -1,1499 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:134217727:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615:0:0:0:0 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu0.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu0.tracer -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - -[system.cpu0.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu0.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu0.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu1.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu1.interrupts -isa=system.cpu1.isa -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu1.tracer -workload= -dcache_port=system.cpu1.dcache.cpu_side -icache_port=system.cpu1.icache.cpu_side - -[system.cpu1.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[3] - -[system.cpu1.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu1.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[2] - -[system.cpu1.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu1.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu1.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu0 -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr deleted file mode 100755 index 9acbae09f..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout deleted file mode 100755 index d5fb9a1a9..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ /dev/null @@ -1,16 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28056 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 752919000 -Exiting @ tick 1966741627000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt deleted file mode 100644 index 5f20e9468..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ /dev/null @@ -1,1782 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.966742 # Number of seconds simulated -sim_ticks 1966742176000 # Number of ticks simulated -final_tick 1966742176000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1742915 # Simulator instruction rate (inst/s) -host_op_rate 1742915 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56229643103 # Simulator tick rate (ticks/s) -host_mem_usage 335876 # Number of bytes of host memory used -host_seconds 34.98 # Real time elapsed on the host -sim_insts 60961842 # Number of instructions simulated -sim_ops 60961842 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 796800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24828736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 62272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 430784 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26119552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 796800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 62272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 859072 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7774400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7774400 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6731 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408118 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121475 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121475 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 405137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12624296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 31663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 219034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13280618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 405137 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 31663 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 436800 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3952933 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3952933 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3952933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 405137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12624296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 31663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 219034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17233551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408118 # Number of read requests accepted -system.physmem.writeReqs 121475 # Number of write requests accepted -system.physmem.readBursts 408118 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121475 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26112384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 7772672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26119552 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7774400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25299 # Per bank write bursts -system.physmem.perBankRdBursts::1 25599 # Per bank write bursts -system.physmem.perBankRdBursts::2 25910 # Per bank write bursts -system.physmem.perBankRdBursts::3 25657 # Per bank write bursts -system.physmem.perBankRdBursts::4 25586 # Per bank write bursts -system.physmem.perBankRdBursts::5 25177 # Per bank write bursts -system.physmem.perBankRdBursts::6 26012 # Per bank write bursts -system.physmem.perBankRdBursts::7 25110 # Per bank write bursts -system.physmem.perBankRdBursts::8 25002 # Per bank write bursts -system.physmem.perBankRdBursts::9 25326 # Per bank write bursts -system.physmem.perBankRdBursts::10 25349 # Per bank write bursts -system.physmem.perBankRdBursts::11 25350 # Per bank write bursts -system.physmem.perBankRdBursts::12 25737 # Per bank write bursts -system.physmem.perBankRdBursts::13 25386 # Per bank write bursts -system.physmem.perBankRdBursts::14 25673 # Per bank write bursts -system.physmem.perBankRdBursts::15 25833 # Per bank write bursts -system.physmem.perBankWrBursts::0 7888 # Per bank write bursts -system.physmem.perBankWrBursts::1 7973 # Per bank write bursts -system.physmem.perBankWrBursts::2 7891 # Per bank write bursts -system.physmem.perBankWrBursts::3 7697 # Per bank write bursts -system.physmem.perBankWrBursts::4 7528 # Per bank write bursts -system.physmem.perBankWrBursts::5 7375 # Per bank write bursts -system.physmem.perBankWrBursts::6 8079 # Per bank write bursts -system.physmem.perBankWrBursts::7 7030 # Per bank write bursts -system.physmem.perBankWrBursts::8 7056 # Per bank write bursts -system.physmem.perBankWrBursts::9 7058 # Per bank write bursts -system.physmem.perBankWrBursts::10 7244 # Per bank write bursts -system.physmem.perBankWrBursts::11 7671 # Per bank write bursts -system.physmem.perBankWrBursts::12 7657 # Per bank write bursts -system.physmem.perBankWrBursts::13 7545 # Per bank write bursts -system.physmem.perBankWrBursts::14 7813 # Per bank write bursts -system.physmem.perBankWrBursts::15 7943 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 71 # Number of times write queue was full causing retry -system.physmem.totGap 1966734882500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408118 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121475 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 513.433277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 309.806046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.661980 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15519 23.51% 23.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12333 18.69% 42.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4691 7.11% 49.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3281 4.97% 54.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3296 4.99% 59.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1531 2.32% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1650 2.50% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1071 1.62% 65.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22625 34.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65997 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5403 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.512863 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2871.806103 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5400 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5403 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5403 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.477883 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.790649 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.259878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4886 90.43% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 27 0.50% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 174 3.22% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 7 0.13% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 18 0.33% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 10 0.19% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 26 0.48% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.11% 95.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 152 2.81% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 23 0.43% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 4 0.07% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 7 0.13% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 10 0.19% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.11% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5403 # Writes before turning the bus around for reads -system.physmem.totQLat 6253232750 # Total ticks spent queuing -system.physmem.totMemAccLat 13903345250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2040030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15326.33 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34076.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.13 # Data bus utilization in percentage -system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing -system.physmem.readRowHits 365871 # Number of row buffer hits during reads -system.physmem.writeRowHits 97586 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes -system.physmem.avgGap 3713672.35 # Average gap between requests -system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 236455380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125679015 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5647926960.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5154923820 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 376838880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13418648160 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6443555040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 458974810065 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 492161345970 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.241923 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1954449369000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 631981750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2402382000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1908243357500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16780134250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9257305750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 29427014750 # Time in different power states -system.physmem_1.actEnergy 234763200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 124779600 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1454103840 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313132140 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5778230640.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5151828720 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 364649760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13829543490 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6726228480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 458595076560 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 492575015880 # Total energy per rank (pJ) -system.physmem_1.averagePower 250.452256 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1954420956750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 598934250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2457676000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1906644575500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17516296750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9196775500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 30327918000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7479524 # DTB read hits -system.cpu0.dtb.read_misses 7764 # DTB read misses -system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524068 # DTB read accesses -system.cpu0.dtb.write_hits 5079926 # DTB write hits -system.cpu0.dtb.write_misses 909 # DTB write misses -system.cpu0.dtb.write_acv 133 # DTB write access violations -system.cpu0.dtb.write_accesses 202594 # DTB write accesses -system.cpu0.dtb.data_hits 12559450 # DTB hits -system.cpu0.dtb.data_misses 8673 # DTB misses -system.cpu0.dtb.data_acv 343 # DTB access violations -system.cpu0.dtb.data_accesses 726662 # DTB accesses -system.cpu0.itb.fetch_hits 3638587 # ITB hits -system.cpu0.itb.fetch_misses 3984 # ITB misses -system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3642571 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13586 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 272328046.518475 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 432907003.390448 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 169000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 116817756000 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849924420000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3933484352 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 163848 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56217 40.17% 40.17% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139951 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55705 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55272 48.69% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113516 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903162232500 96.77% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93267000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 789745000 0.04% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 321096500 0.02% 96.83% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 62375109000 3.17% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1966741450000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990892 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680732 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811112 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3063 2.07% 2.43% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132999 89.79% 92.25% # number of callpals executed -system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed -system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 148123 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6987 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 -system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195935 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327749 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1962822047500 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3919400500 0.20% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3064 # number of times the context was actually changed -system.cpu0.committedInsts 47693300 # Number of instructions committed -system.cpu0.committedOps 47693300 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44245928 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210005 # Number of float alu accesses -system.cpu0.num_func_calls 1191022 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5607802 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44245928 # number of integer instructions -system.cpu0.num_fp_insts 210005 # number of float instructions -system.cpu0.num_int_register_reads 60860766 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32957591 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102620 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104398 # number of times the floating registers were written -system.cpu0.num_mem_refs 12600240 # number of memory refs -system.cpu0.num_load_insts 7507148 # Number of load instructions -system.cpu0.num_store_insts 5093092 # Number of store instructions -system.cpu0.num_idle_cycles 3699848839.998118 # Number of idle cycles -system.cpu0.num_busy_cycles 233635512.001881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059397 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940603 # Percentage of idle cycles -system.cpu0.Branches 7183589 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2715591 5.69% 5.69% # Class of executed instruction -system.cpu0.op_class::IntAlu 31389831 65.80% 71.50% # Class of executed instruction -system.cpu0.op_class::IntMult 52060 0.11% 71.61% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26674 0.06% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.67% # Class of executed instruction -system.cpu0.op_class::MemRead 7588720 15.91% 87.57% # Class of executed instruction -system.cpu0.op_class::MemWrite 5010315 10.50% 98.08% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 92556 0.19% 98.27% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 88892 0.19% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 735794 1.54% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47702316 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1183155 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.237754 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11370167 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1183667 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.605883 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.237754 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986792 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986792 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51474763 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51474763 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6401125 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6401125 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4669512 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4669512 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146310 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 146310 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11070637 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11070637 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11070637 # number of overall hits -system.cpu0.dcache.overall_hits::total 11070637 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 938392 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 938392 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 255335 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 255335 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13590 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13590 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1193727 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1193727 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1193727 # number of overall misses -system.cpu0.dcache.overall_misses::total 1193727 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31214419000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 31214419000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12662507500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12662507500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31952500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 31952500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 43876926500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 43876926500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 43876926500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 43876926500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339517 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7339517 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924847 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4924847 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152584 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 152584 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152038 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 152038 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12264364 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12264364 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12264364 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12264364 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127855 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127855 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051846 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051846 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089066 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089066 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097333 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097333 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097333 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097333 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.730935 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.730935 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49591.742221 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 49591.742221 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11064.606328 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11064.606328 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.299581 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.299581 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36756.248707 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36756.248707 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 681263 # number of writebacks -system.cpu0.dcache.writebacks::total 681263 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938392 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 938392 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255335 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 255335 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13590 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13590 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193727 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1193727 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193727 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1193727 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30276027000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30276027000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12407172500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12407172500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136778000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136778000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26224500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26224500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42683199500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 42683199500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42683199500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 42683199500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572134500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572134500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572134500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572134500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127855 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127855 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051846 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051846 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089066 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089066 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097333 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097333 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.730935 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.730935 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48591.742221 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48591.742221 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10064.606328 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10064.606328 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.299581 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.299581 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.656581 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.656581 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.288920 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.288920 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 692168 # number of replacements -system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47009511 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 692680 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.866130 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 44813247500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48395123 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48395123 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 47009511 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47009511 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47009511 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47009511 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47009511 # number of overall hits -system.cpu0.icache.overall_hits::total 47009511 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 692806 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 692806 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 692806 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 692806 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 692806 # number of overall misses -system.cpu0.icache.overall_misses::total 692806 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10342349000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10342349000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10342349000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10342349000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10342349000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10342349000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47702317 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47702317 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47702317 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47702317 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47702317 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47702317 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.203566 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.203566 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14928.203566 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14928.203566 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 692168 # number of writebacks -system.cpu0.icache.writebacks::total 692168 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692806 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 692806 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 692806 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 692806 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 692806 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 692806 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9649543000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9649543000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9649543000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9649543000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9649543000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9649543000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.203566 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2442461 # DTB read hits -system.cpu1.dtb.read_misses 2621 # DTB read misses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 205338 # DTB read accesses -system.cpu1.dtb.write_hits 1749247 # DTB write hits -system.cpu1.dtb.write_misses 236 # DTB write misses -system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 89740 # DTB write accesses -system.cpu1.dtb.data_hits 4191708 # DTB hits -system.cpu1.dtb.data_misses 2857 # DTB misses -system.cpu1.dtb.data_acv 24 # DTB access violations -system.cpu1.dtb.data_accesses 295078 # DTB accesses -system.cpu1.itb.fetch_hits 1826964 # ITB hits -system.cpu1.itb.fetch_misses 1064 # ITB misses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1828028 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 692201198.395722 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 417085998.942743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 61500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 974672500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 25117814500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941624361500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3931646343 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 79704 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27198 38.42% 38.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41099 58.06% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 70791 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26333 48.20% 48.20% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25808 47.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 54635 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909855455500 97.15% 97.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731138500 0.04% 97.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 371933000 0.02% 97.21% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 54864614500 2.79% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1965823141500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968196 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.627947 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771779 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 64571 88.14% 91.50% # number of callpals executed -system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed -system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed -system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73263 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 816 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 449 -system.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18379231500 0.94% 0.94% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1492112000 0.08% 1.01% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1945079443000 98.99% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2017 # number of times the context was actually changed -system.cpu1.committedInsts 13268542 # Number of instructions committed -system.cpu1.committedOps 13268542 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12224320 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses -system.cpu1.num_func_calls 423403 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1315333 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12224320 # number of integer instructions -system.cpu1.num_fp_insts 175144 # number of float instructions -system.cpu1.num_int_register_reads 16795598 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8988647 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written -system.cpu1.num_mem_refs 4214775 # number of memory refs -system.cpu1.num_load_insts 2456291 # Number of load instructions -system.cpu1.num_store_insts 1758484 # Number of store instructions -system.cpu1.num_idle_cycles 3881434187.727123 # Number of idle cycles -system.cpu1.num_busy_cycles 50212155.272877 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012771 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987229 # Percentage of idle cycles -system.cpu1.Branches 1898911 # Number of branches fetched -system.cpu1.op_class::No_OpClass 719210 5.42% 5.42% # Class of executed instruction -system.cpu1.op_class::IntAlu 7860972 59.23% 64.65% # Class of executed instruction -system.cpu1.op_class::IntMult 22603 0.17% 64.82% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.93% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.93% # Class of executed instruction -system.cpu1.op_class::MemRead 2447819 18.44% 83.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 1681290 12.67% 96.05% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction -system.cpu1.op_class::IprAccess 364385 2.75% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13271423 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 162127 # number of replacements -system.cpu1.dcache.tags.tagsinuse 484.320008 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4015090 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 162456 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.714938 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 72636345500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320008 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16996743 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16996743 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2273788 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2273788 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1634135 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1634135 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51915 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 51915 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52085 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 52085 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3907923 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3907923 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3907923 # number of overall hits -system.cpu1.dcache.overall_hits::total 3907923 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118690 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118690 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 58791 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 58791 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9152 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9152 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6117 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6117 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 177481 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 177481 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 177481 # number of overall misses -system.cpu1.dcache.overall_misses::total 177481 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1467443500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1467443500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1300528500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1300528500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84062000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84062000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34151000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 34151000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2767972000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2767972000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2767972000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2767972000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392478 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2392478 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692926 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1692926 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61067 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 61067 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58202 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 58202 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4085404 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4085404 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4085404 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4085404 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049610 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049610 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034727 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034727 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149868 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149868 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105099 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105099 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043443 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043443 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043443 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043443 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12363.665852 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12363.665852 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22121.217533 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22121.217533 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.096154 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.096154 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5582.965506 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5582.965506 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15595.877869 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15595.877869 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 111642 # number of writebacks -system.cpu1.dcache.writebacks::total 111642 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118690 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118690 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58791 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 58791 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9152 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9152 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6117 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6117 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 177481 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 177481 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 177481 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 177481 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1348753500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1348753500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1241737500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1241737500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74910000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74910000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28034000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28034000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2590491000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2590491000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2590491000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2590491000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049610 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049610 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034727 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034727 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149868 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149868 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105099 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105099 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043443 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043443 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11363.665852 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11363.665852 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21121.217533 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21121.217533 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.096154 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.096154 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4582.965506 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4582.965506 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 326560 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.783409 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12944312 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 327071 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.576459 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960887860500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783409 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13598534 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13598534 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 12944312 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12944312 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12944312 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12944312 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12944312 # number of overall hits -system.cpu1.icache.overall_hits::total 12944312 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 327111 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 327111 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 327111 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 327111 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 327111 # number of overall misses -system.cpu1.icache.overall_misses::total 327111 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4448984500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4448984500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4448984500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4448984500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4448984500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4448984500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13271423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13271423 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13271423 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13271423 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13271423 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024648 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024648 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024648 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024648 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024648 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024648 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.840388 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13600.840388 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13600.840388 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13600.840388 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 326560 # number of writebacks -system.cpu1.icache.writebacks::total 326560 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327111 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 327111 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 327111 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 327111 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 327111 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 327111 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4121873500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4121873500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4121873500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4121873500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4121873500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4121873500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024648 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024648 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024648 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12600.840388 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 55675 # Transaction distribution -system.iobus.trans_dist::WriteResp 55675 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42642 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56144 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216236013 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.568425 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1760410358000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.568425 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035527 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035527 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375570 # Number of tag accesses -system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4955951130 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4955951130 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4978364013 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4978364013 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4978364013 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4978364013 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119271.061080 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119271.061080 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119299.401222 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119299.401222 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2875898127 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2875898127 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2889411010 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2889411010 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2889411010 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2889411010 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69212.026545 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69212.026545 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 342924 # number of replacements -system.l2c.tags.tagsinuse 65389.954347 # Cycle average of tags in use -system.l2c.tags.total_refs 3989934 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 408445 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.768596 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7750508000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 285.827021 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4794.067634 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 59305.224879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 165.844219 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 838.990595 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073152 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.904926 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002531 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012802 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35598107 # Number of tag accesses -system.l2c.tags.data_accesses 35598107 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 792905 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 792905 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 747283 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 747283 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3151 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2387 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5538 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 946 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 957 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1903 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 128511 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 43286 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171797 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 680335 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 326126 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1006461 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 663262 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 108452 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 771714 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 680335 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 791773 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 326126 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 151738 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949972 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 680335 # number of overall hits -system.l2c.overall_hits::cpu0.data 791773 # number of overall hits -system.l2c.overall_hits::cpu1.inst 326126 # number of overall hits -system.l2c.overall_hits::cpu1.data 151738 # number of overall hits -system.l2c.overall_hits::total 1949972 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 116816 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6419 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123235 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 12450 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 984 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13434 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 271517 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 339 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 271856 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 12450 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 388333 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 984 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6758 # number of demand (read+write) misses -system.l2c.demand_misses::total 408525 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12450 # number of overall misses -system.l2c.overall_misses::cpu0.data 388333 # number of overall misses -system.l2c.overall_misses::cpu1.inst 984 # number of overall misses -system.l2c.overall_misses::cpu1.data 6758 # number of overall misses -system.l2c.overall_misses::total 408525 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 300000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 28500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 328500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 10623244500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 659466000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11282710500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1281529500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 100368000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1381897500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 21945590000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 41766500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 21987356500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1281529500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 32568834500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 100368000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 701232500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 34651964500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1281529500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 32568834500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 100368000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 701232500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 34651964500 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 792905 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 792905 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 747283 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 747283 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3156 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2388 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5544 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 946 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 957 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1903 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 245327 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 49705 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295032 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 692785 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 327110 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1019895 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 934779 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 108791 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1043570 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 692785 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1180106 # 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mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013161 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290461 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003116 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260506 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173209 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173209 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80939.978256 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92736.563328 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 81554.432588 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92885.159800 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70825.841476 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113205.014749 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70878.687614 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 856478 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 407046 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 512 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7198 # Transaction distribution -system.membus.trans_dist::ReadResp 292655 # Transaction distribution -system.membus.trans_dist::WriteReq 14123 # Transaction distribution -system.membus.trans_dist::WriteResp 14123 # Transaction distribution -system.membus.trans_dist::WritebackDirty 121475 # Transaction distribution -system.membus.trans_dist::CleanEvict 262336 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11690 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9942 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 123955 # Transaction distribution -system.membus.trans_dist::ReadExResp 123087 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285457 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 148 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181082 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1223724 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1307167 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31318106 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33976346 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22923 # Total snoops (count) -system.membus.snoopTraffic 27264 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 493917 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001373 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037025 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 493239 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 678 0.14% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 493917 # Request fanout histogram -system.membus.reqLayer0.occupancy 40493500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1322925099 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2182236750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1074598 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4789722 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2388089 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 374620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 991 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 930 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107102 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 872860 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1018728 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 815346 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17080 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11845 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28925 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297046 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297046 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019917 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079990 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077759 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616208 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980781 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523727 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7198475 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88636992 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119193988 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41834880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17315286 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266981146 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 403271 # Total snoops (count) -system.toL2Bus.snoopTraffic 7578112 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2790369 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.143087 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.350419 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2391353 85.70% 85.70% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 398767 14.29% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 248 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2790369 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4224217497 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 304383 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1039374668 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1817986111 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 491891046 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 276353266 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal deleted file mode 100644 index fff26b301..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal +++ /dev/null @@ -1,113 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 -
Got Configuration 623 -
memsize 8000000 pages 4000 -
First free page after ROM 0xFFFFFC0000018000 -
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 -
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 -
CPU Clock at 2000 MHz IntrClockFrequency=1024 -
Booting with 2 processor(s) -
KSP: 0x20043FE8 PTBR 0x20 -
KSP: 0x20043FE8 PTBR 0x20 -
Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 -
Memory cluster 0 [0 - 392] -
Memory cluster 1 [392 - 15992] -
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 -
ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 -
Bootstraping CPU 1 with sp=0xFFFFFC0000076000 -
unix_boot_mem ends at FFFFFC0000078000 -
k_argc = 0 -
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) -
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 -
CallbackFixup 0 18000, t7=FFFFFC000070C000 -
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 -
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM -
Major Options: SMP LEGACY_START VERBOSE_MCHECK -
Command line: root=/dev/hda1 console=ttyS0 -
memcluster 0, usage 1, start 0, end 392 -
memcluster 1, usage 0, start 392, end 16384 -
freeing pages 1069:16384 -
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles -
SMP: 2 CPUs probed -- cpu_present_mask = 3 -
Built 1 zonelists -
Kernel command line: root=/dev/hda1 console=ttyS0 -
PID hash table entries: 1024 (order: 10, 32768 bytes) -
Using epoch = 1900 -
Console: colour dummy device 80x25 -
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) -
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) -
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) -
Mount-cache hash table entries: 512 -
SMP starting up secondaries. -
Slave CPU 1 console command START
-SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 -
Brought up 2 CPUs -
SMP: Total of 2 processors activated (8000.15 BogoMIPS). -
NET: Registered protocol family 16 -
EISA bus registered -
pci: enabling save/restore of SRM state -
SCSI subsystem initialized -
srm_env: version 0.0.5 loaded successfully -
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). -
Initializing Cryptographic API -
rtc: Standard PC (1900) epoch (1900) detected -
Real Time Clock Driver v1.12 -
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled -
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 -
io scheduler noop registered -
io scheduler anticipatory registered -
io scheduler deadline registered -
io scheduler cfq registered -
loop: loaded (max 8 devices) -
nbd: registered device at major 43 -
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. -
PCI: Setting latency timer of device 0000:00:01.0 to 64 -
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 -
eth0: enabling optical transceiver -
eth0: using 64 bit addressing. -
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg -
tun: Universal TUN/TAP device driver, 1.6 -
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> -
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 -
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -
PIIX4: IDE controller at PCI slot 0000:00:00.0 -
PIIX4: chipset revision 0 -
PIIX4: 100% native mode on irq 31 -
PCI: Setting latency timer of device 0000:00:00.0 to 64 -
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA -
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA -
hda: M5 IDE Disk, ATA DISK drive -
hdb: M5 IDE Disk, ATA DISK drive -
ide0 at 0x8410-0x8417,0x8422 on irq 31 -
hda: max request size: 128KiB -
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) -
hda: cache flushes not supported -
hda: hda1 -
hdb: max request size: 128KiB -
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) -
hdb: cache flushes not supported -
hdb: unknown partition table -
mice: PS/2 mouse device common for all mice -
NET: Registered protocol family 2 -
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) -
TCP established hash table entries: 16384 (order: 5, 262144 bytes) -
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) -
TCP: Hash tables configured (established 16384 bind 16384) -
TCP reno registered -
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack -
ip_tables: (C) 2000-2002 Netfilter core team -
arp_tables: (C) 2002 David S. Miller -
TCP bic registered -
Initializing IPsec netlink socket -
NET: Registered protocol family 1 -
NET: Registered protocol family 17 -
NET: Registered protocol family 15 -
Bridge firewalling registered -
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> -
All bugs added by David S. Miller <davem@redhat.com> -
VFS: Mounted root (ext2 filesystem) readonly. -
Freeing unused kernel memory: 224k freed -
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script...
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini deleted file mode 100644 index 7a4d88e30..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ /dev/null @@ -1,1346 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:134217727:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615:0:0:0:0 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr deleted file mode 100755 index a8a3639b1..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr +++ /dev/null @@ -1,6 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout deleted file mode 100755 index 1d59c0edc..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28068 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1926421414000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt deleted file mode 100644 index 0bead1a4b..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ /dev/null @@ -1,1226 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.926422 # Number of seconds simulated -sim_ticks 1926421638000 # Number of ticks simulated -final_tick 1926421638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1739419 # Simulator instruction rate (inst/s) -host_op_rate 1739418 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59628989604 # Simulator tick rate (ticks/s) -host_mem_usage 334072 # Number of bytes of host memory used -host_seconds 32.31 # Real time elapsed on the host -sim_insts 56195014 # Number of instructions simulated -sim_ops 56195014 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25702528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 844672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 844672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7408960 # Number of bytes written to this memory -system.physmem.bytes_written::total 7408960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13198 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388389 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401602 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12903144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13342109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3845970 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3845970 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3845970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12903144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17188079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401602 # Number of read requests accepted -system.physmem.writeReqs 115765 # Number of write requests accepted -system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115765 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25695552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 7408000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25702528 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7408960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25229 # Per bank write bursts -system.physmem.perBankRdBursts::1 25631 # Per bank write bursts -system.physmem.perBankRdBursts::2 25563 # Per bank write bursts -system.physmem.perBankRdBursts::3 25503 # Per bank write bursts -system.physmem.perBankRdBursts::4 24978 # Per bank write bursts -system.physmem.perBankRdBursts::5 24964 # Per bank write bursts -system.physmem.perBankRdBursts::6 24209 # Per bank write bursts -system.physmem.perBankRdBursts::7 24494 # Per bank write bursts -system.physmem.perBankRdBursts::8 25180 # Per bank write bursts -system.physmem.perBankRdBursts::9 24757 # Per bank write bursts -system.physmem.perBankRdBursts::10 25269 # Per bank write bursts -system.physmem.perBankRdBursts::11 24873 # Per bank write bursts -system.physmem.perBankRdBursts::12 24512 # Per bank write bursts -system.physmem.perBankRdBursts::13 25367 # Per bank write bursts -system.physmem.perBankRdBursts::14 25615 # Per bank write bursts -system.physmem.perBankRdBursts::15 25349 # Per bank write bursts -system.physmem.perBankWrBursts::0 7626 # Per bank write bursts -system.physmem.perBankWrBursts::1 7640 # Per bank write bursts -system.physmem.perBankWrBursts::2 7866 # Per bank write bursts -system.physmem.perBankWrBursts::3 7539 # Per bank write bursts -system.physmem.perBankWrBursts::4 7128 # Per bank write bursts -system.physmem.perBankWrBursts::5 6982 # Per bank write bursts -system.physmem.perBankWrBursts::6 6324 # Per bank write bursts -system.physmem.perBankWrBursts::7 6321 # Per bank write bursts -system.physmem.perBankWrBursts::8 7317 # Per bank write bursts -system.physmem.perBankWrBursts::9 6511 # Per bank write bursts -system.physmem.perBankWrBursts::10 7117 # Per bank write bursts -system.physmem.perBankWrBursts::11 6900 # Per bank write bursts -system.physmem.perBankWrBursts::12 7101 # Per bank write bursts -system.physmem.perBankWrBursts::13 7827 # Per bank write bursts -system.physmem.perBankWrBursts::14 7864 # Per bank write bursts -system.physmem.perBankWrBursts::15 7687 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 65 # Number of times write queue was full causing retry -system.physmem.totGap 1926409764500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401602 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115765 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 521.512887 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 315.060266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.295929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14957 23.56% 23.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11430 18.01% 41.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4320 6.81% 48.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3081 4.85% 53.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3222 5.08% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1508 2.38% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1584 2.50% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 999 1.57% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22375 35.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63476 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5046 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.953728 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.991500 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4538 89.88% 89.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 34 0.67% 90.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 165 3.27% 93.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.16% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 5 0.10% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 34 0.67% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 141 2.79% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 16 0.32% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 12 0.24% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 13 0.26% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads -system.physmem.totQLat 6110922250 # Total ticks spent queuing -system.physmem.totMemAccLat 13638916000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15220.50 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33970.50 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.13 # Data bus utilization in percentage -system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing -system.physmem.readRowHits 360225 # Number of row buffer hits during reads -system.physmem.writeRowHits 93542 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3723487.90 # Average gap between requests -system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5038088640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 365587680 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13029981120 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6359365440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 449603503800 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 481990544460 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.199922 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1914259413500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 611958500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1869275787500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16560859500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9050522500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28574618000 # Time in different power states -system.physmem_1.actEnergy 232378440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123512070 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5156813940 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 361085280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13650484260 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6593796000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 449082763260 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 482651694330 # Total energy per rank (pJ) -system.physmem_1.averagePower 250.543123 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1914156494000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 598122250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1867055047500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17171481750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9234080250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 29935396250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066536 # DTB read hits -system.cpu.dtb.read_misses 10331 # DTB read misses -system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728865 # DTB read accesses -system.cpu.dtb.write_hits 6357492 # DTB write hits -system.cpu.dtb.write_misses 1143 # DTB write misses -system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291932 # DTB write accesses -system.cpu.dtb.data_hits 15424028 # DTB hits -system.cpu.dtb.data_misses 11474 # DTB misses -system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020797 # DTB accesses -system.cpu.itb.fetch_hits 4975201 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses -system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980211 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12758 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281128919.971939 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439406494.656653 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 133100257499 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321380501 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3852843276 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212049 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74911 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1934 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106246 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183222 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73544 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1859428733000 96.52% 96.52% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 772464500 0.04% 96.57% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 66125203500 3.43% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1926420904000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692205 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814056 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175997 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5159 2.67% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192947 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 47043334000 2.44% 2.44% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5370278500 0.28% 2.72% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1874007289500 97.28% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.committedInsts 56195014 # Number of instructions committed -system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066552 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1483758 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469897 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066552 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 71340789 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530081 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 15476659 # number of memory refs -system.cpu.num_load_insts 9103400 # Number of load instructions -system.cpu.num_store_insts 6373259 # Number of store instructions -system.cpu.num_idle_cycles 3586642761.000138 # Number of idle cycles -system.cpu.num_busy_cycles 266200514.999862 # Number of busy cycles -system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.930908 # Percentage of idle cycles -system.cpu.Branches 8424278 # Number of branches fetched -system.cpu.op_class::No_OpClass 3201027 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36239709 64.48% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61024 0.11% 70.28% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9185894 16.34% 86.70% # Class of executed instruction -system.cpu.op_class::MemWrite 6241230 11.10% 97.80% # Class of executed instruction -system.cpu.op_class::FloatMemRead 144629 0.26% 98.06% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 138108 0.25% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56206855 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1390804 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14051759 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391316 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.099617 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999954 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63163621 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63163621 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7815914 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815914 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853567 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853567 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183003 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183003 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199258 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669481 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669481 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669481 # number of overall hits -system.cpu.dcache.overall_hits::total 13669481 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069734 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069734 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304322 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304322 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17278 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17278 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374056 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374056 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374056 # number of overall misses -system.cpu.dcache.overall_misses::total 1374056 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050329500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33050329500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442227500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13442227500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46492557000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46492557000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46492557000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46492557000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157889 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200281 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200281 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199258 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199258 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15043537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120389 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120389 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049420 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049420 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086269 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086269 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.839059 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.839059 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.067159 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.067159 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.823706 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.823706 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33835.998678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33835.998678 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 835203 # number of writebacks -system.cpu.dcache.writebacks::total 835203 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069734 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069734 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304322 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304322 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17278 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17278 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374056 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374056 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374056 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374056 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980595500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980595500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137905500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137905500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215229000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215229000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45118501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45118501000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533908500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533908500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533908500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533908500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120389 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120389 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049420 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049420 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086269 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086269 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091339 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091339 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.839059 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.839059 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.067159 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.067159 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.823706 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.823706 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.217893 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.217893 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92504.432517 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92504.432517 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 928685 # number of replacements -system.cpu.icache.tags.tagsinuse 507.830405 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55277500 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929196 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.489602 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 44439092500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 507.830405 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.991856 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.991856 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57136212 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57136212 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14321.838994 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 928685 # number of writebacks -system.cpu.icache.writebacks::total 928685 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929356 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929356 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929356 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929356 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929356 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929356 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380731000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12380731000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380731000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12380731000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380731000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12380731000 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 336397 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65387.710870 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4236311 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401919 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.540211 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 7724199000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 234.658565 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574877 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477428 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.003581 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072183 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.921974 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4685 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59935 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37511410 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37511410 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 835203 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 835203 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 928452 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 928452 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187488 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187488 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916138 # 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number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540730500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540730500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221942000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221942000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273468500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273468500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221942000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814199000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30036141000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221942000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814199000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30036141000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383881 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383881 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250203 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250203 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81672.449215 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81672.449215 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92585.391726 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92585.391726 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70865.113945 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70865.113945 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4640179 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319543 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023455 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 909456 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 928685 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 817745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304305 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304305 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929356 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087173 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787377 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206794 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6994171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142551908 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261465252 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 336955 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2674049 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001078 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032812 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2671167 99.89% 99.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2882 0.11% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2674049 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4097094500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 293883 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394034000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098740000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51204 # Transaction distribution -system.iobus.trans_dist::WriteResp 51204 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116614 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5344000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15813000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6041500 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216206774 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.342515 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.342515 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083907 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083907 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937049891 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4937049891 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4958898774 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4958898774 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4958898774 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4958898774 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118816.179510 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118816.179510 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118847.184518 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118847.184518 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 175 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857005811 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2857005811 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2870204694 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2870204694 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2870204694 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2870204694 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68757.359718 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68757.359718 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 378172 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292275 # Transaction distribution -system.membus.trans_dist::WriteReq 9652 # Transaction distribution -system.membus.trans_dist::WriteResp 9652 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115765 # Transaction distribution -system.membus.trans_dist::CleanEvict 261592 # Transaction distribution -system.membus.trans_dist::UpgradeReq 136 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 116686 # Transaction distribution -system.membus.trans_dist::ReadExResp 116686 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 124 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1255842 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30453760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 555 # Total snoops (count) -system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 460301 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001419 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037638 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 459648 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 653 0.14% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 460301 # Request fanout histogram -system.membus.reqLayer0.occupancy 30123500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1287046834 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2142988500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1022522 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal deleted file mode 100644 index d82c05314..000000000 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal +++ /dev/null @@ -1,108 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 -
Got Configuration 623 -
memsize 8000000 pages 4000 -
First free page after ROM 0xFFFFFC0000018000 -
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 -
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 -
CPU Clock at 2000 MHz IntrClockFrequency=1024 -
Booting with 1 processor(s) -
KSP: 0x20043FE8 PTBR 0x20 -
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 -
Memory cluster 0 [0 - 392] -
Memory cluster 1 [392 - 15992] -
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 -
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 -
unix_boot_mem ends at FFFFFC0000076000 -
k_argc = 0 -
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) -
CallbackFixup 0 18000, t7=FFFFFC000070C000 -
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 -
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM -
Major Options: SMP LEGACY_START VERBOSE_MCHECK -
Command line: root=/dev/hda1 console=ttyS0 -
memcluster 0, usage 1, start 0, end 392 -
memcluster 1, usage 0, start 392, end 16384 -
freeing pages 1069:16384 -
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles -
SMP: 1 CPUs probed -- cpu_present_mask = 1 -
Built 1 zonelists -
Kernel command line: root=/dev/hda1 console=ttyS0 -
PID hash table entries: 1024 (order: 10, 32768 bytes) -
Using epoch = 1900 -
Console: colour dummy device 80x25 -
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) -
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) -
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) -
Mount-cache hash table entries: 512 -
SMP mode deactivated. -
Brought up 1 CPUs -
SMP: Total of 1 processors activated (4002.20 BogoMIPS). -
NET: Registered protocol family 16 -
EISA bus registered -
pci: enabling save/restore of SRM state -
SCSI subsystem initialized -
srm_env: version 0.0.5 loaded successfully -
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). -
Initializing Cryptographic API -
rtc: Standard PC (1900) epoch (1900) detected -
Real Time Clock Driver v1.12 -
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled -
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 -
io scheduler noop registered -
io scheduler anticipatory registered -
io scheduler deadline registered -
io scheduler cfq registered -
loop: loaded (max 8 devices) -
nbd: registered device at major 43 -
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. -
PCI: Setting latency timer of device 0000:00:01.0 to 64 -
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 -
eth0: enabling optical transceiver -
eth0: using 64 bit addressing. -
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg -
tun: Universal TUN/TAP device driver, 1.6 -
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> -
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 -
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -
PIIX4: IDE controller at PCI slot 0000:00:00.0 -
PIIX4: chipset revision 0 -
PIIX4: 100% native mode on irq 31 -
PCI: Setting latency timer of device 0000:00:00.0 to 64 -
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA -
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA -
hda: M5 IDE Disk, ATA DISK drive -
hdb: M5 IDE Disk, ATA DISK drive -
ide0 at 0x8410-0x8417,0x8422 on irq 31 -
hda: max request size: 128KiB -
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) -
hda: cache flushes not supported -
hda: hda1 -
hdb: max request size: 128KiB -
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) -
hdb: cache flushes not supported -
hdb: unknown partition table -
mice: PS/2 mouse device common for all mice -
NET: Registered protocol family 2 -
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) -
TCP established hash table entries: 16384 (order: 5, 262144 bytes) -
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) -
TCP: Hash tables configured (established 16384 bind 16384) -
TCP reno registered -
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack -
ip_tables: (C) 2000-2002 Netfilter core team -
arp_tables: (C) 2002 David S. Miller -
TCP bic registered -
Initializing IPsec netlink socket -
NET: Registered protocol family 1 -
NET: Registered protocol family 17 -
NET: Registered protocol family 15 -
Bridge firewalling registered -
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> -
All bugs added by David S. Miller <davem@redhat.com> -
VFS: Mounted root (ext2 filesystem) readonly. -
Freeing unused kernel memory: 224k freed -
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script...
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