diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
5 files changed, 5779 insertions, 5299 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index b46274bd4..676e01409 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,133 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.961841 # Number of seconds simulated -sim_ticks 1961841175000 # Number of ticks simulated -final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961837 # Number of seconds simulated +sim_ticks 1961837389000 # Number of ticks simulated +final_tick 1961837389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1272238 # Simulator instruction rate (inst/s) -host_op_rate 1272238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42053157352 # Simulator tick rate (ticks/s) -host_mem_usage 308880 # Number of bytes of host memory used -host_seconds 46.65 # Real time elapsed on the host -sim_insts 59351715 # Number of instructions simulated -sim_ops 59351715 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24914752 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 32192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 287808 # Number of bytes read from this memory -system.physmem.bytes_read::total 28716928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 32192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7746368 # Number of bytes written to this memory -system.physmem.bytes_written::total 7746368 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389293 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4497 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121037 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121037 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12699678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351188 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 146703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14637744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423765 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3948519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3948519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3948519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12699678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448702 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 121037 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 448702 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 121037 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28716928 # Total number of bytes read from memory -system.physmem.bytesWritten 7746368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28314 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28019 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27858 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27836 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27466 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27953 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27826 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28040 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28092 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28236 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7314 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7222 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7326 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8207 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7890 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1961833946000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448702 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121037 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +host_inst_rate 1325125 # Simulator instruction rate (inst/s) +host_op_rate 1325124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42668778131 # Simulator tick rate (ticks/s) +host_mem_usage 308960 # Number of bytes of host memory used +host_seconds 45.98 # Real time elapsed on the host +sim_insts 60926932 # Number of instructions simulated +sim_ops 60926932 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 833280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 338432 # Number of bytes read from this memory +system.physmem.bytes_read::total 28741376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7742464 # Number of bytes written to this memory +system.physmem.bytes_written::total 7742464 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5288 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449084 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120976 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120976 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12685610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 172508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14650234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3946537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3946537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3946537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12685610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 172508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18596771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449084 # Number of read requests accepted +system.physmem.writeReqs 120976 # Number of write requests accepted +system.physmem.readBursts 449084 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120976 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28737920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3456 # Total number of bytes read from write queue +system.physmem.bytesWritten 7741568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28741376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7742464 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 54 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 7077 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28167 # Per bank write bursts +system.physmem.perBankRdBursts::1 28458 # Per bank write bursts +system.physmem.perBankRdBursts::2 28055 # Per bank write bursts +system.physmem.perBankRdBursts::3 27665 # Per bank write bursts +system.physmem.perBankRdBursts::4 27762 # Per bank write bursts +system.physmem.perBankRdBursts::5 27792 # Per bank write bursts +system.physmem.perBankRdBursts::6 28261 # Per bank write bursts +system.physmem.perBankRdBursts::7 27879 # Per bank write bursts +system.physmem.perBankRdBursts::8 28077 # Per bank write bursts +system.physmem.perBankRdBursts::9 27735 # Per bank write bursts +system.physmem.perBankRdBursts::10 27671 # Per bank write bursts +system.physmem.perBankRdBursts::11 28135 # Per bank write bursts +system.physmem.perBankRdBursts::12 28173 # Per bank write bursts +system.physmem.perBankRdBursts::13 28505 # Per bank write bursts +system.physmem.perBankRdBursts::14 28655 # Per bank write bursts +system.physmem.perBankRdBursts::15 28040 # Per bank write bursts +system.physmem.perBankWrBursts::0 7931 # Per bank write bursts +system.physmem.perBankWrBursts::1 7869 # Per bank write bursts +system.physmem.perBankWrBursts::2 7539 # Per bank write bursts +system.physmem.perBankWrBursts::3 7157 # Per bank write bursts +system.physmem.perBankWrBursts::4 7275 # Per bank write bursts +system.physmem.perBankWrBursts::5 7313 # Per bank write bursts +system.physmem.perBankWrBursts::6 7748 # Per bank write bursts +system.physmem.perBankWrBursts::7 7258 # Per bank write bursts +system.physmem.perBankWrBursts::8 7316 # Per bank write bursts +system.physmem.perBankWrBursts::9 7114 # Per bank write bursts +system.physmem.perBankWrBursts::10 7078 # Per bank write bursts +system.physmem.perBankWrBursts::11 7523 # Per bank write bursts +system.physmem.perBankWrBursts::12 7676 # Per bank write bursts +system.physmem.perBankWrBursts::13 8141 # Per bank write bursts +system.physmem.perBankWrBursts::14 8336 # Per bank write bursts +system.physmem.perBankWrBursts::15 7688 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1961830378000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 449084 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 120976 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 409885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -139,382 +141,444 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 922.589599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.543369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2381.494153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13878 35.12% 35.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6056 15.33% 50.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3741 9.47% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2391 6.05% 65.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1744 4.41% 70.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1425 3.61% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1039 2.63% 76.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 750 1.90% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 668 1.69% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 592 1.50% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 528 1.34% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 459 1.16% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 301 0.76% 84.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 245 0.62% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 187 0.47% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 264 0.67% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 137 0.35% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 111 0.28% 87.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 92 0.23% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 96 0.24% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 88 0.22% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 105 0.27% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1100 2.78% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 187 0.47% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 132 0.33% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 88 0.22% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 54 0.14% 92.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 43 0.11% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 23 0.06% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 21 0.05% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 20 0.05% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 29 0.07% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 11 0.03% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 14 0.04% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 4 0.01% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 6 0.02% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.00% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 2 0.01% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 4 0.01% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 2 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 3 0.01% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 3 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 4 0.01% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 2 0.01% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 3 0.01% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 2 0.01% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.01% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.01% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 6 0.02% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2432 6.15% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 3 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 2 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 242 0.61% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 10 0.03% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 6 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 6 0.02% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17987 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39515 # Bytes accessed per row activation -system.physmem.totQLat 3750140000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12006448750 # Sum of mem lat for all requests -system.physmem.totBusLat 2243145000 # Total cycles spent in databus access -system.physmem.totBankLat 6013163750 # Total cycles spent in bank access -system.physmem.avgQLat 8359.11 # Average queueing delay per request -system.physmem.avgBankLat 13403.42 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26762.53 # Average memory access latency -system.physmem.avgRdBW 14.64 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 49252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 740.628604 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 223.502021 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1737.958624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 17638 35.81% 35.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 7255 14.73% 50.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4934 10.02% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2938 5.97% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1843 3.74% 70.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1471 2.99% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1137 2.31% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 871 1.77% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 749 1.52% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 678 1.38% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 696 1.41% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 441 0.90% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 346 0.70% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 295 0.60% 83.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 325 0.66% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 366 0.74% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 215 0.44% 85.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 196 0.40% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 200 0.41% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 126 0.26% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 182 0.37% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 862 1.75% 88.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 228 0.46% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 113 0.23% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 126 0.26% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 100 0.20% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 86 0.17% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 47 0.10% 90.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 73 0.15% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 75 0.15% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 79 0.16% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 32 0.06% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 84 0.17% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 62 0.13% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 61 0.12% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 26 0.05% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 60 0.12% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 59 0.12% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 68 0.14% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 29 0.06% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 67 0.14% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 63 0.13% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 57 0.12% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 25 0.05% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 61 0.12% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 59 0.12% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 69 0.14% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 25 0.05% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 65 0.13% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 58 0.12% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 65 0.13% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 25 0.05% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 59 0.12% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 71 0.14% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 22 0.04% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 70 0.14% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 53 0.11% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 60 0.12% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 27 0.05% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 61 0.12% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 53 0.11% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 63 0.13% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 34 0.07% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 63 0.13% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 57 0.12% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 62 0.13% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 28 0.06% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 58 0.12% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 54 0.11% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 66 0.13% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 361 0.73% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 57 0.12% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 23 0.05% 95.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 53 0.11% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 23 0.05% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 58 0.12% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 23 0.05% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 51 0.10% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 22 0.04% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 54 0.11% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 39 0.08% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 55 0.11% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 21 0.04% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 55 0.11% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 27 0.05% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 50 0.10% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 22 0.04% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 54 0.11% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 25 0.05% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 53 0.11% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 22 0.04% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 52 0.11% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 23 0.05% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 54 0.11% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 23 0.05% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 52 0.11% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 23 0.05% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 54 0.11% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 23 0.05% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 53 0.11% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 23 0.05% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 55 0.11% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 26 0.05% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 57 0.12% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 421 0.85% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 12 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 6 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 4 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 40 0.08% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 179 0.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49252 # Bytes accessed per row activation +system.physmem.totQLat 6314810500 # Total ticks spent queuing +system.physmem.totMemAccLat 14686644250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2245150000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6126683750 # Total ticks spent accessing banks +system.physmem.avgQLat 14063.23 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13644.26 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32707.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 6.90 # Average write queue length over time -system.physmem.readRowHits 433153 # Number of row buffer hits during reads -system.physmem.writeRowHits 96987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes -system.physmem.avgGap 3443390.65 # Average gap between requests -system.membus.throughput 18639952 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292620 # Transaction distribution -system.membus.trans_dist::ReadResp 292620 # Transaction distribution -system.membus.trans_dist::WriteReq 12397 # Transaction distribution -system.membus.trans_dist::WriteResp 12397 # Transaction distribution -system.membus.trans_dist::Writeback 121037 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4186 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 858 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3168 # Transaction distribution -system.membus.trans_dist::ReadExReq 163944 # Transaction distribution -system.membus.trans_dist::ReadExResp 163855 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36531890 # Total data (bytes) -system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 39129000 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.09 # Average write queue length when enqueuing +system.physmem.readRowHits 424855 # Number of row buffer hits during reads +system.physmem.writeRowHits 95885 # Number of row buffer hits during writes +system.physmem.readRowHitRate 94.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.26 # Row buffer hit rate for writes +system.physmem.avgGap 3441445.42 # Average gap between requests +system.physmem.pageHitRate 91.36 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18657286 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292799 # Transaction distribution +system.membus.trans_dist::ReadResp 292799 # Transaction distribution +system.membus.trans_dist::WriteReq 14111 # Transaction distribution +system.membus.trans_dist::WriteResp 14111 # Transaction distribution +system.membus.trans_dist::Writeback 120976 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16467 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11554 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7080 # Transaction distribution +system.membus.trans_dist::ReadExReq 164905 # Transaction distribution +system.membus.trans_dist::ReadExResp 164053 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42620 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930997 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 973617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1098283 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82306 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31175680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31257986 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36566146 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36566146 # Total data (bytes) +system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 43190000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1559666750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1566162500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3812357322 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3824002662 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376301000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 341780 # number of replacements -system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use -system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 908184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 776732 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 79667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 28709 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1793292 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820882 # number of Writeback hits -system.l2c.Writeback_hits::total 820882 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 160 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 201 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 36 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 176285 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 7535 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183820 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 908184 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 953017 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 79667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 36244 # number of demand (read+write) hits -system.l2c.demand_hits::total 1977112 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 908184 # number of overall hits -system.l2c.overall_hits::cpu0.data 953017 # number of overall hits -system.l2c.overall_hits::cpu1.inst 79667 # number of overall hits -system.l2c.overall_hits::cpu1.data 36244 # number of overall hits -system.l2c.overall_hits::total 1977112 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12993 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271572 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 511 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 178 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285254 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2440 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2923 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 33 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 106 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 118111 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 4331 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122442 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12993 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389683 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 511 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 4509 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57451.052944 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63520.225475 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57700.510194 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53726.370751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63681.296716 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54193.418969 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53726.370751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63681.296716 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54193.418969 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -649,39 +713,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.571330 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses +system.iocache.tags.warmup_cycle 1754532770000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.571330 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035708 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035708 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21912883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21912883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10439154521 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10439154521 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10461067404 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10461067404 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10461067404 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10461067404 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21248383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21248383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12952701816 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12952701816 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12973950199 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12973950199 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12973950199 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12973950199 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -690,40 +754,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123106.084270 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123106.084270 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251231.096482 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251231.096482 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250684.577139 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250684.577139 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 274830 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 311722.704467 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 311722.704467 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 310932.037555 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 310932.037555 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 405757 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27442 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29467 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.014941 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.769878 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12655383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12655383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8277077521 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8277077521 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8289732904 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8289732904 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8289732904 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8289732904 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10790464816 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10790464816 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10802664199 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10802664199 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10802664199 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10802664199 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -732,14 +796,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71097.657303 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71097.657303 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199198.053547 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199198.053547 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 259685.810936 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 259685.810936 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -757,22 +821,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8725663 # DTB read hits +system.cpu0.dtb.read_hits 7530179 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 6139453 # DTB write hits +system.cpu0.dtb.write_hits 5118893 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 14865116 # DTB hits +system.cpu0.dtb.data_hits 12649072 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 4015307 # ITB hits +system.cpu0.itb.fetch_hits 3650586 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 4019291 # ITB accesses +system.cpu0.itb.fetch_accesses 3654570 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -785,55 +849,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923682350 # number of cpu cycles simulated +system.cpu0.numCycles 3923674778 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54601969 # Number of instructions committed -system.cpu0.committedOps 54601969 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50544405 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 297630 # Number of float alu accesses -system.cpu0.num_func_calls 1438477 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6291508 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50544405 # number of integer instructions -system.cpu0.num_fp_insts 297630 # number of float instructions -system.cpu0.num_int_register_reads 69247284 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37427910 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 145753 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 148838 # number of times the floating registers were written -system.cpu0.num_mem_refs 14912078 # number of memory refs -system.cpu0.num_load_insts 8757685 # Number of load instructions -system.cpu0.num_store_insts 6154393 # Number of store instructions -system.cpu0.num_idle_cycles 3674902109.498127 # Number of idle cycles -system.cpu0.num_busy_cycles 248780240.501873 # Number of busy cycles -system.cpu0.not_idle_fraction 0.063405 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.936595 # Percentage of idle cycles +system.cpu0.committedInsts 47959136 # Number of instructions committed +system.cpu0.committedOps 47959136 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44491652 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211334 # Number of float alu accesses +system.cpu0.num_func_calls 1203195 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5632072 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44491652 # number of integer instructions +system.cpu0.num_fp_insts 211334 # number of float instructions +system.cpu0.num_int_register_reads 61191395 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33136181 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 103249 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 105046 # number of times the floating registers were written +system.cpu0.num_mem_refs 12690027 # number of memory refs +system.cpu0.num_load_insts 7557911 # Number of load instructions +system.cpu0.num_store_insts 5132116 # Number of store instructions +system.cpu0.num_idle_cycles 3700191977.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223482800.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.056958 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.943042 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 204697 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 73289 40.68% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.10% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104766 58.15% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 180167 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71920 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.35% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71914 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 145946 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1899196330000 96.81% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95025500 0.00% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 769055500 0.04% 96.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5164500 0.00% 96.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 61774827500 3.15% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961840403000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981321 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6812 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165228 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56779 40.23% 40.23% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.40% 41.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 42.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81809 57.97% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141128 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56269 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55834 48.70% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114643 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1902446374500 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95095000 0.00% 96.98% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 766988500 0.04% 97.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 322426000 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58205747500 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961836631500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991018 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.686425 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810060 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682492 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812333 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -865,37 +929,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3942 2.08% 2.13% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.16% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.16% # number of callpals executed -system.cpu0.kern.callpal::swpipl 173212 91.45% 93.61% # number of callpals executed -system.cpu0.kern.callpal::rdps 6702 3.54% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rti 4842 2.56% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 189397 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7440 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches +system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3084 2.06% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134176 89.75% 92.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6701 4.48% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rti 4411 2.95% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149500 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7010 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1368 -system.cpu0.kern.mode_good::user 1369 +system.cpu0.kern.mode_good::kernel 1372 +system.cpu0.kern.mode_good::user 1373 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.183871 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195720 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.310705 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958025785500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3814613000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327448 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958037655500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3798971500 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3943 # number of times the context was actually changed +system.cpu0.kern.swap_context 3085 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -927,47 +991,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 105075557 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2099191 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2099176 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12397 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12397 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 820882 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4248 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 894 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1842377 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3534341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 160357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 115223 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5652298 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58955328 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 137106504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 5131392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4050090 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 205243314 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 205232754 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) +system.toL2Bus.throughput 103908079 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2101783 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2101768 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14111 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14111 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 792069 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16689 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11613 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28302 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 338794 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297244 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1394675 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121086 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 636287 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 464415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5616463 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44628928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119461456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20361152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17008562 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 201460098 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 201449794 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2400960 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4792055385 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4148559004 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3140628756 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 6195378103 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5519397625 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 360929992 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 206344318 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1431747492 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 796288703 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1391673 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 53949 # Transaction distribution -system.iobus.trans_dist::WriteResp 53949 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1398649 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55663 # Transaction distribution +system.iobus.trans_dist::WriteResp 55663 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -979,11 +1043,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42620 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126072 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56040 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -995,12 +1059,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2730242 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 82306 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2743922 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2743922 # Total data (bytes) +system.iobus.reqLayer0.occupancy 13365000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1022,59 +1086,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378297154 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377760199 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26795000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42664000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 920572 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # 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number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 921200 # number of overall misses -system.cpu0.icache.overall_misses::total 921200 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12937764004 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12937764004 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12937764004 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12937764004 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12937764004 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12937764004 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54610988 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54610988 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54610988 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54610988 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54610988 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54610988 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016868 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016868 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016868 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016868 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016868 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016868 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14044.468089 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14044.468089 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14044.468089 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14044.468089 # average overall miss latency +system.cpu0.icache.tags.replacements 696718 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.401211 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47270807 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 697230 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.798011 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40083254250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.401211 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992971 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992971 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47270807 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47270807 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47270807 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47270807 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47270807 # number of overall hits +system.cpu0.icache.overall_hits::total 47270807 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 697348 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 697348 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 697348 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 697348 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 697348 # number of overall misses +system.cpu0.icache.overall_misses::total 697348 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9977651756 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9977651756 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9977651756 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9977651756 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9977651756 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9977651756 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47968155 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47968155 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47968155 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47968155 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47968155 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47968155 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014538 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014538 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014538 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014538 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014538 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014538 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14307.995084 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14307.995084 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14307.995084 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14307.995084 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1083,112 +1147,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 921200 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 921200 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 921200 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 921200 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 921200 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 921200 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11089045996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11089045996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11089045996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11089045996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11089045996 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11089045996 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016868 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016868 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016868 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12037.609635 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697348 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 697348 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 697348 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 697348 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 697348 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 697348 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8577830244 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8577830244 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8577830244 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8577830244 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8577830244 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8577830244 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014538 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014538 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014538 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12300.645078 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1349865 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5646858 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177791 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 177791 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 193304 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 193304 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 13154053 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 13154053 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 13154053 # number of overall hits -system.cpu0.dcache.overall_hits::total 13154053 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1040730 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1040730 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 297940 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 297940 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16884 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16884 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 399 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 399 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1338670 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1338670 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1338670 # number of overall misses -system.cpu0.dcache.overall_misses::total 1338670 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27787431256 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27787431256 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10644315314 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10644315314 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 223091000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 223091000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2495533 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2495533 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38431746570 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14492723 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14492723 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14492723 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14492723 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.121752 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.121752 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050118 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.050118 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086729 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086729 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092368 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092368 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092368 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092368 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26699.942594 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26699.942594 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35726.372135 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35726.372135 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13213.160389 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13213.160389 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6254.468672 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6254.468672 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 28708.902545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 28708.902545 # average overall miss latency +system.cpu0.dcache.tags.replacements 1186136 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.274988 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11457169 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1186648 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.655070 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 107469250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.274988 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986865 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986865 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6449366 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6449366 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4705451 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4705451 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140478 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140478 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147984 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147984 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11154817 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11154817 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11154817 # number of overall hits +system.cpu0.dcache.overall_hits::total 11154817 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 939343 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 939343 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 256772 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 256772 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13639 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13639 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5591 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5591 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1196115 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1196115 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1196115 # number of overall misses +system.cpu0.dcache.overall_misses::total 1196115 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27074316502 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27074316502 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10448735954 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10448735954 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148878750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 148878750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43336419 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 43336419 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37523052456 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37523052456 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37523052456 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37523052456 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7388709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7388709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4962223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4962223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154117 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154117 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153575 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153575 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12350932 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12350932 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12350932 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12350932 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127132 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127132 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051745 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051745 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088498 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088498 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036406 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036406 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096844 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096844 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096844 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096844 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28822.609528 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28822.609528 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40692.661014 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40692.661014 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10915.664638 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10915.664638 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7751.103380 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7751.103380 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31370.773258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31370.773258 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1197,62 +1261,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 798646 # number of writebacks -system.cpu0.dcache.writebacks::total 798646 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1040730 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1040730 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297940 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 297940 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16884 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16884 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1338670 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1338670 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1338670 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1338670 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25571734744 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25571734744 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9990567686 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9990567686 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 189290000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 189290000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1697467 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1697467 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35562302430 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35562302430 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35562302430 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35562302430 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465580500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465580500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2094321000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2094321000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3559901500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3559901500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121752 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121752 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050118 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050118 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086729 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086729 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092368 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092368 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24570.959561 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24570.959561 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33532.146358 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33532.146358 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11211.205875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11211.205875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4254.303258 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4254.303258 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 682430 # number of writebacks +system.cpu0.dcache.writebacks::total 682430 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939343 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939343 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256772 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 256772 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13639 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13639 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5590 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5590 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196115 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1196115 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196115 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1196115 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25063726498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25063726498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9880374046 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9880374046 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121588250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121588250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32154581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32154581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34944100544 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34944100544 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34944100544 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34944100544 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465575000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465575000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284904500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284904500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750479500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750479500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096844 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096844 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26682.187974 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26682.187974 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38479.172363 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38479.172363 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8914.748149 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8914.748149 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5752.161181 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5752.161181 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1264,22 +1328,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 957039 # DTB read hits +system.cpu1.dtb.read_hits 2385380 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 556340 # DTB write hits +system.cpu1.dtb.write_hits 1707840 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 1513379 # DTB hits +system.cpu1.dtb.data_hits 4093220 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1320031 # ITB hits +system.cpu1.itb.fetch_hits 1814538 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1321095 # ITB accesses +system.cpu1.itb.fetch_accesses 1815602 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1292,51 +1356,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3921887017 # number of cpu cycles simulated +system.cpu1.numCycles 3921880904 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 4749746 # Number of instructions committed -system.cpu1.committedOps 4749746 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4446088 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 30301 # Number of float alu accesses -system.cpu1.num_func_calls 145582 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 455512 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4446088 # number of integer instructions -system.cpu1.num_fp_insts 30301 # number of float instructions -system.cpu1.num_int_register_reads 6169769 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3384887 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 19629 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 19442 # number of times the floating registers were written -system.cpu1.num_mem_refs 1521715 # number of memory refs -system.cpu1.num_load_insts 962201 # Number of load instructions -system.cpu1.num_store_insts 559514 # Number of store instructions -system.cpu1.num_idle_cycles 3904242469.193159 # Number of idle cycles -system.cpu1.num_busy_cycles 17644547.806841 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004499 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995501 # Percentage of idle cycles +system.cpu1.committedInsts 12967796 # Number of instructions committed +system.cpu1.committedOps 12967796 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11946960 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses +system.cpu1.num_func_calls 410982 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1284197 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11946960 # number of integer instructions +system.cpu1.num_fp_insts 174217 # number of float instructions +system.cpu1.num_int_register_reads 16422187 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8787604 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written +system.cpu1.num_mem_refs 4116157 # number of memory refs +system.cpu1.num_load_insts 2399132 # Number of load instructions +system.cpu1.num_store_insts 1717025 # Number of store instructions +system.cpu1.num_idle_cycles 3872385828.119347 # Number of idle cycles +system.cpu1.num_busy_cycles 49495075.880653 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012620 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987380 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2329 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 33659 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 8392 30.97% 30.97% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 7.27% 38.24% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.32% 38.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 16645 61.43% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 27095 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 8384 44.74% 44.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 10.51% 55.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.47% 55.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 8296 44.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 18738 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917649813500 97.79% 97.79% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700167000 0.04% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 60318500 0.00% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42533179500 2.17% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1960943478500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999047 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2742 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78306 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26634 38.27% 38.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40476 58.16% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69596 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25767 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25250 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53503 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909643308000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700945000 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 361639500 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50234529500 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960940422000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967448 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.498408 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.691567 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.623826 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.768765 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1352,81 +1416,81 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 283 1.02% 1.06% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.07% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.03% 1.09% # number of callpals executed -system.cpu1.kern.callpal::swpipl 22604 81.73% 82.82% # number of callpals executed -system.cpu1.kern.callpal::rdps 2147 7.76% 90.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 90.60% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.61% # number of callpals executed -system.cpu1.kern.callpal::rti 2432 8.79% 99.41% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.44% 99.84% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2001 2.78% 3.39% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63390 88.19% 91.60% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 2.99% 94.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed +system.cpu1.kern.callpal::rti 3719 5.17% 99.77% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 27656 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 652 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 379 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 12 -system.cpu1.kern.mode_switch_good::kernel 0.581288 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71875 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches +system.cpu1.kern.mode_switch::user 368 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2907 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 809 +system.cpu1.kern.mode_good::user 368 +system.cpu1.kern.mode_good::idle 441 +system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.005811 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.245785 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2892019000 0.15% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 284 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 79630 # number of replacements -system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 4672446 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 4672446 # number of overall hits -system.cpu1.icache.overall_hits::total 4672446 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 80179 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 80179 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 80179 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 80179 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 80179 # number of overall misses -system.cpu1.icache.overall_misses::total 80179 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1082064992 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1082064992 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1082064992 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1082064992 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1082064992 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1082064992 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 4752625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 4752625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 4752625 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 4752625 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 4752625 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 4752625 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016870 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016870 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016870 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016870 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016870 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016870 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13495.615959 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13495.615959 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13495.615959 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13495.615959 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.151703 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.309310 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17986321500 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1483696000 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1940592550000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2002 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 317593 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.454785 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12652531 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 318104 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.774825 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1959964216000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.454785 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871982 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.871982 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12652531 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12652531 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12652531 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12652531 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12652531 # number of overall hits +system.cpu1.icache.overall_hits::total 12652531 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 318144 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 318144 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 318144 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 318144 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 318144 # number of overall misses +system.cpu1.icache.overall_misses::total 318144 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4187615492 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4187615492 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4187615492 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4187615492 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4187615492 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4187615492 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12970675 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12970675 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12970675 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12970675 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12970675 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12970675 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024528 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024528 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024528 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024528 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024528 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13162.641735 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13162.641735 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13162.641735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13162.641735 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1435,112 +1499,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 80179 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 80179 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 80179 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 80179 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 80179 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 80179 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 921458008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 921458008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 921458008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 921458008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 921458008 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 921458008 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016870 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016870 # 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number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 318144 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 318144 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 318144 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3551128508 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3551128508 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3551128508 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3551128508 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3551128508 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3551128508 # 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average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11162.016282 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 40890 # number of replacements -system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 531046 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 9250 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 9250 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 9554 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 9554 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1448467 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1448467 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1448467 # number of overall hits -system.cpu1.dcache.overall_hits::total 1448467 # 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number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 45308 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 45308 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 334917000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 334917000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 427133505 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 427133505 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 7677750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 7677750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2708927 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2708927 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 762050505 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 762050505 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 762050505 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 762050505 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18768000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 527878500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 527878500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 546646500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 546646500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033675 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033675 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024499 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.024499 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.084158 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.084158 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.049259 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030331 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030331 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10475.649808 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10475.649808 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32026.205668 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32026.205668 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.647059 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9032.647059 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.579798 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5472.579798 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 109639 # number of writebacks +system.cpu1.dcache.writebacks::total 109639 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116850 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 116850 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57159 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 57159 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9086 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9086 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6023 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6023 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 174009 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 174009 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 174009 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 174009 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1177711751 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1177711751 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 928682973 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 928682973 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64347500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64347500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32228573 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32228573 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2106394724 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2106394724 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2106394724 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2106394724 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18769000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18769000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718428000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718428000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737197000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737197000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034576 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034576 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159069 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159069 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106338 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106338 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043584 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043584 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10078.833984 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10078.833984 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16247.362148 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16247.362148 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7082.049307 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7082.049307 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5350.916985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5350.916985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 0de871519..479e1f707 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,123 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.918473 # Number of seconds simulated -sim_ticks 1918473094000 # Number of ticks simulated -final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920428 # Number of seconds simulated +sim_ticks 1920428041000 # Number of ticks simulated +final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 948634 # Simulator instruction rate (inst/s) -host_op_rate 948634 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32389976926 # Simulator tick rate (ticks/s) -host_mem_usage 304780 # Number of bytes of host memory used -host_seconds 59.23 # Real time elapsed on the host -sim_insts 56188014 # Number of instructions simulated -sim_ops 56188014 # Number of ops (including micro ops) simulated +host_inst_rate 1218375 # Simulator instruction rate (inst/s) +host_op_rate 1218374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41646226437 # Simulator tick rate (ticks/s) +host_mem_usage 305884 # Number of bytes of host memory used +host_seconds 46.11 # Real time elapsed on the host +sim_insts 56182750 # Number of instructions simulated +sim_ops 56182750 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350528 # Number of bytes read from this memory +system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7389888 # Number of bytes written to this memory -system.physmem.bytes_written::total 7389888 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory +system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442977 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115467 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115467 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12951700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1382533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14777652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3851963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3851963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3851963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28350528 # Total number of bytes read from memory -system.physmem.bytesWritten 7389888 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 26911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 26768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28025 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28266 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7594 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7543 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6467 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6223 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6661 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6780 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7013 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7721 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7822 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1918461222000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 442977 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 115467 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 402244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 442968 # Number of read requests accepted +system.physmem.writeReqs 115466 # Number of write requests accepted +system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue +system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 27966 # Per bank write bursts +system.physmem.perBankRdBursts::1 28089 # Per bank write bursts +system.physmem.perBankRdBursts::2 28297 # Per bank write bursts +system.physmem.perBankRdBursts::3 28053 # Per bank write bursts +system.physmem.perBankRdBursts::4 27407 # Per bank write bursts +system.physmem.perBankRdBursts::5 27545 # Per bank write bursts +system.physmem.perBankRdBursts::6 26911 # Per bank write bursts +system.physmem.perBankRdBursts::7 26762 # Per bank write bursts +system.physmem.perBankRdBursts::8 27807 # Per bank write bursts +system.physmem.perBankRdBursts::9 27255 # Per bank write bursts +system.physmem.perBankRdBursts::10 27714 # Per bank write bursts +system.physmem.perBankRdBursts::11 27327 # Per bank write bursts +system.physmem.perBankRdBursts::12 27431 # Per bank write bursts +system.physmem.perBankRdBursts::13 28073 # Per bank write bursts +system.physmem.perBankRdBursts::14 28024 # Per bank write bursts +system.physmem.perBankRdBursts::15 28256 # Per bank write bursts +system.physmem.perBankWrBursts::0 7722 # Per bank write bursts +system.physmem.perBankWrBursts::1 7593 # Per bank write bursts +system.physmem.perBankWrBursts::2 7833 # Per bank write bursts +system.physmem.perBankWrBursts::3 7543 # Per bank write bursts +system.physmem.perBankWrBursts::4 7010 # Per bank write bursts +system.physmem.perBankWrBursts::5 6982 # Per bank write bursts +system.physmem.perBankWrBursts::6 6469 # Per bank write bursts +system.physmem.perBankWrBursts::7 6223 # Per bank write bursts +system.physmem.perBankWrBursts::8 7224 # Per bank write bursts +system.physmem.perBankWrBursts::9 6661 # Per bank write bursts +system.physmem.perBankWrBursts::10 7099 # Per bank write bursts +system.physmem.perBankWrBursts::11 6780 # Per bank write bursts +system.physmem.perBankWrBursts::12 7009 # Per bank write bursts +system.physmem.perBankWrBursts::13 7722 # Per bank write bursts +system.physmem.perBankWrBursts::14 7773 # Per bank write bursts +system.physmem.perBankWrBursts::15 7817 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1920416169000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 442968 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 115466 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -129,233 +131,289 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 962.378541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.718891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2449.750918 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13161 35.44% 35.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5591 15.06% 50.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3357 9.04% 59.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2263 6.09% 65.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1589 4.28% 69.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1303 3.51% 73.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 971 2.61% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 731 1.97% 78.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 647 1.74% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 569 1.53% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 543 1.46% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 425 1.14% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 308 0.83% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 237 0.64% 85.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 163 0.44% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 235 0.63% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 101 0.27% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 93 0.25% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 98 0.26% 87.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 98 0.26% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 85 0.23% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 107 0.29% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1046 2.82% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 157 0.42% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 87 0.23% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 55 0.15% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 46 0.12% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 40 0.11% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 31 0.08% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 18 0.05% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 16 0.04% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 26 0.07% 92.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 8 0.02% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 8 0.02% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 15 0.04% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 14 0.04% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 2 0.01% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 3 0.01% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 4 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 2 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.01% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2437 6.56% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 242 0.65% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 9 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 2 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 2 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37132 # Bytes accessed per row activation -system.physmem.totQLat 3659130000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11798708750 # Sum of mem lat for all requests -system.physmem.totBusLat 2214635000 # Total cycles spent in databus access -system.physmem.totBankLat 5924943750 # Total cycles spent in bank access -system.physmem.avgQLat 8261.25 # Average queueing delay per request -system.physmem.avgBankLat 13376.80 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26638.04 # Average memory access latency -system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.85 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation +system.physmem.totQLat 6257775000 # Total ticks spent queuing +system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks +system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 13.19 # Average write queue length over time -system.physmem.readRowHits 427838 # Number of row buffer hits during reads -system.physmem.writeRowHits 93417 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes -system.physmem.avgGap 3435369.03 # Average gap between requests -system.membus.throughput 18671288 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292313 # Transaction distribution -system.membus.trans_dist::ReadResp 292313 # Transaction distribution -system.membus.trans_dist::WriteReq 9649 # Transaction distribution -system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 115467 # Transaction distribution +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing +system.physmem.readRowHits 419360 # Number of row buffer hits during reads +system.physmem.writeRowHits 92763 # Number of row buffer hits during writes +system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes +system.physmem.avgGap 3438931.31 # Average gap between requests +system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18651952 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292310 # Transaction distribution +system.membus.trans_dist::ReadResp 292310 # Transaction distribution +system.membus.trans_dist::WriteReq 9650 # Transaction distribution +system.membus.trans_dist::WriteResp 9650 # Transaction distribution +system.membus.trans_dist::Writeback 115466 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158147 # Transaction distribution -system.membus.trans_dist::ReadExResp 158147 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877556 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 158141 # Transaction distribution +system.membus.trans_dist::ReadExResp 158141 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35784972 # Total data (bytes) +system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35784340 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32373000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1487941500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3745756604 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -364,14 +422,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21343633 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21343633 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10434225282 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10434225282 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10455568915 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10455568915 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10455568915 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10455568915 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -388,19 +446,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123373.601156 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123373.601156 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251112.468281 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251112.468281 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250582.837987 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250582.837987 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 272640 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27184 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.029429 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -414,14 +472,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8272160782 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8272160782 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8284506915 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8284506915 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8284506915 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8284506915 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +488,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199079.726174 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199079.726174 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +513,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9065600 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9064966 # DTB read hits +system.cpu.dtb.read_misses 10312 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6356756 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728817 # DTB read accesses +system.cpu.dtb.write_hits 6356267 # DTB write hits +system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15422356 # DTB hits -system.cpu.dtb.data_misses 11466 # DTB misses +system.cpu.dtb.write_accesses 291929 # DTB write accesses +system.cpu.dtb.data_hits 15421233 # DTB hits +system.cpu.dtb.data_misses 11452 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020784 # DTB accesses -system.cpu.itb.fetch_hits 4974352 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.dtb.data_accesses 1020746 # DTB accesses +system.cpu.itb.fetch_hits 4973920 # ITB hits +system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979362 # ITB accesses +system.cpu.itb.fetch_accesses 4978917 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -483,51 +541,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3836946188 # number of cpu cycles simulated +system.cpu.numCycles 3840856082 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56188014 # Number of instructions committed -system.cpu.committedOps 56188014 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52059797 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses -system.cpu.num_func_calls 1483456 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468822 # number of instructions that are conditional controls -system.cpu.num_int_insts 52059797 # number of integer instructions -system.cpu.num_fp_insts 324527 # number of float instructions -system.cpu.num_int_register_reads 71330046 # number of times the integer registers were read -system.cpu.num_int_register_writes 38525190 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written -system.cpu.num_mem_refs 15474978 # number of memory refs -system.cpu.num_load_insts 9102456 # Number of load instructions -system.cpu.num_store_insts 6372522 # Number of store instructions -system.cpu.num_idle_cycles 3586988416.498130 # Number of idle cycles -system.cpu.num_busy_cycles 249957771.501870 # Number of busy cycles -system.cpu.not_idle_fraction 0.065145 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934855 # Percentage of idle cycles +system.cpu.committedInsts 56182750 # Number of instructions committed +system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses +system.cpu.num_func_calls 1483342 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054772 # number of integer instructions +system.cpu.num_fp_insts 324326 # number of float instructions +system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read +system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written +system.cpu.num_mem_refs 15473812 # number of memory refs +system.cpu.num_load_insts 9101789 # Number of load instructions +system.cpu.num_store_insts 6372023 # Number of store instructions +system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934400 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211982 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74893 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106209 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183164 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73526 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73526 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149114 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857159489000 96.80% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91367000 0.00% 96.81% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736929000 0.04% 96.85% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 60484575000 3.15% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1918472360000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692277 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814101 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -563,33 +621,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175945 91.21% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192891 # number of callpals executed +system.cpu.kern.callpal::total 192898 # number of callpals executed system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46124802000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5245072500 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1867102483500 97.32% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4176 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -621,12 +679,12 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1410582 # Throughput (bytes/s) +system.iobus.throughput 1409150 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51201 # Transaction distribution -system.iobus.trans_dist::WriteResp 51201 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51202 # Transaction distribution +system.iobus.trans_dist::WriteResp 51202 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -638,11 +696,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -654,12 +712,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2706164 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2706172 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -681,59 +739,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378268915 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 928665 # number of replacements -system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55270512 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55270512 # number of overall hits -system.cpu.icache.overall_hits::total 55270512 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929336 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929336 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929336 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929336 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929336 # number of overall misses -system.cpu.icache.overall_misses::total 929336 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13015346257 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13015346257 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13015346257 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13015346257 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13015346257 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13015346257 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56199848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56199848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56199848 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56199848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56199848 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56199848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016536 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016536 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016536 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016536 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016536 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016536 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14004.995241 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14004.995241 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14004.995241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14004.995241 # average overall miss latency +system.cpu.icache.tags.replacements 928358 # number of replacements +system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits +system.cpu.icache.overall_hits::total 55265541 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses +system.cpu.icache.overall_misses::total 929029 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56194570 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56194570 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56194570 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56194570 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56194570 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -742,126 +800,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929336 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929336 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929336 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929336 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11150220743 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11150220743 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11150220743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11150220743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11150220743 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11150220743 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016536 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016536 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016536 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.051020 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.051020 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929029 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929029 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929029 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929029 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929029 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929029 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11098555742 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11098555742 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11098555742 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11098555742 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11098555742 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11098555742 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11946.403979 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11946.403979 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336065 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173191 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173191 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67190.284156 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49740.362006 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50553.602654 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57678.065137 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -937,79 +995,79 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390866 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120380 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120380 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049437 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049437 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091341 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091341 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091341 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091341 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29050.711070 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29050.711070 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1018,54 +1076,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835407 # number of writebacks -system.cpu.dcache.writebacks::total 835407 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069668 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069668 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304510 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374178 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374178 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374178 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374178 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25967193744 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25967193744 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9940394617 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9940394617 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194939500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194939500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35907588361 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 35907588361 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35907588361 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 35907588361 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424233500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424233500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435453000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435453000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120394 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120394 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085985 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085985 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091357 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091357 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24275.937715 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24275.937715 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32643.902062 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32643.902062 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.185899 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.185899 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks +system.cpu.dcache.writebacks::total 835114 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304370 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304370 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17259 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17259 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373840 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373840 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373840 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373840 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26604805241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26604805241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10372104863 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10372104863 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194393750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194393750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36976910104 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36976910104 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36976910104 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36976910104 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120380 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1073,31 +1131,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105316327 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2023326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023309 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835407 # Transaction distribution +system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1397230757 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194639139 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 643b5e070..951921c42 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,148 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.194884 # Number of seconds simulated -sim_ticks 1194883580500 # Number of ticks simulated -final_tick 1194883580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.195756 # Number of seconds simulated +sim_ticks 1195756323500 # Number of ticks simulated +final_tick 1195756323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 298011 # Simulator instruction rate (inst/s) -host_op_rate 379758 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5802481089 # Simulator tick rate (ticks/s) -host_mem_usage 399660 # Number of bytes of host memory used -host_seconds 205.93 # Real time elapsed on the host -sim_insts 61368273 # Number of instructions simulated -sim_ops 78202205 # Number of ops (including micro ops) simulated +host_inst_rate 469394 # Simulator instruction rate (inst/s) +host_op_rate 598174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9145402965 # Simulator tick rate (ticks/s) +host_mem_usage 398732 # Number of bytes of host memory used +host_seconds 130.75 # Real time elapsed on the host +sim_insts 61373013 # Number of instructions simulated +sim_ops 78210923 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6626292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 463908 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6634996 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory -system.physmem.bytes_read::total 62155300 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4136384 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2903984 # Number of bytes read from this memory +system.physmem.bytes_read::total 62164260 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463908 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 720320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4143232 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7163728 # Number of bytes written to this memory +system.physmem.bytes_written::total 7170576 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103744 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654631 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64631 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45401 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654771 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64738 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821467 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43438970 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821574 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43407265 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 388085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5545554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 387962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5548786 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2430563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52017871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 388085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3461746 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2533556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2428575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51987398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 387962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3464947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2531706 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5995336 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3461746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43438970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 5996687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3464947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43407265 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 388085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8079110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 387962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8080492 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2430597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58013207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654631 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 821467 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 6654631 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 821467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 425896384 # Total number of bytes read from memory -system.physmem.bytesWritten 52573888 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62155300 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7163728 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 531 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 10643 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 422327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415446 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 414743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415731 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7326 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7216 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6699 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6873 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7393 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7176 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6994 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 6995 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6985 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6704 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7238 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7541 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7391 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7368 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1194879167500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6825 # Categorize read packet sizes -system.physmem.readPktSize::3 6488064 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159742 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 756836 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64631 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 586175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 426728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 441027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1598520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1190036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1186243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1162812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 12576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see +system.physmem.bw_total::cpu1.inst 214435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2428609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57984085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654771 # Number of read requests accepted +system.physmem.writeReqs 821574 # Number of write requests accepted +system.physmem.readBursts 6654771 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821574 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425880832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7300224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62164260 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7170576 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 383 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707506 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 10656 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415729 # Per bank write bursts +system.physmem.perBankRdBursts::1 415559 # Per bank write bursts +system.physmem.perBankRdBursts::2 414962 # Per bank write bursts +system.physmem.perBankRdBursts::3 415336 # Per bank write bursts +system.physmem.perBankRdBursts::4 422370 # Per bank write bursts +system.physmem.perBankRdBursts::5 415375 # Per bank write bursts +system.physmem.perBankRdBursts::6 415451 # Per bank write bursts +system.physmem.perBankRdBursts::7 415289 # Per bank write bursts +system.physmem.perBankRdBursts::8 415350 # Per bank write bursts +system.physmem.perBankRdBursts::9 415631 # Per bank write bursts +system.physmem.perBankRdBursts::10 415265 # Per bank write bursts +system.physmem.perBankRdBursts::11 414898 # Per bank write bursts +system.physmem.perBankRdBursts::12 415464 # Per bank write bursts +system.physmem.perBankRdBursts::13 416088 # Per bank write bursts +system.physmem.perBankRdBursts::14 415829 # Per bank write bursts +system.physmem.perBankRdBursts::15 415792 # Per bank write bursts +system.physmem.perBankWrBursts::0 7314 # Per bank write bursts +system.physmem.perBankWrBursts::1 7200 # Per bank write bursts +system.physmem.perBankWrBursts::2 6696 # Per bank write bursts +system.physmem.perBankWrBursts::3 6864 # Per bank write bursts +system.physmem.perBankWrBursts::4 7395 # Per bank write bursts +system.physmem.perBankWrBursts::5 6961 # Per bank write bursts +system.physmem.perBankWrBursts::6 7170 # Per bank write bursts +system.physmem.perBankWrBursts::7 6990 # Per bank write bursts +system.physmem.perBankWrBursts::8 6985 # Per bank write bursts +system.physmem.perBankWrBursts::9 7249 # Per bank write bursts +system.physmem.perBankWrBursts::10 6972 # Per bank write bursts +system.physmem.perBankWrBursts::11 6687 # Per bank write bursts +system.physmem.perBankWrBursts::12 7224 # Per bank write bursts +system.physmem.perBankWrBursts::13 7527 # Per bank write bursts +system.physmem.perBankWrBursts::14 7429 # Per bank write bursts +system.physmem.perBankWrBursts::15 7403 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1195751937000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 6825 # Read request sizes (log2) +system.physmem.readPktSize::3 6488064 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 159882 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 64738 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 632405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 479192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 479926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1578313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1129029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1122994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1119651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -157,31 +159,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -189,282 +191,423 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 12682.337813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 707.328285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 25224.390929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 7803 22.85% 22.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 4015 11.76% 34.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2702 7.91% 42.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1928 5.64% 48.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1397 4.09% 52.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1203 3.52% 55.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 946 2.77% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 826 2.42% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 667 1.95% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 557 1.63% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 438 1.28% 65.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 432 1.26% 67.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 317 0.93% 68.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 252 0.74% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 181 0.53% 69.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 297 0.87% 70.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 146 0.43% 70.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 131 0.38% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 122 0.36% 71.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 99 0.29% 71.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 97 0.28% 71.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 161 0.47% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 728 2.13% 74.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 239 0.70% 75.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 168 0.49% 75.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 146 0.43% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 103 0.30% 76.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 87 0.25% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 68 0.20% 76.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 55 0.16% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 40 0.12% 77.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 46 0.13% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 38 0.11% 77.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 21 0.06% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 23 0.07% 77.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 20 0.06% 77.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 20 0.06% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 20 0.06% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 23 0.07% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 11 0.03% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 12 0.04% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 19 0.06% 77.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 8 0.02% 77.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 17 0.05% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 10 0.03% 77.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 5 0.01% 78.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 78.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 13 0.04% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 2 0.01% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 15 0.04% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 7 0.02% 78.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 12 0.04% 78.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 12 0.04% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 8 0.02% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 8 0.02% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 11 0.03% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 11 0.03% 78.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 6 0.02% 78.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 9 0.03% 78.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 11 0.03% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 7 0.02% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 32 0.09% 78.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 3 0.01% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 6 0.02% 78.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 3 0.01% 78.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 3 0.01% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 7 0.02% 78.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 5 0.01% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 6 0.02% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 4 0.01% 78.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 5 0.01% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 2 0.01% 78.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 1 0.00% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 4 0.01% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 2 0.01% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 3 0.01% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 4 0.01% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 1 0.00% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 2 0.01% 78.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 4 0.01% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 5 0.01% 78.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 1 0.00% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 2 0.01% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 2 0.01% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 1 0.00% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 4 0.01% 78.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 1 0.00% 78.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 22 0.06% 78.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 1 0.00% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 5 0.01% 78.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 7 0.02% 78.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7359 3 0.01% 79.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 2 0.01% 79.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 6 0.02% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 7 0.02% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 1 0.00% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 9 0.03% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 6 0.02% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 323 0.95% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8319 1 0.00% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 25 0.07% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8575 138 0.40% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 174 0.51% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 2 0.01% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 1 0.00% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8959 1 0.00% 81.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9471 1 0.00% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10047 3 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 1 0.00% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10815 2 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11071 1 0.00% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 4 0.01% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11839 2 0.01% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 1 0.00% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12351 2 0.01% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12607 1 0.00% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12863 3 0.01% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 3 0.01% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13631 1 0.00% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14271 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14911 3 0.01% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15167 2 0.01% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 5 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15679 1 0.00% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16703 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16959 1 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 4 0.01% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 3 0.01% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18751 1 0.00% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-19007 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19199 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19391 1 0.00% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 3 0.01% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 2 0.01% 81.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-20031 2 0.01% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 4 0.01% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 1 0.00% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21311 3 0.01% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 5 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22335 1 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 2 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 3 0.01% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 1 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 2 0.01% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25151 1 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26175 2 0.01% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26431 1 0.00% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 3 0.01% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 4 0.01% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 2 0.01% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 3 0.01% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29503 1 0.00% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 4 0.01% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 3 0.01% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 3 0.01% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 2 0.01% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 3 0.01% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 4 0.01% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 11 0.03% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 42 0.12% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33855 1 0.00% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34111 1 0.00% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34112-34175 1 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35135 1 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36927 1 0.00% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37183 1 0.00% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37951 2 0.01% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38207 1 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38975 1 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41535 1 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42303 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44095 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44863 1 0.00% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45119 2 0.01% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45631 1 0.00% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45887 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46271 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48959 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49471 1 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 2 0.01% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50751 1 0.00% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51328-51391 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52287 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52480-52543 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52992-53055 1 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53311 2 0.01% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55552-55615 1 0.00% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56128-56191 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57088-57151 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58175 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58431 1 0.00% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59455 1 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60928-60991 1 0.00% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61952-62015 1 0.00% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62720-62783 1 0.00% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63680-63743 1 0.00% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 39 0.11% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 6180 18.09% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66880-66943 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66944-67007 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::67904-67967 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74048-74111 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74112-74175 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34155 # Bytes accessed per row activation -system.physmem.totQLat 126519681500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 168380906500 # Sum of mem lat for all requests -system.physmem.totBusLat 33270500000 # Total cycles spent in databus access -system.physmem.totBankLat 8590725000 # Total cycles spent in bank access -system.physmem.avgQLat 19013.79 # Average queueing delay per request -system.physmem.avgBankLat 1291.04 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25304.84 # Average memory access latency -system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.13 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 14.04 # Average write queue length over time -system.physmem.readRowHits 6636405 # Number of row buffer hits during reads -system.physmem.writeRowHits 97666 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.89 # Row buffer hit rate for writes -system.physmem.avgGap 159826.58 # Average gap between requests +system.physmem.bytesPerActivate::samples 75043 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5772.432765 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 392.553072 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 13030.260865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 26180 34.89% 34.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 15268 20.35% 55.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3440 4.58% 59.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2311 3.08% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1510 2.01% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1328 1.77% 66.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1040 1.39% 68.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1132 1.51% 69.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 816 1.09% 70.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 593 0.79% 71.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 586 0.78% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 709 0.94% 73.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 314 0.42% 73.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 269 0.36% 73.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 220 0.29% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 291 0.39% 74.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 182 0.24% 74.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 143 0.19% 75.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 140 0.19% 75.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 157 0.21% 75.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2241 2.99% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 115 0.15% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 232 0.31% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 71 0.09% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 55 0.07% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 54 0.07% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 56 0.07% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 28 0.04% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 107 0.14% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 143 0.19% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 11 0.01% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 15 0.02% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 43 0.06% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 9 0.01% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 16 0.02% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 18 0.02% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 98 0.13% 80.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 8 0.01% 80.11% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 6 0.01% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 16 0.02% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 2 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 6 0.01% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 30 0.04% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 86 0.11% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 3 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 188 0.25% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 2 0.00% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 22 0.03% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 27 0.04% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 207 0.28% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 1 0.00% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 13 0.02% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 90 0.12% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 1 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 76 0.10% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 12 0.02% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 206 0.27% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 11 0.01% 82.10% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 161 0.21% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 26 0.03% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 70 0.09% 83.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 24 0.03% 83.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 2 0.00% 83.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 167 0.22% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 10 0.01% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 21 0.03% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 83 0.11% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 148 0.20% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10311 1 0.00% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 31 0.04% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 9 0.01% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 1 0.00% 83.91% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 83 0.11% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 12 0.02% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 24 0.03% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13255 1 0.00% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 154 0.21% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13447 2 0.00% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 30 0.04% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13639 1 0.00% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 90 0.12% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 1 0.00% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 16 0.02% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 91 0.12% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 1 0.00% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 14 0.02% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 2 0.00% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 154 0.21% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 12 0.02% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 76 0.10% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 82 0.11% 85.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 16 0.02% 85.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 19 0.03% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 4 0.01% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 270 0.36% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16775 2 0.00% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 17 0.02% 86.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 84 0.11% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 77 0.10% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 12 0.02% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 2 0.00% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 156 0.21% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 14 0.02% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 92 0.12% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18496-18503 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 12 0.02% 86.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 95 0.13% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 30 0.04% 86.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19264-19271 1 0.00% 86.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 153 0.20% 87.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 23 0.03% 87.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 10 0.01% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 83 0.11% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 180 0.24% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20551 2 0.00% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 18 0.02% 87.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20800-20807 1 0.00% 87.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 25 0.03% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21184-21191 1 0.00% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 75 0.10% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21440-21447 1 0.00% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 92 0.12% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21952-21959 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 14 0.02% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 35 0.05% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 142 0.19% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22663 1 0.00% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 87 0.12% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22976-22983 1 0.00% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 4 0.01% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 166 0.22% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 23 0.03% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 66 0.09% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 30 0.04% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 147 0.20% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 27 0.04% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 68 0.09% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 24 0.03% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 1 0.00% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 171 0.23% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 5 0.01% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 19 0.03% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 83 0.11% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 139 0.19% 89.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 34 0.05% 89.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 75 0.10% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 2 0.00% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 88 0.12% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 2 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 75 0.10% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28103 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 24 0.03% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 21 0.03% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 180 0.24% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 2 0.00% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 82 0.11% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 10 0.01% 90.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 24 0.03% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 153 0.20% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 28 0.04% 90.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 92 0.12% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 14 0.02% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 87 0.12% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 12 0.02% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 151 0.20% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 11 0.01% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 72 0.10% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 84 0.11% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 15 0.02% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 24 0.03% 91.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 273 0.36% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 27 0.04% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 28 0.04% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 83 0.11% 92.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 70 0.09% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 13 0.02% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 153 0.20% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 13 0.02% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 85 0.11% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 13 0.02% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 90 0.12% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 32 0.04% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 150 0.20% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 9 0.01% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 172 0.23% 93.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 19 0.03% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 1 0.00% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 2 0.00% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 23 0.03% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 70 0.09% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 89 0.12% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 2 0.00% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 74 0.10% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 31 0.04% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 140 0.19% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 81 0.11% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 14 0.02% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 5 0.01% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 169 0.23% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 1 0.00% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 23 0.03% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 29 0.04% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 152 0.20% 94.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 26 0.03% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 66 0.09% 94.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 22 0.03% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41920-41927 1 0.00% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 165 0.22% 94.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 4 0.01% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 13 0.02% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42560-42567 1 0.00% 94.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 87 0.12% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 139 0.19% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 32 0.04% 95.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43584-43591 1 0.00% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 72 0.10% 95.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 72 0.10% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 22 0.03% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44736-44743 1 0.00% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 1 0.00% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 169 0.23% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 83 0.11% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 7 0.01% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 22 0.03% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 150 0.20% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 96 0.13% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 12 0.02% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 92 0.12% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 3 0.00% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 18 0.02% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 2 0.00% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 154 0.21% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 17 0.02% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 94 0.13% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 97 0.13% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 12 0.02% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 17 0.02% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 9 0.01% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 6 0.01% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2103 2.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49792-49799 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75043 # Bytes accessed per row activation +system.physmem.totQLat 159590177750 # Total ticks spent queuing +system.physmem.totMemAccLat 202588661500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33271940000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9726543750 # Total ticks spent accessing banks +system.physmem.avgQLat 23982.70 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1461.67 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30444.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.83 # Data bus utilization in percentage +system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.10 # Average write queue length when enqueuing +system.physmem.readRowHits 6598517 # Number of row buffer hits during reads +system.physmem.writeRowHits 94894 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.19 # Row buffer hit rate for writes +system.physmem.avgGap 159938.04 # Average gap between requests +system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.89 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -483,286 +626,286 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 60029719 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703148 # Transaction distribution -system.membus.trans_dist::ReadResp 7703148 # Transaction distribution -system.membus.trans_dist::WriteReq 767203 # Transaction distribution -system.membus.trans_dist::WriteResp 767203 # Transaction distribution -system.membus.trans_dist::Writeback 64631 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27692 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16414 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10643 # Transaction distribution -system.membus.trans_dist::ReadExReq 137763 # Transaction distribution -system.membus.trans_dist::ReadExResp 137302 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382562 # Packet count per connected master and slave (bytes) +system.membus.throughput 59999152 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703168 # Transaction distribution +system.membus.trans_dist::ReadResp 7703168 # Transaction distribution +system.membus.trans_dist::WriteReq 767205 # Transaction distribution +system.membus.trans_dist::WriteResp 767205 # Transaction distribution +system.membus.trans_dist::Writeback 64738 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27605 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16481 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10656 # Transaction distribution +system.membus.trans_dist::ReadExReq 137900 # Transaction distribution +system.membus.trans_dist::ReadExResp 137428 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4359019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4359426 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335147 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389878 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17335554 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17732 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414516 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19824014 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17430324 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19839854 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71728526 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71728526 # Total data (bytes) +system.membus.tot_pkt_size::total 71744366 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71744366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1208318500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1219669500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7968000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7974500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 776500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9149406000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9159249500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5034563338 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5040906450 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14646378749 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657427498 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 69624 # number of replacements -system.l2c.tags.tagsinuse 53154.717455 # Cycle average of tags in use -system.l2c.tags.total_refs 1650852 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134785 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.248039 # Average number of references to valid blocks. +system.l2c.tags.replacements 69764 # number of replacements +system.l2c.tags.tagsinuse 53155.979727 # Cycle average of tags in use +system.l2c.tags.total_refs 1654767 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134953 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.261802 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40039.692381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667893 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4638.680952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5789.816440 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1927.067698 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 756.788910 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.610957 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 40044.748185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4637.745622 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016760 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018067 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.755732 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.882138 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.808933 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.590840 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830156 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702922 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592083 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.496123 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.557684 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108667 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108667 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63169.701337 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67697.542283 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61549.990959 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.407974 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10039.718297 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10024.942342 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.501292 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.611691 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10016.009238 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56187.238680 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64785.004126 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58929.114754 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -944,64 +1087,64 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118384606 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2504676 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2504676 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767203 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767203 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576006 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 26963 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16769 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43732 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262452 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262452 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951029 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5836 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14921 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753525 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879302 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6196 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11995 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7616516 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31376632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53718524 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24082060 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27916814 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 137140510 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137140510 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4315312 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4764811697 # Layer occupancy (ticks) +system.toL2Bus.throughput 118413539 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2505894 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2505894 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576824 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 26927 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16847 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262598 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262598 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 994053 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951842 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5908 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15091 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 754073 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2881163 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6136 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11790 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7620056 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31386872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53739672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24100876 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 28000722 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7240 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 14248 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 137274438 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137274438 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4319300 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4769236119 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2217607730 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2218068983 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2471552710 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2472016836 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10394000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 10401000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1697838714 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1698781961 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2214012427 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 2209782432 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 8228499 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45439063 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671399 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671399 # Transaction distribution +system.iobus.throughput 45405912 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution system.iobus.trans_dist::WriteResp 7946 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) @@ -1021,14 +1164,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382562 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382570 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358690 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 15358698 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16132 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) @@ -1048,18 +1191,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389878 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294390 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294390 # Total data (bytes) +system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294406 # Total data (bytes) system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4039000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1101,32 +1244,32 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374616000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17783069251 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17778330502 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9653247 # DTB read hits -system.cpu0.dtb.read_misses 3738 # DTB read misses -system.cpu0.dtb.write_hits 7597488 # DTB write hits -system.cpu0.dtb.write_misses 1585 # DTB write misses +system.cpu0.dtb.read_hits 9652613 # DTB read hits +system.cpu0.dtb.read_misses 3746 # DTB read misses +system.cpu0.dtb.write_hits 7596890 # DTB write hits +system.cpu0.dtb.write_misses 1582 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9656985 # DTB read accesses -system.cpu0.dtb.write_accesses 7599073 # DTB write accesses +system.cpu0.dtb.read_accesses 9656359 # DTB read accesses +system.cpu0.dtb.write_accesses 7598472 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17250735 # DTB hits -system.cpu0.dtb.misses 5323 # DTB misses -system.cpu0.dtb.accesses 17256058 # DTB accesses -system.cpu0.itb.inst_hits 43297764 # ITB inst hits +system.cpu0.dtb.hits 17249503 # DTB hits +system.cpu0.dtb.misses 5328 # DTB misses +system.cpu0.dtb.accesses 17254831 # DTB accesses +system.cpu0.itb.inst_hits 43298526 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1143,79 +1286,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43299969 # ITB inst accesses -system.cpu0.itb.hits 43297764 # DTB hits +system.cpu0.itb.inst_accesses 43300731 # ITB inst accesses +system.cpu0.itb.hits 43298526 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43299969 # DTB accesses -system.cpu0.numCycles 2389767161 # number of cpu cycles simulated +system.cpu0.itb.accesses 43300731 # DTB accesses +system.cpu0.numCycles 2391512647 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42570861 # Number of instructions committed -system.cpu0.committedOps 53303375 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48060351 # Number of integer alu accesses +system.cpu0.committedInsts 42571581 # Number of instructions committed +system.cpu0.committedOps 53301862 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48058821 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403492 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582702 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48060351 # number of integer instructions +system.cpu0.num_func_calls 1403638 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582830 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48058821 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272449792 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52270848 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272440712 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52270303 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 18020156 # number of memory refs -system.cpu0.num_load_insts 10037111 # Number of load instructions -system.cpu0.num_store_insts 7983045 # Number of store instructions -system.cpu0.num_idle_cycles 2150298949.878201 # Number of idle cycles -system.cpu0.num_busy_cycles 239468211.121800 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100206 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899794 # Percentage of idle cycles +system.cpu0.num_mem_refs 18019009 # number of memory refs +system.cpu0.num_load_insts 10036459 # Number of load instructions +system.cpu0.num_store_insts 7982550 # Number of store instructions +system.cpu0.num_idle_cycles 2151176097.904201 # Number of idle cycles +system.cpu0.num_busy_cycles 240336549.095799 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100496 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899504 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51312 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 490078 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.399401 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 42807156 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 490590 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 87.256479 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76013480250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.399401 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994921 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994921 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 42807156 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42807156 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 42807156 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42807156 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 42807156 # number of overall hits -system.cpu0.icache.overall_hits::total 42807156 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490591 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490591 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490591 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 490591 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 490591 # number of overall misses -system.cpu0.icache.overall_misses::total 490591 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6809993230 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6809993230 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6809993230 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6809993230 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6809993230 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6809993230 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 43297747 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43297747 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 43297747 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43297747 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 43297747 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43297747 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011331 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011331 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011331 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011331 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011331 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011331 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13881.202937 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13881.202937 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13881.202937 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13881.202937 # average overall miss latency +system.cpu0.kern.inst.quiesce 51331 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 490259 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.365280 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 42807737 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490771 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.225482 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76178400000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.365280 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994854 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994854 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42807737 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42807737 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42807737 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42807737 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42807737 # number of overall hits +system.cpu0.icache.overall_hits::total 42807737 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490772 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490772 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490772 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490772 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490772 # number of overall misses +system.cpu0.icache.overall_misses::total 490772 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6820513233 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6820513233 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6820513233 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6820513233 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6820513233 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6820513233 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43298509 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43298509 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43298509 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43298509 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43298509 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43298509 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011335 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011335 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011335 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011335 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011335 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011335 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.519078 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.519078 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13897.519078 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13897.519078 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1224,120 +1367,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490591 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 490591 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 490591 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 490591 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 490591 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 490591 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5825469770 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5825469770 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5825469770 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5825469770 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5825469770 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5825469770 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 415499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 415499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 415499500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 415499500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11874.391846 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490772 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490772 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490772 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490772 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490772 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490772 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5836336767 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5836336767 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5836336767 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5836336767 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5836336767 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5836336767 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011335 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011335 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011335 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11892.155149 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 406634 # number of replacements -system.cpu0.dcache.tags.tagsinuse 471.214045 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 15967998 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 407146 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 39.219341 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 643231250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.214045 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920340 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.920340 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 9137347 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 9137347 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6494912 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6494912 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156532 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 156532 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159004 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 159004 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 15632259 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 15632259 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 15632259 # number of overall hits -system.cpu0.dcache.overall_hits::total 15632259 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 263669 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 263669 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 176685 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 176685 # 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number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6671597 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166442 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 166442 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166388 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 166388 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 16072613 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 16072613 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 16072613 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 16072613 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028047 # 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miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027424 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027424 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14866.791444 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14866.791444 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44670.147868 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44670.147868 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9955.188917 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9955.188917 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5497.898371 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5497.898371 # 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mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40423.275666 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40423.275666 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7956.432896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7956.432896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3489.851606 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3489.851606 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10890401466 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10890401466 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10890401466 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10890401466 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765517500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765517500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807250835 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807250835 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572768335 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572768335 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028088 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059640 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059640 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027424 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027424 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.165854 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.165854 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42418.953310 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42418.953310 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7950.100756 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7950.100756 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.035695 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.035695 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1415,26 +1558,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5705173 # DTB read hits -system.cpu1.dtb.read_misses 3576 # DTB read misses -system.cpu1.dtb.write_hits 3872049 # DTB write hits -system.cpu1.dtb.write_misses 645 # DTB write misses +system.cpu1.dtb.read_hits 5708064 # DTB read hits +system.cpu1.dtb.read_misses 3582 # DTB read misses +system.cpu1.dtb.write_hits 3874465 # DTB write hits +system.cpu1.dtb.write_misses 647 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5708749 # DTB read accesses -system.cpu1.dtb.write_accesses 3872694 # DTB write accesses +system.cpu1.dtb.read_accesses 5711646 # DTB read accesses +system.cpu1.dtb.write_accesses 3875112 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9577222 # DTB hits -system.cpu1.dtb.misses 4221 # DTB misses -system.cpu1.dtb.accesses 9581443 # DTB accesses -system.cpu1.itb.inst_hits 19377969 # ITB inst hits +system.cpu1.dtb.hits 9582529 # DTB hits +system.cpu1.dtb.misses 4229 # DTB misses +system.cpu1.dtb.accesses 9586758 # DTB accesses +system.cpu1.itb.inst_hits 19382020 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1451,79 +1594,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19380140 # ITB inst accesses -system.cpu1.itb.hits 19377969 # DTB hits +system.cpu1.itb.inst_accesses 19384191 # ITB inst accesses +system.cpu1.itb.hits 19382020 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19380140 # DTB accesses -system.cpu1.numCycles 2388332817 # number of cpu cycles simulated +system.cpu1.itb.accesses 19384191 # DTB accesses +system.cpu1.numCycles 2390063941 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18797412 # Number of instructions committed -system.cpu1.committedOps 24898830 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22263010 # Number of integer alu accesses +system.cpu1.committedInsts 18801432 # Number of instructions committed +system.cpu1.committedOps 24909061 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22272671 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796668 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514459 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22263010 # number of integer instructions +system.cpu1.num_func_calls 796781 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514806 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22272671 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130745617 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23316317 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130802029 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23323968 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10012651 # number of memory refs -system.cpu1.num_load_insts 5981805 # Number of load instructions -system.cpu1.num_store_insts 4030846 # Number of store instructions -system.cpu1.num_idle_cycles 1968708722.646828 # Number of idle cycles -system.cpu1.num_busy_cycles 419624094.353172 # Number of busy cycles -system.cpu1.not_idle_fraction 0.175697 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.824303 # Percentage of idle cycles +system.cpu1.num_mem_refs 10017952 # number of memory refs +system.cpu1.num_load_insts 5984754 # Number of load instructions +system.cpu1.num_store_insts 4033198 # Number of store instructions +system.cpu1.num_idle_cycles 1969143633.381917 # Number of idle cycles +system.cpu1.num_busy_cycles 420920307.618083 # Number of busy cycles +system.cpu1.not_idle_fraction 0.176113 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.823887 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39053 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 376539 # number of replacements -system.cpu1.icache.tags.tagsinuse 474.945138 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19000914 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 377051 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 50.393485 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 327002273500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.945138 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927627 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.927627 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19000914 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19000914 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19000914 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19000914 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19000914 # number of overall hits -system.cpu1.icache.overall_hits::total 19000914 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377051 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377051 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377051 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377051 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377051 # number of overall misses -system.cpu1.icache.overall_misses::total 377051 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154764964 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5154764964 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5154764964 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5154764964 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5154764964 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5154764964 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19377965 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19377965 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19377965 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19377965 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19377965 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19377965 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019458 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019458 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019458 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019458 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019458 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019458 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.267187 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.267187 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13671.267187 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13671.267187 # average overall miss latency +system.cpu1.kern.inst.quiesce 39084 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 376793 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.907040 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19004711 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 377305 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 50.369624 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 327169943500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.907040 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927553 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927553 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19004711 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19004711 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19004711 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19004711 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19004711 # number of overall hits +system.cpu1.icache.overall_hits::total 19004711 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377305 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377305 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377305 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377305 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377305 # number of overall misses +system.cpu1.icache.overall_misses::total 377305 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5159789711 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5159789711 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5159789711 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5159789711 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5159789711 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5159789711 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19382016 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19382016 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19382016 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19382016 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19382016 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19382016 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019467 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019467 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019467 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019467 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019467 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019467 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.381219 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13675.381219 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13675.381219 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13675.381219 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1532,120 +1675,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377051 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 377051 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 377051 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 377051 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 377051 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 377051 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398685536 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398685536 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398685536 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4398685536 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398685536 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4398685536 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6184500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6184500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6184500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6184500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019458 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019458 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11666.022729 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377305 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 377305 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 377305 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 377305 # 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number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3492633532 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3492633532 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58449751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58449751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30384025 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30384025 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 200272 # number of writebacks +system.cpu1.dcache.writebacks::total 200272 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134090 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 134090 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112827 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112827 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9762 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9762 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9426 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9426 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246917 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246917 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1388441271 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1388441271 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4117774524 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4117774524 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58015501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58015501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30499022 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30499022 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4873705297 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4873705297 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4873705297 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4873705297 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372112000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372112000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531034000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531034000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903146000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903146000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029784 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029784 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117027 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117027 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113004 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113004 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029671 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.029671 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10325.924612 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10325.924612 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30982.289825 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30982.289825 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6004.083308 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6004.083308 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3234.751943 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3234.751943 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5506215795 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5506215795 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5506215795 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5506215795 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168382941250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168382941250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531038000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531038000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168913979250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168913979250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029790 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029790 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117265 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117265 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113346 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113346 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029706 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029706 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10354.547476 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10354.547476 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36496.357468 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36496.357468 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5942.993342 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5942.993342 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3235.627201 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3235.627201 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1735,10 +1878,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 618710198251 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651875253502 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651875253502 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651875253502 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651875253502 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index efd49eb78..50a428e90 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,130 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.615716 # Number of seconds simulated -sim_ticks 2615716222000 # Number of ticks simulated -final_tick 2615716222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.616536 # Number of seconds simulated +sim_ticks 2616536483000 # Number of ticks simulated +final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 250038 # Simulator instruction rate (inst/s) -host_op_rate 318184 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10864403710 # Simulator tick rate (ticks/s) -host_mem_usage 394540 # Number of bytes of host memory used -host_seconds 240.76 # Real time elapsed on the host -sim_insts 60199078 # Number of instructions simulated -sim_ops 76605946 # Number of ops (including micro ops) simulated +host_inst_rate 552343 # Simulator instruction rate (inst/s) +host_op_rate 702879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24008008080 # Simulator tick rate (ticks/s) +host_mem_usage 395660 # Number of bytes of host memory used +host_seconds 108.99 # Real time elapsed on the host +sim_insts 60197580 # Number of instructions simulated +sim_ops 76603973 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory -system.physmem.bytes_read::total 132482480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 703904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9089744 # Number of bytes read from this memory +system.physmem.bytes_read::total 132477488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 703904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 703904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory +system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17217 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494771 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142061 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494693 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46902409 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3476567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50648644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1418405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153058 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2571462 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1418405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46902409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3473960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50630858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1416443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4629625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53220107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494771 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 811989 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 15494771 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 811989 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 991665344 # Total number of bytes read from memory -system.physmem.bytesWritten 51967296 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132482480 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1656 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 974355 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 968114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967591 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 967810 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967816 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967690 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6734 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6600 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6526 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6493 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6993 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6823 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6694 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6691 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6338 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6636 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6497 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2615711849000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6652 # Categorize read packet sizes -system.physmem.readPktSize::3 15335424 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152695 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754018 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57971 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1137574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 984079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1018155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3783404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2827794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2821787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2781992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 48 # What read queue length does an incoming req see +system.physmem.bw_total::cpu.inst 269021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4626657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53199998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494693 # Number of read requests accepted +system.physmem.writeReqs 811927 # Number of write requests accepted +system.physmem.readBursts 15494693 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991555264 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue +system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132477488 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 967983 # Per bank write bursts +system.physmem.perBankRdBursts::1 967714 # Per bank write bursts +system.physmem.perBankRdBursts::2 967672 # Per bank write bursts +system.physmem.perBankRdBursts::3 967769 # Per bank write bursts +system.physmem.perBankRdBursts::4 974609 # Per bank write bursts +system.physmem.perBankRdBursts::5 968229 # Per bank write bursts +system.physmem.perBankRdBursts::6 967807 # Per bank write bursts +system.physmem.perBankRdBursts::7 967736 # Per bank write bursts +system.physmem.perBankRdBursts::8 968546 # Per bank write bursts +system.physmem.perBankRdBursts::9 968137 # Per bank write bursts +system.physmem.perBankRdBursts::10 967949 # Per bank write bursts +system.physmem.perBankRdBursts::11 967746 # Per bank write bursts +system.physmem.perBankRdBursts::12 967851 # Per bank write bursts +system.physmem.perBankRdBursts::13 967741 # Per bank write bursts +system.physmem.perBankRdBursts::14 967766 # Per bank write bursts +system.physmem.perBankRdBursts::15 967796 # Per bank write bursts +system.physmem.perBankWrBursts::0 6610 # Per bank write bursts +system.physmem.perBankWrBursts::1 6410 # Per bank write bursts +system.physmem.perBankWrBursts::2 6422 # Per bank write bursts +system.physmem.perBankWrBursts::3 6344 # Per bank write bursts +system.physmem.perBankWrBursts::4 6906 # Per bank write bursts +system.physmem.perBankWrBursts::5 7096 # Per bank write bursts +system.physmem.perBankWrBursts::6 6901 # Per bank write bursts +system.physmem.perBankWrBursts::7 6892 # Per bank write bursts +system.physmem.perBankWrBursts::8 7193 # Per bank write bursts +system.physmem.perBankWrBursts::9 6845 # Per bank write bursts +system.physmem.perBankWrBursts::10 6667 # Per bank write bursts +system.physmem.perBankWrBursts::11 6550 # Per bank write bursts +system.physmem.perBankWrBursts::12 6596 # Per bank write bursts +system.physmem.perBankWrBursts::13 6392 # Per bank write bursts +system.physmem.perBankWrBursts::14 6532 # Per bank write bursts +system.physmem.perBankWrBursts::15 6576 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2616532122000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 6652 # Read request sizes (log2) +system.physmem.readPktSize::3 15335424 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 152617 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 57909 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1265330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1118297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1122310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3740106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2667387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2661184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2667924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 54482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -140,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -172,281 +174,478 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38068 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 26227.310287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2428.378300 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31656.989485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5540 14.55% 14.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3323 8.73% 23.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2175 5.71% 29.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1668 4.38% 33.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1160 3.05% 36.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1060 2.78% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 828 2.18% 41.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 781 2.05% 43.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 514 1.35% 44.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 493 1.30% 46.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 417 1.10% 47.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 450 1.18% 48.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 283 0.74% 49.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 279 0.73% 49.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 185 0.49% 50.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 195 0.51% 50.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 134 0.35% 51.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 139 0.37% 51.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 114 0.30% 51.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 94 0.25% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 76 0.20% 52.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 792 2.08% 54.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 136 0.36% 55.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 113 0.30% 55.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 85 0.22% 56.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 60 0.16% 56.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 34 0.09% 56.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 44 0.12% 56.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 48 0.13% 56.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 35 0.09% 57.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 24 0.06% 57.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 25 0.07% 57.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 18 0.05% 57.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 21 0.06% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 5 0.01% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 8 0.02% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 15 0.04% 57.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 17 0.04% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 7 0.02% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 18 0.05% 57.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 8 0.02% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 16 0.04% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 11 0.03% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 6 0.02% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 5 0.01% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 5 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 7 0.02% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 6 0.02% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 6 0.02% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 9 0.02% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 42 0.11% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 2 0.01% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 4 0.01% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 8 0.02% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 4 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 5 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 6 0.02% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 2 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 1 0.00% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 6 0.02% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 1 0.00% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 10 0.03% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 2 0.01% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 5 0.01% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 2 0.01% 58.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 3 0.01% 58.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 3 0.01% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 3 0.01% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 1 0.00% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 2 0.01% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 2 0.01% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 2 0.01% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 1 0.00% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 4 0.01% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 1 0.00% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 6 0.02% 58.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 16 0.04% 58.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 4 0.01% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 4 0.01% 58.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 4 0.01% 58.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 2 0.01% 58.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 2 0.01% 58.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 5 0.01% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 2 0.01% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 7 0.02% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 6 0.02% 58.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 8 0.02% 58.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 8 0.02% 58.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 328 0.86% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 24 0.06% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8575 141 0.37% 59.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 169 0.44% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8831 1 0.00% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 2 0.01% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 3 0.01% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 3 0.01% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 4 0.01% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 1 0.00% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11967 1 0.00% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 2 0.01% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12991 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 4 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13247 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-14015 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 4 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14655 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-15039 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16703 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 3 0.01% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 2 0.01% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 5 0.01% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18624-18687 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19391 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20415 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 2 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22207 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22335 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23231 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 4 0.01% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24255 1 0.00% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 3 0.01% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25151 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25407 1 0.00% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25791 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 2 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 4 0.01% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28223 2 0.01% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28863 1 0.00% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 3 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30399 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31167 1 0.00% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31423 1 0.00% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 2 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31743 1 0.00% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 6 0.02% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33215 19 0.05% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 23 0.06% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 1 0.00% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36415 2 0.01% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40255 1 0.00% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41279 2 0.01% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41791 1 0.00% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46399 1 0.00% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46591 1 0.00% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47167 3 0.01% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47935 1 0.00% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48447 1 0.00% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48959 1 0.00% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49727 1 0.00% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52287 2 0.01% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 1 0.00% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56576-56639 1 0.00% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57407 1 0.00% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57600-57663 1 0.00% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58431 2 0.01% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60479 1 0.00% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60672-60735 1 0.00% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61247 1 0.00% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61696-61759 1 0.00% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 1 0.00% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 190 0.50% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65151 6 0.02% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65279 6 0.02% 61.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 1 0.00% 61.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 1 0.00% 61.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 14664 38.52% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::67392-67455 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::69760-69823 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::71744-71807 2 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-74047 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38068 # Bytes accessed per row activation -system.physmem.totQLat 296768605750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 390592239500 # Sum of mem lat for all requests -system.physmem.totBusLat 77465575000 # Total cycles spent in databus access -system.physmem.totBankLat 16358058750 # Total cycles spent in bank access -system.physmem.avgQLat 19154.87 # Average queueing delay per request -system.physmem.avgBankLat 1055.83 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25210.70 # Average memory access latency -system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.12 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 13.76 # Average write queue length over time -system.physmem.readRowHits 15468398 # Number of row buffer hits during reads -system.physmem.writeRowHits 93875 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.56 # Row buffer hit rate for writes -system.physmem.avgGap 160406.60 # Average gap between requests +system.physmem.bytesPerActivate::samples 89727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11127.069087 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1028.273701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16706.873806 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23194 25.85% 25.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14559 16.23% 42.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2860 3.19% 45.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2118 2.36% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1356 1.51% 49.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1216 1.36% 50.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 947 1.06% 51.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1180 1.32% 52.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 650 0.72% 53.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 587 0.65% 54.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 521 0.58% 54.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 703 0.78% 55.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 336 0.37% 55.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 268 0.30% 56.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 216 0.24% 56.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 509 0.57% 57.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 151 0.17% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 159 0.18% 57.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 138 0.15% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 229 0.26% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 246 0.27% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 69 0.08% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 53 0.06% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 188 0.21% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 32 0.04% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 26 0.03% 61.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 180 0.20% 61.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 16 0.02% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 28 0.03% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 12 0.01% 61.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 150 0.17% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 27 0.03% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 112 0.12% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 10 0.01% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 11 0.01% 62.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 11 0.01% 62.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 157 0.17% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 13 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 16 0.02% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 359 0.40% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 18 0.02% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 100 0.11% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 18 0.02% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.01% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 89 0.10% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 18 0.02% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 147 0.16% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 12 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 13 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 10 0.01% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 177 0.20% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 8 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 12 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 149 0.17% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 10 0.01% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 161 0.18% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 11 0.01% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 82 0.09% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 497 0.55% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 11 0.01% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 8 0.01% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 7 0.01% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 18 0.02% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 64 0.07% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 10 0.01% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 138 0.15% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 89 0.10% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 2 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 276 0.31% 65.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 1 0.00% 65.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 33 0.04% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 146 0.16% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 83 0.09% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 5 0.01% 65.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 526 0.59% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 79 0.09% 66.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 1 0.00% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 1 0.00% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 37 0.04% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 1 0.00% 66.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 10 0.01% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 407 0.45% 66.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 12 0.01% 66.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 33 0.04% 66.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 77 0.09% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 527 0.59% 67.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9351 2 0.00% 67.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 85 0.09% 67.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 150 0.17% 67.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 29 0.03% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 279 0.31% 68.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 84 0.09% 68.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 6 0.01% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 13 0.01% 68.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 4 0.00% 68.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 496 0.55% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11399 2 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 77 0.09% 68.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11655 4 0.00% 68.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 153 0.17% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 141 0.16% 69.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12167 1 0.00% 69.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 162 0.18% 69.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 69.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 137 0.15% 69.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 74 0.08% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 90 0.10% 69.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13191 2 0.00% 69.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 343 0.38% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 145 0.16% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13703 2 0.00% 70.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 90 0.10% 70.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13959 2 0.00% 70.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 133 0.15% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14215 1 0.00% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 164 0.18% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 153 0.17% 70.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14727 1 0.00% 70.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 162 0.18% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14919 1 0.00% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 88 0.10% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15175 1 0.00% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15239 1 0.00% 71.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 278 0.31% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15495 1 0.00% 71.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15623 83 0.09% 71.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 199 0.22% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16007 2 0.00% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 139 0.15% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16199 1 0.00% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16263 9 0.01% 71.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 416 0.46% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16519 1 0.00% 72.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 138 0.15% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 203 0.23% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 87 0.10% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17287 1 0.00% 72.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 275 0.31% 73.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 89 0.10% 73.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17799 3 0.00% 73.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 155 0.17% 73.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 155 0.17% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 2 0.00% 73.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 162 0.18% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18567 2 0.00% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 131 0.15% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18823 2 0.00% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18951 93 0.10% 74.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19015 1 0.00% 74.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 142 0.16% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19335 3 0.00% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19392-19399 2 0.00% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 340 0.38% 74.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 81 0.09% 74.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19776-19783 1 0.00% 74.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 77 0.09% 74.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20103 2 0.00% 74.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 134 0.15% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20416-20423 2 0.00% 74.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 164 0.18% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20615 1 0.00% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 141 0.16% 75.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20864-20871 1 0.00% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20928-20935 1 0.00% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 149 0.17% 75.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21255 80 0.09% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21319 2 0.00% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21376-21383 3 0.00% 75.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 482 0.54% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 10 0.01% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 5 0.01% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22208-22215 1 0.00% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 92 0.10% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22407 5 0.01% 76.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 269 0.30% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 35 0.04% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 146 0.16% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 81 0.09% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23431 4 0.00% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 526 0.59% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 74 0.08% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 36 0.04% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24135 1 0.00% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 12 0.01% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24512-24519 1 0.00% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 404 0.45% 78.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 7 0.01% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 28 0.03% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 84 0.09% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25472-25479 7 0.01% 78.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 523 0.58% 78.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 80 0.09% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 152 0.17% 78.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 79.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 1 0.00% 79.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 32 0.04% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26496-26503 4 0.00% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 274 0.31% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 82 0.09% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26944-26951 1 0.00% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 3 0.00% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 17 0.02% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 484 0.54% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27719 1 0.00% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27776-27783 1 0.00% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 77 0.09% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27975 2 0.00% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 152 0.17% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28224-28231 1 0.00% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 140 0.16% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 163 0.18% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28807 2 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 130 0.14% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29120-29127 1 0.00% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 75 0.08% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 86 0.10% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29575 3 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 336 0.37% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 140 0.16% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30080-30087 1 0.00% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30144-30151 2 0.00% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 91 0.10% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30407 1 0.00% 81.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 134 0.15% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 156 0.17% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 2 0.00% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 152 0.17% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 2 0.00% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 157 0.17% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31367 2 0.00% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31431 1 0.00% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 86 0.10% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 2 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 272 0.30% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 83 0.09% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32135 2 0.00% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32199 1 0.00% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 202 0.23% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 144 0.16% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 2 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 415 0.46% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 148 0.16% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 208 0.23% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33408-33415 2 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 85 0.09% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 2 0.00% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 270 0.30% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 2 0.00% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 85 0.09% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 157 0.17% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 152 0.17% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34624-34631 2 0.00% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 147 0.16% 85.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 134 0.15% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 90 0.10% 85.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35392-35399 2 0.00% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 4 0.00% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35520-35527 1 0.00% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 143 0.16% 85.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 337 0.38% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 82 0.09% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 76 0.08% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36416-36423 1 0.00% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 131 0.15% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 154 0.17% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 139 0.15% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 153 0.17% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37575 2 0.00% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 81 0.09% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37760-37767 2 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37824-37831 1 0.00% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 483 0.54% 87.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 87.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 12 0.01% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 2 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 84 0.09% 87.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 271 0.30% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 30 0.03% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 152 0.17% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 3 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 86 0.10% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 521 0.58% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40064-40071 2 0.00% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 77 0.09% 88.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 28 0.03% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 10 0.01% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 402 0.45% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 9 0.01% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 35 0.04% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 4 0.00% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 79 0.09% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 523 0.58% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 79 0.09% 89.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 146 0.16% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 34 0.04% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 269 0.30% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 89 0.10% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 3 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 3 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 13 0.01% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 1 0.00% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 482 0.54% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 78 0.09% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 151 0.17% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 138 0.15% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 3 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 153 0.17% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 2 0.00% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 134 0.15% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 77 0.09% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 82 0.09% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 341 0.38% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 2 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 140 0.16% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 93 0.10% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 1 0.00% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 133 0.15% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 149 0.17% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 3 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 156 0.17% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 157 0.17% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 3 0.00% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 88 0.10% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 298 0.33% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 110 0.12% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 200 0.22% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 70 0.08% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 136 0.15% 94.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 9 0.01% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 6 0.01% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5002 5.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89727 # Bytes accessed per row activation +system.physmem.totQLat 373414318500 # Total ticks spent queuing +system.physmem.totMemAccLat 469593144750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77465255000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18713571250 # Total ticks spent accessing banks +system.physmem.avgQLat 24102.05 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1207.87 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30309.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.98 # Data bus utilization in percentage +system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing +system.physmem.readRowHits 15419103 # Number of row buffer hits during reads +system.physmem.writeRowHits 91153 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.23 # Row buffer hit rate for writes +system.physmem.avgGap 160458.28 # Average gap between requests +system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -459,49 +658,49 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54136917 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546596 # Transaction distribution -system.membus.trans_dist::ReadResp 16546596 # Transaction distribution +system.membus.throughput 54116520 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546551 # Transaction distribution +system.membus.trans_dist::ReadResp 16546551 # Transaction distribution system.membus.trans_dist::WriteReq 763368 # Transaction distribution system.membus.trans_dist::WriteResp 763368 # Transaction distribution -system.membus.trans_dist::Writeback 57971 # Transaction distribution +system.membus.trans_dist::Writeback 57909 # Transaction distribution system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution -system.membus.trans_dist::ReadExReq 132250 # Transaction distribution -system.membus.trans_dist::ReadExResp 132250 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 132216 # Transaction distribution +system.membus.trans_dist::ReadExResp 132216 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893731 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893513 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280361 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951429 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34951209 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525304 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923421 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516344 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914457 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141606813 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141606813 # Total data (bytes) +system.membus.tot_pkt_size::total 141597849 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141597849 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206151000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3613000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3614000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17904160000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17910601500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4944878700 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4950348835 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34615555500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34633819250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -509,13 +708,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47816267 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution +system.iobus.throughput 47801275 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution system.iobus.trans_dist::WriteReq 8166 # Transaction distribution system.iobus.trans_dist::WriteResp 8166 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -537,12 +736,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -564,14 +763,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073785 # Total data (bytes) +system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073781 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -617,32 +816,32 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42038784500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42037561750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996146 # DTB read hits -system.cpu.dtb.read_misses 7341 # DTB read misses -system.cpu.dtb.write_hits 11230467 # DTB write hits -system.cpu.dtb.write_misses 2217 # DTB write misses +system.cpu.dtb.read_hits 14995644 # DTB read hits +system.cpu.dtb.read_misses 7334 # DTB read misses +system.cpu.dtb.write_hits 11230146 # DTB write hits +system.cpu.dtb.write_misses 2212 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3498 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 197 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003487 # DTB read accesses -system.cpu.dtb.write_accesses 11232684 # DTB write accesses +system.cpu.dtb.read_accesses 15002978 # DTB read accesses +system.cpu.dtb.write_accesses 11232358 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226613 # DTB hits -system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 26236171 # DTB accesses -system.cpu.itb.inst_hits 61492923 # ITB inst hits +system.cpu.dtb.hits 26225790 # DTB hits +system.cpu.dtb.misses 9546 # DTB misses +system.cpu.dtb.accesses 26235336 # DTB accesses +system.cpu.itb.inst_hits 61491413 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -659,79 +858,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61497394 # ITB inst accesses -system.cpu.itb.hits 61492923 # DTB hits +system.cpu.itb.inst_accesses 61495884 # ITB inst accesses +system.cpu.itb.hits 61491413 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61497394 # DTB accesses -system.cpu.numCycles 5231432444 # number of cpu cycles simulated +system.cpu.itb.accesses 61495884 # DTB accesses +system.cpu.numCycles 5233072966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60199078 # Number of instructions committed -system.cpu.committedOps 76605946 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872726 # Number of integer alu accesses +system.cpu.committedInsts 60197580 # Number of instructions committed +system.cpu.committedOps 76603973 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68871033 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140465 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948429 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872726 # number of integer instructions +system.cpu.num_func_calls 2140403 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948247 # number of instructions that are conditional controls +system.cpu.num_int_insts 68871033 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394779183 # number of times the integer registers were read -system.cpu.num_int_register_writes 74182470 # number of times the integer registers were written +system.cpu.num_int_register_reads 394768801 # number of times the integer registers were read +system.cpu.num_int_register_writes 74180798 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394080 # number of memory refs -system.cpu.num_load_insts 15660200 # Number of load instructions -system.cpu.num_store_insts 11733880 # Number of store instructions -system.cpu.num_idle_cycles 4581975478.612248 # Number of idle cycles -system.cpu.num_busy_cycles 649456965.387752 # Number of busy cycles -system.cpu.not_idle_fraction 0.124145 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875855 # Percentage of idle cycles +system.cpu.num_mem_refs 27393280 # number of memory refs +system.cpu.num_load_insts 15659727 # Number of load instructions +system.cpu.num_store_insts 11733553 # Number of store instructions +system.cpu.num_idle_cycles 4581527140.608249 # Number of idle cycles +system.cpu.num_busy_cycles 651545825.391751 # Number of busy cycles +system.cpu.not_idle_fraction 0.124505 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875495 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856273 # number of replacements -system.cpu.icache.tags.tagsinuse 510.884220 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60636138 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856785 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.771708 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19799760250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.884220 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997821 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997821 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60636138 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60636138 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60636138 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60636138 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60636138 # number of overall hits -system.cpu.icache.overall_hits::total 60636138 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856785 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856785 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856785 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856785 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856785 # number of overall misses -system.cpu.icache.overall_misses::total 856785 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11770019500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11770019500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11770019500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11770019500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11770019500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11770019500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61492923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61492923 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61492923 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61492923 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61492923 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61492923 # number of overall (read+write) accesses +system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 856254 # number of replacements +system.cpu.icache.tags.tagsinuse 510.868538 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60634647 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856766 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.771537 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.868538 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60634647 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60634647 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60634647 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60634647 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60634647 # number of overall hits +system.cpu.icache.overall_hits::total 60634647 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856766 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856766 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856766 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856766 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856766 # number of overall misses +system.cpu.icache.overall_misses::total 856766 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773893500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11773893500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11773893500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11773893500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11773893500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11773893500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491413 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491413 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491413 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13737.424792 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13737.424792 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13737.424792 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13737.424792 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.251093 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13742.251093 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.251093 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13742.251093 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.251093 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13742.251093 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,174 +939,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856785 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856785 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856785 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856785 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856785 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856785 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051263500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10051263500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051263500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10051263500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051263500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10051263500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 414413750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 414413750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 414413750 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056315500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10056315500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435321250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435321250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435321250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 435321250 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58563.863958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59597.697660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.421514 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1011,79 +1210,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # 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average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25873.058298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25873.058298 # average overall miss latency +system.cpu.dcache.tags.replacements 626141 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.876746 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23655438 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626653 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.748863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.876746 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195736 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195736 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972597 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236394 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236394 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23168333 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168333 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168333 # number of overall hits +system.cpu.dcache.overall_hits::total 23168333 # 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number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11621403015 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158363750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158363750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17038281265 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17038281265 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17038281265 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17038281265 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222739 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23786534 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23786534 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23786534 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23786534 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027135 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027135 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # 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average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.859464 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.859464 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27561.070372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27561.070372 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1092,54 +1291,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595785 # number of writebacks -system.cpu.dcache.writebacks::total 595785 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250216 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250216 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618715 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618715 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14701227235 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14701227235 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050836250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050836250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234094465 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234094465 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284930715 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284930715 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027167 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027167 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024476 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024476 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12599.264856 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12599.264856 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40198.911081 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40198.911081 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11797.695652 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11797.695652 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595234 # number of writebacks +system.cpu.dcache.writebacks::total 595234 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250142 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250142 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11385 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11385 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618201 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618201 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618201 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618201 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4678465750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678465750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069177985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069177985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135539250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135539250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747643735 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15747643735 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747643735 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15747643735 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284765600 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284765600 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045948 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045948 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025990 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025990 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12711.184212 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12711.184212 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44251.577044 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44251.577044 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11905.072464 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.072464 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1147,37 +1346,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 53011951 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2455175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2455175 # Transaction distribution +system.cpu.toL2Bus.throughput 52965120 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454582 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454582 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595785 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247318 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247318 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5751163 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7516260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755700 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83692841 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34900 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138497589 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138497589 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3009741500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 595234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247209 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514380 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54754804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615077 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138418857 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138418857 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3008581500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1296026750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295429750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2542955300 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2534385915 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18720500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use @@ -1193,10 +1392,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1460469685500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1460469685500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1538389615750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1538389615750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index e69bdd504..79d47dc5b 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,131 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.192278 # Number of seconds simulated -sim_ticks 5192277855000 # Number of ticks simulated -final_tick 5192277855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196390 # Number of seconds simulated +sim_ticks 5196390180000 # Number of ticks simulated +final_tick 5196390180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 964497 # Simulator instruction rate (inst/s) -host_op_rate 1859169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39021883302 # Simulator tick rate (ticks/s) -host_mem_usage 587612 # Number of bytes of host memory used -host_seconds 133.06 # Real time elapsed on the host -sim_insts 128336541 # Number of instructions simulated -sim_ops 247382226 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2866368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory +host_inst_rate 893068 # Simulator instruction rate (inst/s) +host_op_rate 1721530 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36161085452 # Simulator tick rate (ticks/s) +host_mem_usage 586592 # Number of bytes of host memory used +host_seconds 143.70 # Real time elapsed on the host +sim_insts 128334813 # Number of instructions simulated +sim_ops 247385808 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2883712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9005696 # Number of bytes read from this memory -system.physmem.bytes_read::total 12698368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8111936 # Number of bytes written to this memory -system.physmem.bytes_written::total 8111936 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8989184 # Number of bytes read from this memory +system.physmem.bytes_read::total 12697856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8110912 # Number of bytes written to this memory +system.physmem.bytes_written::total 8110912 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 45058 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140714 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198412 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126749 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126749 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 552044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140456 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198404 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126733 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126733 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 554945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1734440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2445626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1562308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1562308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1562308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 552044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1729890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2443592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1560874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 554945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1734440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4007933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198412 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 126749 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 198412 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 126749 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 12698368 # Total number of bytes read from memory -system.physmem.bytesWritten 8111936 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12698368 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8111936 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 1635 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12459 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12489 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12363 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12070 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 11839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 11744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12394 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12454 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12175 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8332 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8067 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7928 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8252 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8013 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7644 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7381 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7640 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8073 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8394 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8318 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7938 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7649 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry -system.physmem.totGap 5192277790500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198412 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 126749 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 155262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1087 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see +system.physmem.bw_total::cpu.inst 158670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1729890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4004466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198404 # Number of read requests accepted +system.physmem.writeReqs 126733 # Number of write requests accepted +system.physmem.readBursts 198404 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 126733 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12694144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue +system.physmem.bytesWritten 8109888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12697856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8110912 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1616 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12580 # Per bank write bursts +system.physmem.perBankRdBursts::1 12146 # Per bank write bursts +system.physmem.perBankRdBursts::2 12820 # Per bank write bursts +system.physmem.perBankRdBursts::3 12639 # Per bank write bursts +system.physmem.perBankRdBursts::4 12420 # Per bank write bursts +system.physmem.perBankRdBursts::5 12033 # Per bank write bursts +system.physmem.perBankRdBursts::6 12032 # Per bank write bursts +system.physmem.perBankRdBursts::7 12154 # Per bank write bursts +system.physmem.perBankRdBursts::8 12328 # Per bank write bursts +system.physmem.perBankRdBursts::9 11842 # Per bank write bursts +system.physmem.perBankRdBursts::10 12289 # Per bank write bursts +system.physmem.perBankRdBursts::11 12385 # Per bank write bursts +system.physmem.perBankRdBursts::12 12618 # Per bank write bursts +system.physmem.perBankRdBursts::13 13039 # Per bank write bursts +system.physmem.perBankRdBursts::14 12508 # Per bank write bursts +system.physmem.perBankRdBursts::15 12513 # Per bank write bursts +system.physmem.perBankWrBursts::0 8180 # Per bank write bursts +system.physmem.perBankWrBursts::1 7837 # Per bank write bursts +system.physmem.perBankWrBursts::2 8283 # Per bank write bursts +system.physmem.perBankWrBursts::3 8150 # Per bank write bursts +system.physmem.perBankWrBursts::4 7961 # Per bank write bursts +system.physmem.perBankWrBursts::5 7589 # Per bank write bursts +system.physmem.perBankWrBursts::6 7480 # Per bank write bursts +system.physmem.perBankWrBursts::7 7728 # Per bank write bursts +system.physmem.perBankWrBursts::8 7696 # Per bank write bursts +system.physmem.perBankWrBursts::9 7447 # Per bank write bursts +system.physmem.perBankWrBursts::10 7846 # Per bank write bursts +system.physmem.perBankWrBursts::11 7788 # Per bank write bursts +system.physmem.perBankWrBursts::12 8080 # Per bank write bursts +system.physmem.perBankWrBursts::13 8539 # Per bank write bursts +system.physmem.perBankWrBursts::14 8032 # Per bank write bursts +system.physmem.perBankWrBursts::15 8081 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 5196390116500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 198404 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 126733 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 155323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 52 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -137,296 +139,310 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45297 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 459.065810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.635945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1572.397321 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 18574 41.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 7178 15.85% 56.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4205 9.28% 66.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2900 6.40% 72.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1973 4.36% 76.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1677 3.70% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1250 2.76% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1043 2.30% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 738 1.63% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 608 1.34% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 523 1.15% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 460 1.02% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 307 0.68% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 311 0.69% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 233 0.51% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 396 0.87% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 152 0.34% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 138 0.30% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 115 0.25% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 132 0.29% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 133 0.29% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 129 0.28% 95.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 607 1.34% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 165 0.36% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 95 0.21% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 80 0.18% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 50 0.11% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 52 0.11% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 21 0.05% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 24 0.05% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 26 0.06% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 33 0.07% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 17 0.04% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 17 0.04% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.02% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 9 0.02% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 10 0.02% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 10 0.02% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 5 0.01% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 8 0.02% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 10 0.02% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 7 0.02% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 2 0.00% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.00% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 3 0.01% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 4 0.01% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 1 0.00% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 11 0.02% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 3 0.01% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 3 0.01% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 12 0.03% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 1 0.00% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 18 0.04% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 7 0.02% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 3 0.01% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 2 0.00% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 1 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 3 0.01% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 3 0.01% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 10 0.02% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 4 0.01% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 3 0.01% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 3 0.01% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 4 0.01% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 340 0.75% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 7 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 2 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 244 0.54% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 12 0.03% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 10 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17155 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17283 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17539 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45297 # Bytes accessed per row activation -system.physmem.totQLat 3410755000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7054990000 # Sum of mem lat for all requests -system.physmem.totBusLat 991695000 # Total cycles spent in databus access -system.physmem.totBankLat 2652540000 # Total cycles spent in bank access -system.physmem.avgQLat 17196.59 # Average queueing delay per request -system.physmem.avgBankLat 13373.77 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35570.36 # Average memory access latency -system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 5072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 20 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 53708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.265063 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.541838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1283.636288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 22377 41.66% 41.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 8801 16.39% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 5780 10.76% 68.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 3435 6.40% 75.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2322 4.32% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1859 3.46% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1339 2.49% 85.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1034 1.93% 87.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 806 1.50% 88.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 663 1.23% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 546 1.02% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 427 0.80% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 325 0.61% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 307 0.57% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 277 0.52% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 550 1.02% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 185 0.34% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 190 0.35% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 112 0.21% 95.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 109 0.20% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 125 0.23% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 422 0.79% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 149 0.28% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 87 0.16% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 55 0.10% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 85 0.16% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 52 0.10% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 36 0.07% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 25 0.05% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 24 0.04% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 18 0.03% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 26 0.05% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 25 0.05% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 20 0.04% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 13 0.02% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 9 0.02% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 14 0.03% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 11 0.02% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 14 0.03% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 11 0.02% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 9 0.02% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 10 0.02% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 13 0.02% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 26 0.05% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 12 0.02% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 9 0.02% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 19 0.04% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 10 0.02% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 9 0.02% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 12 0.02% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 12 0.02% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 15 0.03% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 10 0.02% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 20 0.04% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 13 0.02% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 24 0.04% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 13 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 11 0.02% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 19 0.04% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 10 0.02% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 13 0.02% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 7 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 9 0.02% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 11 0.02% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 7 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 9 0.02% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 9 0.02% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 10 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 9 0.02% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 7 0.01% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 9 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 7 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 5 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 13 0.02% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 8 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 7 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 8 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 10 0.02% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 5 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 9 0.02% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 151 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 2 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 2 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 4 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 19 0.04% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 4 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 14 0.03% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11139 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 4 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 4 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 6 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 3 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 7 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 32 0.06% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 178 0.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 53708 # Bytes accessed per row activation +system.physmem.totQLat 5080719250 # Total ticks spent queuing +system.physmem.totMemAccLat 8752324250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 991730000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2679875000 # Total ticks spent accessing banks +system.physmem.avgQLat 25615.44 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13511.11 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 44126.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 12.08 # Average write queue length over time -system.physmem.readRowHits 181292 # Number of row buffer hits during reads -system.physmem.writeRowHits 98480 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.70 # Row buffer hit rate for writes -system.physmem.avgGap 15968328.89 # Average gap between requests -system.membus.throughput 4372413 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 623536 # Transaction distribution -system.membus.trans_dist::ReadResp 623536 # Transaction distribution -system.membus.trans_dist::WriteReq 13773 # Transaction distribution -system.membus.trans_dist::WriteResp 13773 # Transaction distribution -system.membus.trans_dist::Writeback 126749 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2152 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution -system.membus.trans_dist::ReadExReq 159747 # Transaction distribution -system.membus.trans_dist::ReadExResp 159747 # Transaction distribution -system.membus.trans_dist::MessageReq 1654 # Transaction distribution -system.membus.trans_dist::MessageResp 1654 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.98 # Average write queue length when enqueuing +system.physmem.readRowHits 173438 # Number of row buffer hits during reads +system.physmem.writeRowHits 97917 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.26 # Row buffer hit rate for writes +system.physmem.avgGap 15982155.57 # Average gap between requests +system.physmem.pageHitRate 83.47 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.27 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 4365247 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 623514 # Transaction distribution +system.membus.trans_dist::ReadResp 623514 # Transaction distribution +system.membus.trans_dist::WriteReq 13775 # Transaction distribution +system.membus.trans_dist::WriteResp 13775 # Transaction distribution +system.membus.trans_dist::Writeback 126733 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1634 # Transaction distribution +system.membus.trans_dist::ReadExReq 159484 # Transaction distribution +system.membus.trans_dist::ReadExResp 159484 # Transaction distribution +system.membus.trans_dist::MessageReq 1655 # Transaction distribution +system.membus.trans_dist::MessageResp 1655 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391769 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1582207 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 139016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1724531 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 139281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1724207 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14957248 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16623909 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5853056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5853056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22483581 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22483581 # Total data (bytes) -system.membus.snoop_data_through_bus 219200 # Total snoop data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14938368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16605037 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5870400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5870400 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22482057 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22482057 # Total data (bytes) +system.membus.snoop_data_through_bus 201472 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 256796500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 359311000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 359316000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1350436000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1352149000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2614907754 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2612327754 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 428881000 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 428873750 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47507 # number of replacements -system.iocache.tags.tagsinuse 0.110729 # Cycle average of tags in use +system.iocache.tags.replacements 47501 # number of replacements +system.iocache.tags.tagsinuse 0.113099 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5049641350000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.110729 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006921 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006921 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses -system.iocache.ReadReq_misses::total 842 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5049776837000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.113099 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007069 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007069 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 836 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses -system.iocache.demand_misses::total 47562 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses -system.iocache.overall_misses::total 47562 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 148613936 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 148613936 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10808111078 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10808111078 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10956725014 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10956725014 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10956725014 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10956725014 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses +system.iocache.demand_misses::total 47556 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses +system.iocache.overall_misses::total 47556 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144134686 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144134686 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12487439330 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12487439330 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 12631574016 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12631574016 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 12631574016 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12631574016 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -435,40 +451,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 176501.111639 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 176501.111639 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 231337.993964 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 231337.993964 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 230367.205206 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 230367.205206 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 230367.205206 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 230367.205206 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 172843 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 172409.911483 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 172409.911483 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267282.519906 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 267282.519906 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 265614.728236 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 265614.728236 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 216457 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 15866 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11594 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.893924 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 18.669743 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104797436 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104797436 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8377057578 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8377057578 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8481855014 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8481855014 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8481855014 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8481855014 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100637686 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100637686 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 10056284830 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10056284830 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10156922516 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10156922516 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -477,14 +493,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 124462.513064 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 124462.513064 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 179303.458433 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 179303.458433 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 178332.597746 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 178332.597746 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 178332.597746 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 178332.597746 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120380.007177 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 120380.007177 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215245.822560 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 215245.822560 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -498,13 +514,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 631773 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 230147 # Transaction distribution -system.iobus.trans_dist::ReadResp 230147 # Transaction distribution +system.iobus.throughput 631264 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 230141 # Transaction distribution +system.iobus.trans_dist::ReadResp 230141 # Transaction distribution system.iobus.trans_dist::WriteReq 57579 # Transaction distribution system.iobus.trans_dist::WriteResp 57579 # Transaction distribution -system.iobus.trans_dist::MessageReq 1654 # Transaction distribution -system.iobus.trans_dist::MessageResp 1654 # Transaction distribution +system.iobus.trans_dist::MessageReq 1655 # Transaction distribution +system.iobus.trans_dist::MessageResp 1655 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -524,11 +540,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 578760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 578750 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -548,13 +564,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3280340 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3280340 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3946566 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3280296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3280296 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3948164 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -590,87 +606,87 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424359014 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424033266 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53490000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52989250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.numCycles 10384555710 # number of cpu cycles simulated +system.cpu.numCycles 10392780360 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128336541 # Number of instructions committed -system.cpu.committedOps 247382226 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231975048 # Number of integer alu accesses +system.cpu.committedInsts 128334813 # Number of instructions committed +system.cpu.committedOps 247385808 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231978567 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2299863 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23167946 # number of instructions that are conditional controls -system.cpu.num_int_insts 231975048 # number of integer instructions +system.cpu.num_func_calls 2299773 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23169265 # number of instructions that are conditional controls +system.cpu.num_int_insts 231978567 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434515715 # number of times the integer registers were read -system.cpu.num_int_register_writes 197846848 # number of times the integer registers were written +system.cpu.num_int_register_reads 434513747 # number of times the integer registers were read +system.cpu.num_int_register_writes 197852200 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132806307 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95529498 # number of times the CC registers were written -system.cpu.num_mem_refs 22249600 # number of memory refs -system.cpu.num_load_insts 13881232 # Number of load instructions -system.cpu.num_store_insts 8368368 # Number of store instructions -system.cpu.num_idle_cycles 9777359201.998117 # Number of idle cycles -system.cpu.num_busy_cycles 607196508.001883 # Number of busy cycles -system.cpu.not_idle_fraction 0.058471 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941529 # Percentage of idle cycles +system.cpu.num_cc_register_reads 132813019 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95534921 # number of times the CC registers were written +system.cpu.num_mem_refs 22245363 # number of memory refs +system.cpu.num_load_insts 13878746 # Number of load instructions +system.cpu.num_store_insts 8366617 # Number of store instructions +system.cpu.num_idle_cycles 9785238216.998117 # Number of idle cycles +system.cpu.num_busy_cycles 607542143.001883 # Number of busy cycles +system.cpu.not_idle_fraction 0.058458 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.941542 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 792807 # number of replacements -system.cpu.icache.tags.tagsinuse 510.358419 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144581557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 793319 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.248953 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161241203250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.358419 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996794 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996794 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144581557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144581557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144581557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144581557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144581557 # number of overall hits -system.cpu.icache.overall_hits::total 144581557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 793326 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 793326 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 793326 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 793326 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 793326 # number of overall misses -system.cpu.icache.overall_misses::total 793326 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11210417756 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11210417756 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11210417756 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11210417756 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11210417756 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11210417756 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145374883 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145374883 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145374883 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145374883 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145374883 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145374883 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005457 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005457 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005457 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005457 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005457 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005457 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14130.909306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14130.909306 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14130.909306 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14130.909306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14130.909306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14130.909306 # average overall miss latency +system.cpu.icache.tags.replacements 788090 # number of replacements +system.cpu.icache.tags.tagsinuse 510.351939 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144584753 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 788602 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 183.343122 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161436066250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.351939 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996781 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144584753 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144584753 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144584753 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144584753 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144584753 # number of overall hits +system.cpu.icache.overall_hits::total 144584753 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 788609 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 788609 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 788609 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 788609 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 788609 # number of overall misses +system.cpu.icache.overall_misses::total 788609 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11107362758 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11107362758 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11107362758 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11107362758 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11107362758 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11107362758 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145373362 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145373362 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145373362 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145373362 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145373362 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145373362 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005425 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005425 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005425 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005425 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005425 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005425 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14084.752720 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14084.752720 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14084.752720 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14084.752720 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -679,80 +695,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793326 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 793326 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 793326 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 793326 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 793326 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 793326 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9617488244 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9617488244 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9617488244 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9617488244 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9617488244 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9617488244 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005457 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005457 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005457 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12122.996402 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12122.996402 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12122.996402 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12122.996402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12122.996402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12122.996402 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788609 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 788609 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 788609 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 788609 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 788609 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 788609 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9525299242 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9525299242 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9525299242 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9525299242 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9525299242 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9525299242 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005425 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005425 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005425 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12078.608337 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12078.608337 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3898 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.066238 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7439 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3908 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.903531 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5166941674000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.066238 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191640 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191640 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7461 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7461 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 3741 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.069761 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7617 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3752 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.030117 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5169682535000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069761 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191860 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191860 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7617 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7617 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7463 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7463 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7463 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7463 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4754 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4754 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4754 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4754 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4754 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4754 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48555250 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48555250 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48555250 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 48555250 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48555250 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 48555250 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12215 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12215 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7619 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7619 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7619 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7619 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4604 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4604 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4604 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4604 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4604 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4604 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44886750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44886750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44886750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 44886750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44886750 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 44886750 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12217 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12217 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12217 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12217 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.389194 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.389194 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.389130 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.389130 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.389130 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.389130 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10213.557005 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10213.557005 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10213.557005 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10213.557005 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10213.557005 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10213.557005 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376729 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376729 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376667 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.376667 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376667 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.376667 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9749.511295 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9749.511295 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9749.511295 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9749.511295 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,78 +777,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 837 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 837 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4754 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4754 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4754 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4754 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4754 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4754 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39044750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39044750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39044750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39044750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39044750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39044750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.389194 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.389194 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.389130 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.389130 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.389130 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.389130 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8213.031132 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8213.031132 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8213.031132 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 621 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 621 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4604 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4604 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4604 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4604 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4604 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4604 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35677750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35677750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35677750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35677750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35677750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35677750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376729 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376729 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376667 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376667 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7749.294092 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7667 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.048611 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13083 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7683 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.702850 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5163398099000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.048611 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315538 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315538 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13083 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13083 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13083 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13083 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13083 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13083 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8874 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8874 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8874 # 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number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21957 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21957 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21957 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21957 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21957 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.404154 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.404154 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.404154 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.404154 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.404154 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.404154 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10811.246338 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10811.246338 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10811.246338 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10811.246338 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10811.246338 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10811.246338 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 7948 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.052475 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12793 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7961 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.606959 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5168018375000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052475 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315780 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315780 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12806 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12806 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12806 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12806 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12806 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12806 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9138 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9138 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9138 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9138 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9138 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9138 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97347500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97347500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97347500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 97347500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97347500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 97347500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21944 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21944 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21944 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21944 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21944 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21944 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.416424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.416424 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.416424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.416424 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.416424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.416424 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10653.042241 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10653.042241 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10653.042241 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10653.042241 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -841,90 +857,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2999 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2999 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8874 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8874 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8874 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8874 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8874 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 78190500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 78190500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 78190500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 78190500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 78190500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 78190500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.404154 # 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average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8811.189993 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8811.189993 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9138 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9138 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9138 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9138 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9138 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9138 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 79071000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 79071000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 79071000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 79071000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 79071000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 79071000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.416424 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.416424 # 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average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622533 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997176 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20039030 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623045 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.346565 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 49459250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997176 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1621547 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997026 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20035701 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622059 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.352017 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 50992250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997026 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11994437 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11994437 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8042382 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8042382 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20036819 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20036819 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20036819 # 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number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29634252490 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29634252490 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29634252490 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29634252490 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13304038 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13304038 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8358054 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8358054 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21662092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21662092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21662092 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21662092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037769 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037769 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075028 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075028 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075028 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075028 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14421.330462 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14421.330462 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34048.200965 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34048.200965 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18233.399860 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18233.399860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18233.399860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18233.399860 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11993197 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11993197 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8040328 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8040328 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20033525 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20033525 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20033525 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29915988238 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29915988238 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29915988238 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29915988238 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13301509 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13301509 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8356302 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8356302 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21657811 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21657811 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21657811 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21657811 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098358 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098358 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074998 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074998 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074998 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074998 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14456.726912 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14456.726912 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34819.570401 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34819.570401 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18417.931471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18417.931471 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -933,46 +949,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539374 # number of writebacks -system.cpu.dcache.writebacks::total 1539374 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309601 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1309601 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315672 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315672 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1625273 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1625273 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625273 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625273 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16253560205 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16253560205 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10061381305 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10061381305 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26314941510 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26314941510 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26314941510 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26314941510 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537247000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537247000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96751919500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96751919500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098436 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098436 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037769 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037769 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075028 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075028 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12411.078034 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12411.078034 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31872.897517 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31872.897517 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16191.090057 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16191.090057 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16191.090057 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16191.090057 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1538973 # number of writebacks +system.cpu.dcache.writebacks::total 1538973 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308312 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308312 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315974 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315974 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1624286 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1624286 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1624286 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1624286 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16288101700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16288101700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10316379062 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10316379062 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26604480762 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26604480762 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26604480762 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26604480762 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214673000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214673000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537491500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537491500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752164500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752164500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098358 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098358 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074998 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074998 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12449.707486 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12449.707486 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32649.455531 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32649.455531 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -980,175 +996,175 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 49299027 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2698843 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2698315 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543210 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 360181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313477 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1586639 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18580 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7593504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50772032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204036453 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 621184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 255690853 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 255669733 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 304512 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3835424500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 49185341 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2692945 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2692419 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1542700 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 360518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313820 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1577205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5977035 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8133 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7581359 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50470144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203948077 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 225856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 630272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 255274349 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 255253101 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 333120 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3831866500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 498000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1193127756 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1185336258 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3058413490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3054054238 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 7132250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6906500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13311250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13707250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 86950 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64733.250589 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3493106 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151616 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.039165 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 86910 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64731.196890 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3488433 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151626 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.006826 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50239.194329 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.026648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3379.223326 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11114.665027 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.766589 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50120.476905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.033461 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141258 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3445.447212 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.098054 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.764778 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.051563 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169596 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987751 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6706 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3239 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 780407 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280531 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2070883 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543210 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543210 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 301 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 301 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200188 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200188 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6706 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3239 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 780407 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1480719 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2271071 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6706 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3239 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 780407 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1480719 # number of overall hits -system.cpu.l2cache.overall_hits::total 2271071 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052573 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.170366 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.987720 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6740 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2903 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 775712 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1279207 # 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