diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
4 files changed, 3737 insertions, 0 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini new file mode 100644 index 000000000..cc3750142 --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini @@ -0,0 +1,1169 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain +atags_addr=134217728 +boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM +mem_mode=atomic +mem_ranges=2147483648:2415919103 +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5/scratch1/gem5/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload= +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +response_latency=1 +snoop_filter=Null +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=1 +frontend_latency=2 +response_latency=2 +use_default_range=true +width=16 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=2147483648:2415919103 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=false +pci_io_base=0 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_phys=29 +int_virt=27 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer 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"walker", + "is_stage2": true, + "clk_domain": "system.cpu_clk_domain", + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dstage2_mmu.stage2_tlb.walker", + "type": "ArmTableWalker", + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dstage2_mmu.stage2_tlb", + "type": "ArmTLB", + "size": 32 + }, + "eventq_index": 0, + "cxx_class": "ArmISA::Stage2MMU", + "path": "system.cpu.dstage2_mmu", + "type": "ArmStage2MMU" + }, + "l2cache": { + "is_top_level": false, + "prefetcher": null, + "clk_domain": "system.cpu_clk_domain", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "BaseCache", + "size": 4194304, + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 20, + "clk_domain": "system.cpu_clk_domain", + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "size": 4194304 + }, + "system": "system", + "max_miss_count": 0, + "eventq_index": 0, + "mem_side": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "mshrs": 20, + "forward_snoops": true, + "hit_latency": 20, + "demand_mshr_reserve": 1, + "tgts_per_mshr": 12, + "addr_ranges": [ + "0:18446744073709551615" + ], + "assoc": 8, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "name": "l2cache", + "type": "BaseCache", + "sequential_access": false, + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "two_queue": false + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [], + "name": "cpu", + "dtb": { + "name": "dtb", + "is_stage2": false, + "eventq_index": 0, + "cxx_class": "ArmISA::TLB", + "walker": { + "name": "walker", + "is_stage2": false, + "clk_domain": "system.cpu_clk_domain", + "sys": "system", + "eventq_index": 0, + "cxx_class": "ArmISA::TableWalker", + "path": "system.cpu.dtb.walker", + "type": "ArmTableWalker", + "port": { + "peer": "system.cpu.toL2Bus.slave[3]", + "role": "MASTER" + }, + "num_squash_per_cycle": 2 + }, + "path": "system.cpu.dtb", + "type": "ArmTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "is_top_level": true, + "prefetcher": null, + "clk_domain": "system.cpu_clk_domain", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "BaseCache", + "size": 32768, + "tags": { + "name": "tags", + "eventq_index": 0, + "hit_latency": 2, + "clk_domain": "system.cpu_clk_domain", + "sequential_access": false, + "assoc": 4, + "cxx_class": "LRU", + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "size": 32768 + }, + "system": "system", + "max_miss_count": 0, + "eventq_index": 0, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "forward_snoops": true, + "hit_latency": 2, + "demand_mshr_reserve": 1, + "tgts_per_mshr": 20, + "addr_ranges": [ + "0:18446744073709551615" + ], + "assoc": 4, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "name": "dcache", + "type": "BaseCache", + "sequential_access": false, + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "two_queue": false + }, + "isa": [ + { + "pmu": null, + "id_pfr1": 4113, + "id_pfr0": 49, + "id_isar1": 34677009, + "id_isar0": 34607377, + "id_isar3": 17899825, + "id_isar2": 555950401, + "id_isar5": 0, + "id_isar4": 268501314, + "cxx_class": "ArmISA::ISA", + "id_aa64mmfr1_el1": 0, + "id_aa64pfr1_el1": 0, + "system": "system", + "eventq_index": 0, + "type": "ArmISA", + "id_aa64dfr1_el1": 0, + "fpsid": 1090793632, + "id_mmfr0": 270536963, + "id_mmfr1": 0, + "id_mmfr2": 19070976, + "id_mmfr3": 34611729, + "id_aa64mmfr0_el1": 15728642, + "id_aa64dfr0_el1": 1052678, + "path": "system.cpu.isa", + "id_aa64isar0_el1": 0, + "name": "isa", + "midr": 1091551472, + "id_aa64afr0_el1": 0, + "id_aa64isar1_el1": 0, + "id_aa64afr1_el1": 0, + "id_aa64pfr0_el1": 17 + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "gic_cpu_addr": 738205696, + "work_cpus_ckpt_count": 0, + "work_begin_exit_count": 0, + "machine_type": "VExpress_EMM", + "flags_addr": 469827632, + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "cf0": { + "driveID": "master", + "name": "cf0", + "image": { + "read_only": false, + "name": "image", + "cxx_class": "CowDiskImage", + "eventq_index": 0, + "child": { + "read_only": true, + "name": "child", + "eventq_index": 0, + "cxx_class": "RawDiskImage", + "path": "system.cf0.image.child", + "image_file": "/work/gem5/dist/disks/linux-aarch32-ael.img", + "type": "RawDiskImage" + }, + "path": "system.cf0.image", + "image_file": "", + "type": "CowDiskImage", + "table_size": 65536 + }, + "delay": 1000000, + "eventq_index": 0, + "cxx_class": "IdeDisk", + "path": "system.cf0", + "type": "IdeDisk" + }, + "boot_release_addr": 65528, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "system_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "load_addr_mask": 268435455, + "work_item_id": -1, + "intrctrl": { + "name": "intrctrl", + "sys": "system", + "eventq_index": 0, + "cxx_class": "IntrControl", + "path": "system.intrctrl", + "type": "IntrControl" + }, + "have_security": false, + "atags_addr": 134217728, + "memories": [ + "system.physmem", + "system.realview.nvmem", + "system.realview.vram" + ], + "work_begin_cpu_id_exit": -1, + "boot_loader": "/work/gem5/dist/binaries/boot_emm.arm", + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": true +}
\ No newline at end of file diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt new file mode 100644 index 000000000..68d3c4919 --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -0,0 +1,740 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 976886 # Simulator instruction rate (inst/s) +host_mem_usage 567972 # Number of bytes of host memory used +host_op_rate 1189202 # Simulator op (including micro ops) rate (op/s) +host_seconds 146.15 # Real time elapsed on the host +host_tick_rate 19047880334 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 142772879 # Number of instructions simulated +sim_ops 173803124 # Number of ops (including micro ops) simulated +sim_seconds 2.783867 # Number of seconds simulated +sim_ticks 2783867052000 # Number of ticks simulated +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.Branches 36396981 # Number of branches fetched +system.cpu.committedInsts 142772879 # Number of instructions committed +system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses +system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses +system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits +system.cpu.dcache.overall_hits::total 52864242 # number of overall hits +system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses +system.cpu.dcache.overall_misses::total 814074 # number of overall misses +system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 819402 # number of replacements +system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks +system.cpu.dcache.writebacks::total 682059 # number of writebacks +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.accesses 54660704 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 54650675 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 10029 # DTB misses +system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 31534804 # DTB read accesses +system.cpu.dtb.read_hits 31526223 # DTB read hits +system.cpu.dtb.read_misses 8581 # DTB read misses +system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 10029 # Table walker walks requested +system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors +system.cpu.dtb.write_accesses 23125900 # DTB write accesses +system.cpu.dtb.write_hits 23124452 # DTB write hits +system.cpu.dtb.write_misses 1448 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses +system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits +system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses +system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits +system.cpu.icache.overall_hits::total 145342721 # number of overall hits +system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses +system.cpu.icache.overall_misses::total 1699732 # number of overall misses +system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 1699214 # number of replacements +system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. +system.cpu.idle_fraction 0.968015 # Percentage of idle cycles +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.accesses 147044108 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 147039346 # DTB hits +system.cpu.itb.inst_accesses 147044108 # ITB inst accesses +system.cpu.itb.inst_hits 147039346 # ITB inst hits +system.cpu.itb.inst_misses 4762 # ITB inst misses +system.cpu.itb.misses 4762 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 4762 # Table walker walks requested +system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses +system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits +system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses +system.cpu.l2cache.overall_misses::total 181764 # number of overall misses +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 110026 # number of replacements +system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks +system.cpu.l2cache.writebacks::total 101897 # number of writebacks +system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles +system.cpu.numCycles 5567737188 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles +system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written +system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses +system.cpu.num_fp_insts 11484 # number of float instructions +system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written +system.cpu.num_func_calls 16873899 # number of times a function call or return occured +system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles +system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses +system.cpu.num_int_insts 153162683 # number of integer instructions +system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read +system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written +system.cpu.num_load_insts 31855884 # Number of load instructions +system.cpu.num_mem_refs 55939276 # number of memory refs +system.cpu.num_store_insts 24083392 # Number of store instructions +system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction +system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 177219912 # Class of executed instruction +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram +system.cpu.toL2Bus.snoops 36631 # Total snoops (count) +system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 30164 # Transaction distribution +system.iobus.trans_dist::ReadResp 30164 # Transaction distribution +system.iobus.trans_dist::WriteReq 59002 # Transaction distribution +system.iobus.trans_dist::WriteResp 22778 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses +system.iocache.ReadReq_misses::total 240 # number of ReadReq misses +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses +system.iocache.demand_misses::total 240 # number of demand (read+write) misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.overall_misses::realview.ide 240 # number of overall misses +system.iocache.overall_misses::total 240 # number of overall misses +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.data_accesses 328176 # Number of data accesses +system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.replacements 36430 # number of replacements +system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. +system.iocache.tags.tag_accesses 328176 # Number of tag accesses +system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_fanout::samples 359045 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 359045 # Request fanout histogram +system.membus.snoops 0 # Total snoops (count) +system.membus.trans_dist::ReadReq 74227 # Transaction distribution +system.membus.trans_dist::ReadResp 74227 # Transaction distribution +system.membus.trans_dist::WriteReq 27546 # Transaction distribution +system.membus.trans_dist::WriteResp 27546 # Transaction distribution +system.membus.trans_dist::Writeback 138087 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution +system.membus.trans_dist::ReadExReq 146085 # Transaction distribution +system.membus.trans_dist::ReadExResp 146085 # Transaction distribution +system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s) +system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory +system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/system.terminal new file mode 100644 index 000000000..ad91d76dd --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/system.terminal @@ -0,0 +1,208 @@ +Booting Linux on physical CPU 0x0
+
Initializing cgroup subsys cpuset
+
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
+
Kernel was built at commit id ''
+
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
+
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
+
Machine model: V2P-CA15
+
bootconsole [earlycon0] enabled
+
Memory policy: Data cache writealloc
+
kdebugv2m: Following are test values to confirm proper working
+
kdebugv2m: Ranges 42000000 0
+
kdebugv2m: Regs 30000000 1000000
+
kdebugv2m: Virtual-Reg f0000000
+
kdebugv2m: pci node addr_cells 3
+
kdebugv2m: pci node size_cells 2
+
kdebugv2m: motherboard addr_cells 2
+
On node 0 totalpages: 65536
+
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
+
Normal zone: 512 pages used for memmap
+
Normal zone: 0 pages reserved
+
Normal zone: 65536 pages, LIFO batch:15
+
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
+
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
+
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
+
pcpu-alloc: [0] 0
+
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
+
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+
PID hash table entries: 1024 (order: 0, 4096 bytes)
+
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
+
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
+
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
+
Virtual kernel memory layout:
+
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
+
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
+
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
+
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
+
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
+
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
+
.text : 0x80008000 - 0x806a942c (6790 kB)
+
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
+
.data : 0x806f4000 - 0x80732754 ( 250 kB)
+
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
+
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
+
Preemptible hierarchical RCU implementation.
+
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
+
NR_IRQS:16 nr_irqs:16 16
+
Architected cp15 timer(s) running at 25.16MHz (phys).
+
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
+
Switching to timer-based delay loop
+
Console: colour dummy device 80x30
+
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+
pid_max: default: 32768 minimum: 301
+
Mount-cache hash table entries: 512
+
CPU: Testing write buffer coherency: ok
+
CPU0: update cpu_power 1024
+
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
+
Setting up static identity map for 0x804fee68 - 0x804fee9c
+
Brought up 1 CPUs
+
SMP: Total of 1 processors activated.
+
CPU: All CPU(s) started in SVC mode.
+
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
+
NET: Registered protocol family 16
+
DMA: preallocated 256 KiB pool for atomic coherent allocations
+
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
+
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
+
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
+
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
+
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
+
hw-breakpoint: CPU 0 failed to disable vector catch
+
Serial: AMBA PL011 UART driver
+
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+
console [ttyAMA0] enabled
+console [ttyAMA0] enabled
+
bootconsole [earlycon0] disabled
+bootconsole [earlycon0] disabled
+
PCI host bridge to bus 0000:00
+pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
+pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
+pci_bus 0000:00: root bus resource [bus 00-ff]
+pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+PCI: bus0: Fast back to back transfers disabled
+pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
+pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
+pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
+pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
+pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
+pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
+pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
+PCI map irq: slot 0, pin 1, devslot 0, irq: 68
+PCI map irq: slot 1, pin 2, devslot 1, irq: 69
+bio: create slab <bio-0> at 0
+vgaarb: loaded
+SCSI subsystem initialized
+libata version 3.00 loaded.
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+pps_core: LinuxPPS API ver. 1 registered
+pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+PTP clock support registered
+Advanced Linux Sound Architecture Driver Initialized.
+Switched to clocksource arch_sys_counter
+NET: Registered protocol family 2
+TCP established hash table entries: 2048 (order: 1, 8192 bytes)
+TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
+TCP: Hash tables configured (established 2048 bind 2048)
+TCP: reno registered
+UDP hash table entries: 256 (order: 1, 8192 bytes)
+UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+NET: Registered protocol family 1
+RPC: Registered named UNIX socket transport module.
+RPC: Registered udp transport module.
+RPC: Registered tcp transport module.
+RPC: Registered tcp NFSv4.1 backchannel transport module.
+PCI: CLS 64 bytes, default 64
+hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available
+jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
+msgmni has been set to 460
+io scheduler noop registered (default)
+brd: module loaded
+loop: module loaded
+ata_piix 0000:00:01.0: version 2.13
+PCI: enabling device 0000:00:01.0 (0040 -> 0041)
+scsi0 : ata_piix
+scsi1 : ata_piix
+ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69
+ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69
+e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
+e100: Copyright(c) 1999-2006 Intel Corporation
+e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+e1000: Copyright (c) 1999-2006 Intel Corporation.
+PCI: enabling device 0000:00:00.0 (0040 -> 0042)
+ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+ata1.00: 1048320 sectors, multi 0: LBA
+ata1.00: configured for UDMA/33
+scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
+sd 0:0:0:0: [sda] Write Protect is off
+sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+ sda: sda1
+sd 0:0:0:0: Attached scsi generic sg0 type 0
+sd 0:0:0:0: [sda] Attached SCSI disk
+e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
+igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+igb: Copyright (c) 2007-2013 Intel Corporation.
+igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k
+igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
+ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k
+ixgbe: Copyright (c) 1999-2013 Intel Corporation.
+ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k
+ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.
+ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
+ixgb: Copyright (c) 1999-2008 Intel Corporation.
+smsc911x: Driver version 2008-10-21
+smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2
+nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller
+nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1
+nxp-isp1760 1b000000.usb: Scratch test failed.
+nxp-isp1760 1b000000.usb: can't setup: -19
+nxp-isp1760 1b000000.usb: USB bus 1 deregistered
+usbcore: registered new interface driver usb-storage
+mousedev: PS/2 mouse device common for all mice
+rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0
+usbcore: registered new interface driver usbhid
+usbhid: USB HID core driver
+ashmem: initialized
+logger: created 256K log 'log_main'
+logger: created 256K log 'log_events'
+logger: created 256K log 'log_radio'
+logger: created 256K log 'log_system'
+oprofile: using timer interrupt.
+TCP: cubic registered
+NET: Registered protocol family 10
+NET: Registered protocol family 17
+rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
+ALSA device list:
+ No soundcards found.
+ +input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2
+VFS: Mounted root (ext2 filesystem) on device 8:1.
+Freeing unused kernel memory: 292K (806aa000 - 806f3000)
+
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
+
starting pid 673, tty '': '/etc/rc.d/rc.local'
+warning: can't open /etc/mtab: No such file or directory
+Thu Jan 1 00:00:02 UTC 2009
+S: devpts
+Thu Jan 1 00:00:02 UTC 2009
|