diff options
Diffstat (limited to 'tests/quick/fs')
48 files changed, 2771 insertions, 11022 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 730b05e22..982acdd3c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -15,16 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -108,6 +108,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -124,6 +125,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -146,6 +148,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -162,6 +165,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -171,6 +175,7 @@ eventq_index=0 [system.cpu0.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu0.itb] type=AlphaTLB @@ -234,6 +239,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags @@ -250,6 +256,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.dtb] @@ -272,6 +279,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags @@ -288,6 +296,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.interrupts] @@ -297,6 +306,7 @@ eventq_index=0 [system.cpu1.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu1.itb] type=AlphaTLB @@ -333,7 +343,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -356,7 +366,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -390,6 +400,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -406,6 +417,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -423,6 +435,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -439,6 +452,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] @@ -495,7 +509,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr index 0bcb6e870..20fe2d682 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr @@ -2,4 +2,3 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 410351310..3fdb0e076 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:50 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:41 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 -Exiting @ tick 1870335643500 because m5_exit instruction encountered +Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index e7342cf46..42e3976c4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1806360 # Simulator instruction rate (inst/s) -host_op_rate 1806359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53496127424 # Simulator tick rate (ticks/s) -host_mem_usage 353980 # Number of bytes of host memory used -host_seconds 34.96 # Real time elapsed on the host +host_inst_rate 3158607 # Simulator instruction rate (inst/s) +host_op_rate 3158605 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93543458564 # Simulator tick rate (ticks/s) +host_mem_usage 309852 # Number of bytes of host memory used +host_seconds 19.99 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory @@ -51,6 +53,7 @@ system.physmem.bw_total::total 42102084 # To system.membus.throughput 42160248 # Throughput (bytes/s) system.membus.data_through_bus 78853810 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 1000626 # number of replacements system.l2c.tags.tagsinuse 65381.922680 # Cycle average of tags in use system.l2c.tags.total_refs 2464737 # Total number of references to valid blocks. @@ -68,6 +71,15 @@ system.l2c.tags.occ_percent::cpu0.data 0.063089 # Av system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65142 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6232 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 47965 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 32109442 # Number of tag accesses +system.l2c.tags.data_accesses 32109442 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits @@ -188,6 +200,11 @@ system.iocache.tags.warmup_cycle 1685787165017 # C system.iocache.tags.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -424,6 +441,13 @@ system.cpu0.icache.tags.warmup_cycle 9786576500 # Cy system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 58115132 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 58115132 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits @@ -466,6 +490,13 @@ system.cpu0.dcache.tags.warmup_cycle 10840000 # Cy system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 62404072 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 62404072 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits @@ -661,6 +692,11 @@ system.cpu1.icache.tags.warmup_cycle 1868933059000 # C system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 6039396 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 6039396 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits @@ -703,6 +739,12 @@ system.cpu1.dcache.tags.warmup_cycle 1851115552500 # C system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 7735310 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 7735310 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 7f56b644f..b586addc4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -15,16 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -108,6 +108,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.dcache.tags @@ -124,6 +125,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.dtb] @@ -146,6 +148,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.icache.tags @@ -162,6 +165,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.interrupts] @@ -171,6 +175,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -192,6 +197,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.cpu.l2cache.tags @@ -208,6 +214,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.cpu.toL2Bus] @@ -251,7 +258,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -274,7 +281,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -308,6 +315,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -324,6 +332,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.membus] @@ -380,7 +389,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr index 0bcb6e870..20fe2d682 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr @@ -2,4 +2,3 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index b63c77b44..142ae35a0 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:50 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:41 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1829332269000 because m5_exit instruction encountered +Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 01a06923f..2043677f9 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1538182 # Simulator instruction rate (inst/s) -host_op_rate 1538181 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46867449524 # Simulator tick rate (ticks/s) -host_mem_usage 350908 # Number of bytes of host memory used -host_seconds 39.03 # Real time elapsed on the host +host_inst_rate 3003513 # Simulator instruction rate (inst/s) +host_op_rate 3003511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91515177007 # Simulator tick rate (ticks/s) +host_mem_usage 306744 # Number of bytes of host memory used +host_seconds 19.99 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory @@ -50,6 +52,11 @@ system.iocache.tags.warmup_cycle 1685780659017 # C system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -97,6 +104,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -278,6 +286,13 @@ system.cpu.icache.tags.warmup_cycle 9686972500 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 60970364 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970364 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits @@ -324,6 +339,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 31737437 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 31737437 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits @@ -400,6 +424,13 @@ system.cpu.dcache.tags.warmup_cycle 10840000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 66369799 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369799 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index c1c2c449d..87138f314 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -15,16 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -101,6 +101,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -117,6 +118,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -139,6 +141,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -155,6 +158,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -164,6 +168,7 @@ eventq_index=0 [system.cpu0.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu0.itb] type=AlphaTLB @@ -220,6 +225,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags @@ -236,6 +242,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.dtb] @@ -258,6 +265,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags @@ -274,6 +282,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.interrupts] @@ -283,6 +292,7 @@ eventq_index=0 [system.cpu1.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu1.itb] type=AlphaTLB @@ -319,7 +329,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -342,7 +352,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -376,6 +386,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -392,6 +403,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -409,6 +421,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -425,6 +438,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] @@ -505,7 +519,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr index 0bcb6e870..20fe2d682 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr @@ -2,4 +2,3 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index a33dd389d..2d1ba2c03 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:51 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:25:12 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 675287000 -Exiting @ tick 1961841175000 because m5_exit instruction encountered +info: Launching CPU 1 @ 688618000 +Exiting @ tick 1960909874500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 8b5007cf5..46997f65e 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.960910 # Nu sim_ticks 1960909874500 # Number of ticks simulated final_tick 1960909874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 787846 # Simulator instruction rate (inst/s) -host_op_rate 787845 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25353578812 # Simulator tick rate (ticks/s) -host_mem_usage 353976 # Number of bytes of host memory used -host_seconds 77.34 # Real time elapsed on the host +host_inst_rate 1305982 # Simulator instruction rate (inst/s) +host_op_rate 1305981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42027651646 # Simulator tick rate (ticks/s) +host_mem_usage 309852 # Number of bytes of host memory used +host_seconds 46.66 # Real time elapsed on the host sim_insts 60933947 # Number of instructions simulated sim_ops 60933947 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 833472 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory @@ -416,6 +418,7 @@ system.membus.respLayer1.occupancy 3830990646 # La system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 376315500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 342160 # number of replacements system.l2c.tags.tagsinuse 65219.945305 # Cycle average of tags in use system.l2c.tags.total_refs 2443226 # Total number of references to valid blocks. @@ -433,6 +436,15 @@ system.l2c.tags.occ_percent::cpu0.data 0.074731 # Av system.l2c.tags.occ_percent::cpu1.inst 0.002426 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.995177 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 761 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5186 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7242 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51881 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 25932224 # Number of tag accesses +system.l2c.tags.data_accesses 25932224 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 684719 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 664525 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 317383 # number of ReadReq hits @@ -724,6 +736,11 @@ system.iocache.tags.warmup_cycle 1754531382000 # C system.iocache.tags.occ_blocks::tsunami.ide 0.570482 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.035655 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.035655 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -1105,6 +1122,14 @@ system.cpu0.icache.tags.warmup_cycle 40091069250 # Cy system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.398756 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992966 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.992966 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 48690501 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48690501 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 47294969 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 47294969 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 47294969 # number of demand (read+write) hits @@ -1183,6 +1208,13 @@ system.cpu0.dcache.tags.warmup_cycle 107902250 # Cy system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.271614 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986859 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.986859 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51851796 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51851796 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 6451735 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 6451735 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4706856 # number of WriteReq hits @@ -1461,6 +1493,12 @@ system.cpu1.icache.tags.warmup_cycle 1958987590000 # C system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.450379 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871973 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.871973 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 13271059 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13271059 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 12635285 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 12635285 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 12635285 # number of demand (read+write) hits @@ -1539,6 +1577,12 @@ system.cpu1.dcache.tags.warmup_cycle 67802253000 # Cy system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.752776 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948736 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.948736 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16587420 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16587420 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 2220669 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 2220669 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 1595283 # number of WriteReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 54bf6e928..161fac4a8 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/dist/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -60,6 +65,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -86,6 +92,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -94,6 +101,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.dcache.tags @@ -108,11 +116,14 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -121,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -129,6 +141,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.icache.tags @@ -143,17 +156,23 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -162,6 +181,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -170,6 +190,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.cpu.l2cache.tags @@ -184,12 +205,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -199,10 +223,12 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -210,19 +236,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -230,28 +259,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -265,6 +299,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -273,6 +308,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -287,13 +323,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.membus] type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -305,6 +344,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -331,6 +371,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -342,29 +383,35 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -373,6 +420,7 @@ port=3456 [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -381,6 +429,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -391,6 +440,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -419,6 +469,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -428,8 +479,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -446,6 +529,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -469,6 +553,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -486,6 +571,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -503,6 +589,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -520,6 +607,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -537,6 +625,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -554,6 +643,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -571,6 +661,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -588,6 +679,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -605,6 +697,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -622,6 +715,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -639,6 +733,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -656,6 +751,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -673,6 +769,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -690,6 +787,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -707,6 +805,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -724,6 +823,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -741,6 +841,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -758,6 +859,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -775,6 +877,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -793,6 +896,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -820,6 +924,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -829,8 +934,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -842,6 +979,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -856,6 +994,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -868,6 +1007,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -878,6 +1018,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -888,6 +1029,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -897,5 +1039,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr index 0bcb6e870..20fe2d682 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr @@ -2,4 +2,3 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index cabc90a11..fa5fb8ad8 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:50 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:24:48 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1918473094000 because m5_exit instruction encountered +Exiting @ tick 1920428041000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 479e1f707..01b0606bd 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.920428 # Nu sim_ticks 1920428041000 # Number of ticks simulated final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1218375 # Simulator instruction rate (inst/s) -host_op_rate 1218374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41646226437 # Simulator tick rate (ticks/s) -host_mem_usage 305884 # Number of bytes of host memory used -host_seconds 46.11 # Real time elapsed on the host +host_inst_rate 1405906 # Simulator instruction rate (inst/s) +host_op_rate 1405905 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48056353161 # Simulator tick rate (ticks/s) +host_mem_usage 307800 # Number of bytes of host memory used +host_seconds 39.96 # Real time elapsed on the host sim_insts 56182750 # Number of instructions simulated sim_ops 56182750 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory @@ -414,6 +416,11 @@ system.iocache.tags.warmup_cycle 1753529489000 # C system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -509,6 +516,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -756,6 +764,14 @@ system.cpu.icache.tags.warmup_cycle 39723654250 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 57123599 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57123599 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits @@ -838,6 +854,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.848127 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072615 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.075609 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.996351 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1050 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4896 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3257 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55781 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 25947571 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25947571 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 915717 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 814814 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1730531 # number of ReadReq hits @@ -1004,6 +1029,13 @@ system.cpu.dcache.tags.warmup_cycle 107298250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 511.978915 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 63152102 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63152102 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 7814622 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7814622 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5852326 # number of WriteReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index db7088ff9..894acecbc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,7 +23,7 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -137,6 +137,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -153,6 +154,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -185,6 +187,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -201,6 +204,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -297,6 +301,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags @@ -313,6 +318,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.dtb] @@ -345,6 +351,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags @@ -361,6 +368,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.interrupts] @@ -440,6 +448,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -456,6 +465,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -473,6 +483,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -489,6 +500,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr index 4ccac5e7b..5a43c8b18 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr @@ -1,7 +1,6 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -15,4 +14,3 @@ warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 789ceb651..1e2520995 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simout -Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:04:45 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 17:30:53 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 912096763500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 622f0dad2..eb8cedaf3 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1031681 # Simulator instruction rate (inst/s) -host_op_rate 1328287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15269405009 # Simulator tick rate (ticks/s) -host_mem_usage 443324 # Number of bytes of host memory used -host_seconds 59.73 # Real time elapsed on the host +host_inst_rate 1859152 # Simulator instruction rate (inst/s) +host_op_rate 2393654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27516397451 # Simulator tick rate (ticks/s) +host_mem_usage 399324 # Number of bytes of host memory used +host_seconds 33.15 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory @@ -87,6 +89,7 @@ system.realview.nvmem.bw_total::total 75 # To system.membus.throughput 64986577 # Throughput (bytes/s) system.membus.data_through_bus 59274047 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 70658 # number of replacements system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. @@ -110,6 +113,19 @@ system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3771 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 12549 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 16906854 # Number of tag accesses +system.l2c.tags.data_accesses 16906854 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits @@ -349,6 +365,12 @@ system.cpu0.icache.tags.warmup_cycle 64537139000 # Cy system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 30669233 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 30669233 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits @@ -391,6 +413,11 @@ system.cpu0.dcache.tags.warmup_cycle 22115000 # Cy system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51675155 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51675155 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits @@ -409,8 +436,8 @@ system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7469 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7469 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses @@ -421,8 +448,8 @@ system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160649 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 160649 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses @@ -433,8 +460,8 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046493 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses @@ -525,6 +552,14 @@ system.cpu1.icache.tags.warmup_cycle 69967763000 # Cy system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 32848033 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 32848033 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits @@ -567,6 +602,14 @@ system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cy system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 48417680 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 48417680 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits @@ -585,8 +628,8 @@ system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10139 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10139 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses @@ -597,8 +640,8 @@ system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89169 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 89169 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses @@ -609,8 +652,8 @@ system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113705 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113705 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses @@ -632,6 +675,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 196c32809..ab338ac30 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,7 +23,7 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -137,6 +137,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.dcache.tags @@ -153,6 +154,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.dtb] @@ -185,6 +187,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.icache.tags @@ -201,6 +204,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.interrupts] @@ -255,6 +259,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.cpu.l2cache.tags @@ -271,6 +276,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.cpu.toL2Bus] @@ -324,6 +330,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -340,6 +347,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.membus] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr index eda827fb8..41742298b 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr @@ -1,7 +1,6 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -14,4 +13,3 @@ warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 0ff7b53a5..8105d53fc 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:30:49 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 17:30:43 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2332810264000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index cb6c51df2..0b833a71d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 993135 # Simulator instruction rate (inst/s) -host_op_rate 1277110 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38352024586 # Simulator tick rate (ticks/s) -host_mem_usage 443324 # Number of bytes of host memory used -host_seconds 60.83 # Real time elapsed on the host +host_inst_rate 1656319 # Simulator instruction rate (inst/s) +host_op_rate 2129924 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63962280307 # Simulator tick rate (ticks/s) +host_mem_usage 398176 # Number of bytes of host memory used +host_seconds 36.47 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory @@ -72,6 +74,7 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.iobus.throughput 48895252 # Throughput (bytes/s) system.iobus.data_through_bus 114063346 # Total data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 14971214 # DTB read hits @@ -147,6 +150,14 @@ system.cpu.icache.tags.warmup_cycle 5709383000 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 62285702 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62285702 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits @@ -197,6 +208,18 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3589 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9187 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52388 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 17035899 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17035899 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits @@ -297,6 +320,13 @@ system.cpu.dcache.tags.warmup_cycle 21763000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 97632617 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 97632617 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits @@ -361,6 +391,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 051cf58a2..da0c44ae8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,7 +23,7 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -130,6 +130,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -146,6 +147,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -178,6 +180,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -194,6 +197,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -283,6 +287,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags @@ -299,6 +304,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.dtb] @@ -331,6 +337,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags @@ -347,6 +354,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.interrupts] @@ -426,6 +434,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -442,6 +451,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -459,6 +469,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -475,6 +486,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr index 4ccac5e7b..5a43c8b18 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr @@ -1,7 +1,6 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -15,4 +14,3 @@ warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index c328b3227..012824f20 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simout -Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:25:29 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 17:31:37 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1194883580500 because m5_exit instruction encountered +Exiting @ tick 1196134388000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 168e14479..da78d67e8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,150 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.195792 # Number of seconds simulated -sim_ticks 1195791950500 # Number of ticks simulated -final_tick 1195791950500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.196134 # Number of seconds simulated +sim_ticks 1196134388000 # Number of ticks simulated +final_tick 1196134388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 418462 # Simulator instruction rate (inst/s) -host_op_rate 533251 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8153682245 # Simulator tick rate (ticks/s) -host_mem_usage 447424 # Number of bytes of host memory used -host_seconds 146.66 # Real time elapsed on the host -sim_insts 61370228 # Number of instructions simulated -sim_ops 78204808 # Number of ops (including micro ops) simulated +host_inst_rate 708523 # Simulator instruction rate (inst/s) +host_op_rate 902798 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13791811883 # Simulator tick rate (ticks/s) +host_mem_usage 403420 # Number of bytes of host memory used +host_seconds 86.73 # Real time elapsed on the host +sim_insts 61448705 # Number of instructions simulated +sim_ops 78297711 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6626164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4724852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2903920 # Number of bytes read from this memory -system.physmem.bytes_read::total 62155172 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4136128 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7163472 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 323996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4798512 # Number of bytes read from this memory +system.physmem.bytes_read::total 62145764 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323996 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4112768 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7140112 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103606 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45400 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654629 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64627 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821463 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43405972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 5144 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75003 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654482 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64262 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 821098 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43393546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 387790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5541235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 328876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3950101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2428449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51978249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 387790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602218 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3458903 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2531631 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5990567 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3458903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43405972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 270869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4011683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51955503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 328876 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 270869 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 599745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3438383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2516727 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5969323 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3438383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43393546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 387790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8072866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 328876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3964314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2428483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57968816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654629 # Number of read requests accepted -system.physmem.writeReqs 821463 # Number of write requests accepted -system.physmem.readBursts 6654629 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821463 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425873472 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22784 # Total number of bytes read from write queue -system.physmem.bytesWritten 7293184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62155172 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7163472 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 356 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707504 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 10661 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415730 # Per bank write bursts -system.physmem.perBankRdBursts::1 415559 # Per bank write bursts -system.physmem.perBankRdBursts::2 414961 # Per bank write bursts -system.physmem.perBankRdBursts::3 415335 # Per bank write bursts -system.physmem.perBankRdBursts::4 422368 # Per bank write bursts -system.physmem.perBankRdBursts::5 415375 # Per bank write bursts -system.physmem.perBankRdBursts::6 415446 # Per bank write bursts -system.physmem.perBankRdBursts::7 415289 # Per bank write bursts -system.physmem.perBankRdBursts::8 415350 # Per bank write bursts -system.physmem.perBankRdBursts::9 415631 # Per bank write bursts -system.physmem.perBankRdBursts::10 415265 # Per bank write bursts -system.physmem.perBankRdBursts::11 414898 # Per bank write bursts -system.physmem.perBankRdBursts::12 415491 # Per bank write bursts -system.physmem.perBankRdBursts::13 416088 # Per bank write bursts -system.physmem.perBankRdBursts::14 415759 # Per bank write bursts -system.physmem.perBankRdBursts::15 415728 # Per bank write bursts -system.physmem.perBankWrBursts::0 7313 # Per bank write bursts -system.physmem.perBankWrBursts::1 7201 # Per bank write bursts -system.physmem.perBankWrBursts::2 6692 # Per bank write bursts -system.physmem.perBankWrBursts::3 6866 # Per bank write bursts -system.physmem.perBankWrBursts::4 7393 # Per bank write bursts -system.physmem.perBankWrBursts::5 6958 # Per bank write bursts -system.physmem.perBankWrBursts::6 7169 # Per bank write bursts -system.physmem.perBankWrBursts::7 6986 # Per bank write bursts -system.physmem.perBankWrBursts::8 6988 # Per bank write bursts -system.physmem.perBankWrBursts::9 7250 # Per bank write bursts -system.physmem.perBankWrBursts::10 6972 # Per bank write bursts -system.physmem.perBankWrBursts::11 6687 # Per bank write bursts -system.physmem.perBankWrBursts::12 7223 # Per bank write bursts -system.physmem.perBankWrBursts::13 7529 # Per bank write bursts -system.physmem.perBankWrBursts::14 7375 # Per bank write bursts -system.physmem.perBankWrBursts::15 7354 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 270869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6528410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57924826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654482 # Number of read requests accepted +system.physmem.writeReqs 821098 # Number of write requests accepted +system.physmem.readBursts 6654482 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821098 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425858048 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 28800 # Total number of bytes read from write queue +system.physmem.bytesWritten 7268928 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62145764 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7140112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 450 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707519 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 11807 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415388 # Per bank write bursts +system.physmem.perBankRdBursts::1 415219 # Per bank write bursts +system.physmem.perBankRdBursts::2 415339 # Per bank write bursts +system.physmem.perBankRdBursts::3 415675 # Per bank write bursts +system.physmem.perBankRdBursts::4 422391 # Per bank write bursts +system.physmem.perBankRdBursts::5 415542 # Per bank write bursts +system.physmem.perBankRdBursts::6 415783 # Per bank write bursts +system.physmem.perBankRdBursts::7 415483 # Per bank write bursts +system.physmem.perBankRdBursts::8 416074 # Per bank write bursts +system.physmem.perBankRdBursts::9 415577 # Per bank write bursts +system.physmem.perBankRdBursts::10 415272 # Per bank write bursts +system.physmem.perBankRdBursts::11 414856 # Per bank write bursts +system.physmem.perBankRdBursts::12 415143 # Per bank write bursts +system.physmem.perBankRdBursts::13 415555 # Per bank write bursts +system.physmem.perBankRdBursts::14 415537 # Per bank write bursts +system.physmem.perBankRdBursts::15 415198 # Per bank write bursts +system.physmem.perBankWrBursts::0 6998 # Per bank write bursts +system.physmem.perBankWrBursts::1 6842 # Per bank write bursts +system.physmem.perBankWrBursts::2 7022 # Per bank write bursts +system.physmem.perBankWrBursts::3 7170 # Per bank write bursts +system.physmem.perBankWrBursts::4 7417 # Per bank write bursts +system.physmem.perBankWrBursts::5 7181 # Per bank write bursts +system.physmem.perBankWrBursts::6 7437 # Per bank write bursts +system.physmem.perBankWrBursts::7 7180 # Per bank write bursts +system.physmem.perBankWrBursts::8 7616 # Per bank write bursts +system.physmem.perBankWrBursts::9 7218 # Per bank write bursts +system.physmem.perBankWrBursts::10 7106 # Per bank write bursts +system.physmem.perBankWrBursts::11 6658 # Per bank write bursts +system.physmem.perBankWrBursts::12 6803 # Per bank write bursts +system.physmem.perBankWrBursts::13 7016 # Per bank write bursts +system.physmem.perBankWrBursts::14 7092 # Per bank write bursts +system.physmem.perBankWrBursts::15 6821 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1195787534500 # Total gap between requests +system.physmem.totGap 1196129800000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6825 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159740 # Read request sizes (log2) +system.physmem.readPktSize::6 159593 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64627 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 636769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 483388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 484627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1579502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1123930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1118197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1114450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8900 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64262 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 634838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 481612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 482409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1579414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1125551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1120257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1116869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -159,29 +165,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -191,408 +197,401 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5778.397556 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 392.859970 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 13041.482454 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 26098 34.81% 34.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 15301 20.41% 55.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3417 4.56% 59.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2337 3.12% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1552 2.07% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1311 1.75% 66.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1048 1.40% 68.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1133 1.51% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 708 0.94% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 576 0.77% 71.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 588 0.78% 72.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 600 0.80% 72.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 313 0.42% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 304 0.41% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 211 0.28% 74.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 484 0.65% 74.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 181 0.24% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 133 0.18% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 163 0.22% 75.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 181 0.24% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 117 0.16% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2275 3.03% 78.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 133 0.18% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 94 0.13% 79.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 64 0.09% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 60 0.08% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 43 0.06% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 123 0.16% 79.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 53 0.07% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 29 0.04% 79.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 191 0.25% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 19 0.03% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 18 0.02% 79.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 24 0.03% 79.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 41 0.05% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 14 0.02% 79.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 25 0.03% 80.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 28 0.04% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 24 0.03% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 25 0.03% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 17 0.02% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 20 0.03% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 20 0.03% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 20 0.03% 80.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 6 0.01% 80.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 190 0.25% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 23 0.03% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 8 0.01% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 10 0.01% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 98 0.13% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 7 0.01% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 7 0.01% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 16 0.02% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 20 0.03% 80.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 6 0.01% 80.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 20 0.03% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 37 0.05% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 47 0.06% 80.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 17 0.02% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 8 0.01% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 6 0.01% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 197 0.26% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 10 0.01% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 14 0.02% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 80 0.11% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 4 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 14 0.02% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 33 0.04% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 14 0.02% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 23 0.03% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 5 0.01% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 7 0.01% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 15 0.02% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 154 0.21% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 14 0.02% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 6 0.01% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 35 0.05% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 170 0.23% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.08% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 78 0.10% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 9 0.01% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 89 0.12% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 2 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 70 0.09% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 1 0.00% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 108 0.14% 82.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 1 0.00% 82.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 17 0.02% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 32 0.04% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 132 0.18% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 28 0.04% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 74 0.10% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 29 0.04% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 75 0.10% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 29 0.04% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 2 0.00% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 130 0.17% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 29 0.04% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9287 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 17 0.02% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 100 0.13% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 74 0.10% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 86 0.11% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 12 0.02% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 80 0.11% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 29 0.04% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 2 0.00% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11207 1 0.00% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 147 0.20% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11463 1 0.00% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 8 0.01% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 25 0.03% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 77 0.10% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 181 0.24% 84.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 36 0.05% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 17 0.02% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 77 0.10% 84.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13255 1 0.00% 84.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 164 0.22% 84.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 12 0.02% 84.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 12 0.02% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 27 0.04% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 1 0.00% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 3 0.00% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 162 0.22% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 88 0.12% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 21 0.03% 85.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15047 2 0.00% 85.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 28 0.04% 85.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 218 0.29% 85.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 20 0.03% 85.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 17 0.02% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 8 0.01% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 2 0.00% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 272 0.36% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 7 0.01% 86.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 1 0.00% 86.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 16 0.02% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 23 0.03% 86.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 1 0.00% 86.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 224 0.30% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17607 2 0.00% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 24 0.03% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 18 0.02% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 1 0.00% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 85 0.11% 86.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 154 0.21% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 30 0.04% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 16 0.02% 86.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 19 0.03% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 1 0.00% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 169 0.23% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 71 0.09% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 12 0.02% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 44 0.06% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 167 0.22% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 3 0.00% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 78 0.10% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20800-20807 1 0.00% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20864-20871 1 0.00% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 25 0.03% 87.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21184-21191 2 0.00% 87.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 12 0.02% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 1 0.00% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 139 0.19% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 23 0.03% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 79 0.11% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22215 1 0.00% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 9 0.01% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 89 0.12% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 2 0.00% 88.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 71 0.09% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 103 0.14% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 16 0.02% 88.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23367 1 0.00% 88.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 26 0.03% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 131 0.17% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 26 0.03% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 72 0.10% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 1 0.00% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 23 0.03% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 77 0.10% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 26 0.03% 88.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 1 0.00% 88.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 132 0.18% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 29 0.04% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 15 0.02% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 98 0.13% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 1 0.00% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 2 0.00% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 75 0.10% 89.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26560-26567 1 0.00% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 84 0.11% 89.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 13 0.02% 89.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 81 0.11% 89.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 23 0.03% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 143 0.19% 89.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 89.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 9 0.01% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 25 0.03% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 80 0.11% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 3 0.00% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 176 0.23% 90.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 1 0.00% 90.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 40 0.05% 90.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 16 0.02% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 72 0.10% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29639 1 0.00% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 167 0.22% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29760-29767 1 0.00% 90.64% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 239 0.32% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 36 0.05% 97.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 14 0.02% 97.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2125 2.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74963 # Bytes accessed per row activation -system.physmem.totQLat 159518930750 # Total ticks spent queuing -system.physmem.totMemAccLat 202571234500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33271365000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9780938750 # Total ticks spent accessing banks -system.physmem.avgQLat 23972.41 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1469.87 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::43776-43783 17 0.02% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 146 0.20% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 71 0.10% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 32 0.04% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 1 0.00% 95.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 75 0.10% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 96 0.13% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 16 0.02% 95.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 9 0.01% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 79 0.11% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 86 0.12% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 3 0.00% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 79 0.11% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 1 0.00% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46784-46791 1 0.00% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 84 0.11% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 165 0.22% 96.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 25 0.03% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 19 0.03% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 18 0.02% 96.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 184 0.25% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 2 0.00% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 42 0.06% 97.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48448-48455 1 0.00% 97.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 81 0.11% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 14 0.02% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 7 0.01% 97.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 10 0.01% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 7 0.01% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2105 2.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74428 # Bytes accessed per row activation +system.physmem.totQLat 159442536500 # Total ticks spent queuing +system.physmem.totMemAccLat 202459287750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33270160000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9746591250 # Total ticks spent accessing banks +system.physmem.avgQLat 23961.79 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1464.76 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30442.28 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.98 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30426.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.03 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.12 # Average write queue length when enqueuing -system.physmem.readRowHits 6598430 # Number of row buffer hits during reads -system.physmem.writeRowHits 94836 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.52 # Average write queue length when enqueuing +system.physmem.readRowHits 6598367 # Number of row buffer hits during reads +system.physmem.writeRowHits 94814 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.22 # Row buffer hit rate for writes -system.physmem.avgGap 159948.21 # Average gap between requests -system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.87 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes +system.physmem.avgGap 160004.95 # Average gap between requests +system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.95 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -611,286 +610,314 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 59983824 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703157 # Transaction distribution -system.membus.trans_dist::ReadResp 7703157 # Transaction distribution -system.membus.trans_dist::WriteReq 767205 # Transaction distribution -system.membus.trans_dist::WriteResp 767205 # Transaction distribution -system.membus.trans_dist::Writeback 64627 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27746 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16446 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10661 # Transaction distribution -system.membus.trans_dist::ReadExReq 137744 # Transaction distribution -system.membus.trans_dist::ReadExResp 137297 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes) +system.membus.throughput 59941628 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703327 # Transaction distribution +system.membus.trans_dist::ReadResp 7703327 # Transaction distribution +system.membus.trans_dist::WriteReq 767563 # Transaction distribution +system.membus.trans_dist::WriteResp 767563 # Transaction distribution +system.membus.trans_dist::Writeback 64262 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31362 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17250 # Transaction distribution +system.membus.trans_dist::UpgradeResp 11807 # Transaction distribution +system.membus.trans_dist::ReadExReq 137774 # Transaction distribution +system.membus.trans_dist::ReadExResp 137331 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382556 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10302 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4359117 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4365438 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335245 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17341566 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389866 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20604 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19823662 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17381364 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19793730 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71728174 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71728174 # Total data (bytes) +system.membus.tot_pkt_size::total 71698242 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71698242 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224786000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224728000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7986500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9233500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 782000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9213145499 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9211169999 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5079077969 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5081009046 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14657796999 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657682249 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 69622 # number of replacements -system.l2c.tags.tagsinuse 53154.714662 # Cycle average of tags in use -system.l2c.tags.total_refs 1651251 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134786 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.250909 # Average number of references to valid blocks. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.l2c.tags.replacements 69474 # number of replacements +system.l2c.tags.tagsinuse 52958.436277 # Cycle average of tags in use +system.l2c.tags.total_refs 1673866 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134633 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.432806 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40043.388352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667642 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40141.137275 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4637.694613 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5787.547519 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1927.667021 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 755.746308 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.611014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 3711.443492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4231.516476 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742470 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001688 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2812.646868 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2058.946054 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.612505 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.088311 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056632 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064568 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011532 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.811077 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4526 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1443 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 483144 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 241974 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3792 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1866 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 372505 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 110561 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1219811 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 576138 # number of Writeback hits -system.l2c.Writeback_hits::total 576138 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1247 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 445 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1692 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 260 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 101 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65526 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 45407 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110933 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4526 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1443 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 483144 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 307500 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3792 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1866 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 372505 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155968 # number of demand (read+write) hits -system.l2c.demand_hits::total 1330744 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4526 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1443 # number of overall hits -system.l2c.overall_hits::cpu0.inst 483144 # number of overall hits -system.l2c.overall_hits::cpu0.data 307500 # number of overall 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latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56666.917644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58768.841591 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55174.000958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70812.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64607.662938 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59152.393857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60061.894404 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62780.286049 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59025.268693 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1072,62 +1111,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118330469 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2505274 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2505274 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576138 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 27005 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16807 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43812 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262415 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262415 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993978 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5841 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753985 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879812 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6193 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 12022 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7617898 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31385016 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53721240 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5780 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24096780 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27936146 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7468 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 137185718 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137185718 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4312904 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4765712727 # Layer occupancy (ticks) +system.toL2Bus.throughput 119504988 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2535165 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535165 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767563 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767563 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 570845 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30638 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17564 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48202 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260860 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260860 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864640 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226897 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6150 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12700 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 939820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600271 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6172 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15273 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7671923 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27252536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41401460 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7016 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15324 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30051724 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39586058 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138342918 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138342918 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4601108 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4758624958 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2217854478 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1926201968 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2469983321 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1755625353 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 8869000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1698669462 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2208533441 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2116407722 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 2924723840 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 4326499 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8230499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 9919749 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45404559 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution +system.iobus.throughput 45391537 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671396 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671396 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution system.iobus.trans_dist::WriteResp 7946 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1149,12 +1188,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382570 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382556 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 15358684 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16132 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16104 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1176,14 +1215,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389866 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294406 # Total data (bytes) +system.iobus.tot_pkt_size::total 54294378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294378 # Total data (bytes) system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4039000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4032000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1229,32 +1268,32 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374610000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17777853001 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17778098751 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9652640 # DTB read hits -system.cpu0.dtb.read_misses 3742 # DTB read misses -system.cpu0.dtb.write_hits 7596858 # DTB write hits -system.cpu0.dtb.write_misses 1582 # DTB write misses +system.cpu0.dtb.read_hits 7069308 # DTB read hits +system.cpu0.dtb.read_misses 3747 # DTB read misses +system.cpu0.dtb.write_hits 5655300 # DTB write hits +system.cpu0.dtb.write_misses 806 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1799 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9656382 # DTB read accesses -system.cpu0.dtb.write_accesses 7598440 # DTB write accesses +system.cpu0.dtb.read_accesses 7073055 # DTB read accesses +system.cpu0.dtb.write_accesses 5656106 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17249498 # DTB hits -system.cpu0.dtb.misses 5324 # DTB misses -system.cpu0.dtb.accesses 17254822 # DTB accesses -system.cpu0.itb.inst_hits 43298691 # ITB inst hits +system.cpu0.dtb.hits 12724608 # DTB hits +system.cpu0.dtb.misses 4553 # DTB misses +system.cpu0.dtb.accesses 12729161 # DTB accesses +system.cpu0.itb.inst_hits 29565201 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1271,79 +1310,87 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43300896 # ITB inst accesses -system.cpu0.itb.hits 43298691 # DTB hits +system.cpu0.itb.inst_accesses 29567406 # ITB inst accesses +system.cpu0.itb.hits 29565201 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43300896 # DTB accesses -system.cpu0.numCycles 2391583901 # number of cpu cycles simulated +system.cpu0.itb.accesses 29567406 # DTB accesses +system.cpu0.numCycles 2392268776 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42571767 # Number of instructions committed -system.cpu0.committedOps 53302041 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48059042 # Number of integer alu accesses +system.cpu0.committedInsts 28867316 # Number of instructions committed +system.cpu0.committedOps 37205643 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33092917 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403630 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582817 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48059042 # number of integer instructions +system.cpu0.num_func_calls 1241596 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4372519 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33092917 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272441604 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52270515 # number of times the integer registers were written +system.cpu0.num_int_register_reads 190017972 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36219842 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 18019009 # number of memory refs -system.cpu0.num_load_insts 10036503 # Number of load instructions -system.cpu0.num_store_insts 7982506 # Number of store instructions -system.cpu0.num_idle_cycles 2151142905.888201 # Number of idle cycles -system.cpu0.num_busy_cycles 240440995.111799 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100536 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899464 # Percentage of idle cycles +system.cpu0.num_mem_refs 13392372 # number of memory refs +system.cpu0.num_load_insts 7406786 # Number of load instructions +system.cpu0.num_store_insts 5985586 # Number of store instructions +system.cpu0.num_idle_cycles 2246456550.382122 # Number of idle cycles +system.cpu0.num_busy_cycles 145812225.617878 # Number of busy cycles +system.cpu0.not_idle_fraction 0.060951 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.939049 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51319 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 490213 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.358566 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 42807948 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 490725 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 87.234088 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 46712 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 425445 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.359322 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29139226 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 425957 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.408844 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.358566 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994841 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994841 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 42807948 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42807948 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 42807948 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42807948 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 42807948 # number of overall hits -system.cpu0.icache.overall_hits::total 42807948 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490726 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490726 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490726 # number of demand (read+write) misses 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# average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11902.398226 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11902.398226 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11902.398226 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11902.398226 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014407 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014407 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014407 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014407 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014407 # mshr miss rate for overall accesses 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0.027404 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14850.374135 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14850.374135 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44763.049240 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44763.049240 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10047.623751 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10047.623751 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5499.376673 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5499.376673 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26846.183681 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26846.183681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26846.183681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26846.183681 # average overall miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 454.615886 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.887922 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.887922 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50897043 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50897043 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6599288 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6599288 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5350353 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5350353 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147935 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147935 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149626 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149626 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11949641 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11949641 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11949641 # number of overall hits +system.cpu0.dcache.overall_hits::total 11949641 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 227704 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 227704 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141542 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141542 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9305 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9305 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7516 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7516 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369246 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369246 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369246 # number of overall misses +system.cpu0.dcache.overall_misses::total 369246 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3302919746 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3302919746 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5684238795 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5684238795 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91447249 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 91447249 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44459563 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44459563 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8987158541 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8987158541 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8987158541 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8987158541 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6826992 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6826992 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491895 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5491895 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157240 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157240 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157142 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157142 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12318887 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12318887 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12318887 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12318887 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033353 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033353 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025773 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025773 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059177 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059177 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047829 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047829 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029974 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029974 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029974 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029974 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14505.321584 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14505.321584 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40159.378806 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40159.378806 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9827.753788 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9827.753788 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5915.322379 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5915.322379 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24339.217056 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24339.217056 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24339.217056 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24339.217056 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1474,66 +1529,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 376546 # number of writebacks -system.cpu0.dcache.writebacks::total 376546 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263803 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 263803 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176623 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176623 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9911 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9911 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7395 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7395 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 440426 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 440426 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 440426 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 440426 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3387671752 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3387671752 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7508595954 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7508595954 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79710001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79710001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25901112 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25901112 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 305829 # number of writebacks +system.cpu0.dcache.writebacks::total 305829 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227704 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227704 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141542 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141542 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9305 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9305 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7514 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7514 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369246 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369246 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369246 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369246 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2845576254 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2845576254 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5370172205 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5370172205 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72789751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72789751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29432437 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29432437 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10896267706 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10896267706 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10896267706 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10896267706 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765830000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765830000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807312360 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807312360 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39573142360 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39573142360 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028063 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028063 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026476 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026476 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059549 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059549 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044448 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044448 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027404 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027404 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.672581 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.672581 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42511.994214 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42511.994214 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8042.579054 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8042.579054 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.516836 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.516836 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8215748459 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8215748459 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8215748459 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8215748459 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13558596000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13558596000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167114500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167114500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14725710500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14725710500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033353 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033353 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025773 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025773 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059177 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059177 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047817 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047817 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029974 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029974 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12496.821549 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12496.821549 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37940.485545 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37940.485545 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7822.649221 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7822.649221 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3917.013175 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3917.013175 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24740.291686 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24740.291686 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24740.291686 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24740.291686 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22250.067595 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22250.067595 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22250.067595 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22250.067595 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1543,26 +1598,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5706417 # DTB read hits -system.cpu1.dtb.read_misses 3586 # DTB read misses -system.cpu1.dtb.write_hits 3873093 # DTB write hits -system.cpu1.dtb.write_misses 644 # DTB write misses +system.cpu1.dtb.read_hits 8311308 # DTB read hits +system.cpu1.dtb.read_misses 3642 # DTB read misses +system.cpu1.dtb.write_hits 5827742 # DTB write hits +system.cpu1.dtb.write_misses 1438 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5710003 # DTB read accesses -system.cpu1.dtb.write_accesses 3873737 # DTB write accesses +system.cpu1.dtb.read_accesses 8314950 # DTB read accesses +system.cpu1.dtb.write_accesses 5829180 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9579510 # DTB hits -system.cpu1.dtb.misses 4230 # DTB misses -system.cpu1.dtb.accesses 9583740 # DTB accesses -system.cpu1.itb.inst_hits 19379017 # ITB inst hits +system.cpu1.dtb.hits 14139050 # DTB hits +system.cpu1.dtb.misses 5080 # DTB misses +system.cpu1.dtb.accesses 14144130 # DTB accesses +system.cpu1.itb.inst_hits 33191969 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1579,79 +1634,86 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19381188 # ITB inst accesses -system.cpu1.itb.hits 19379017 # DTB hits +system.cpu1.itb.inst_accesses 33194140 # ITB inst accesses +system.cpu1.itb.hits 33191969 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19381188 # DTB accesses -system.cpu1.numCycles 2390136116 # number of cpu cycles simulated +system.cpu1.itb.accesses 33194140 # DTB accesses +system.cpu1.numCycles 2390799575 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18798461 # Number of instructions committed -system.cpu1.committedOps 24902767 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22266699 # Number of integer alu accesses +system.cpu1.committedInsts 32581389 # Number of instructions committed +system.cpu1.committedOps 41092068 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37316324 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796691 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514546 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22266699 # number of integer instructions +system.cpu1.num_func_calls 962102 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3732829 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37316324 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130767489 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23318960 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213681333 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39457808 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10014870 # number of memory refs -system.cpu1.num_load_insts 5983067 # Number of load instructions -system.cpu1.num_store_insts 4031803 # Number of store instructions -system.cpu1.num_idle_cycles 1969216562.004314 # Number of idle cycles -system.cpu1.num_busy_cycles 420919553.995686 # Number of busy cycles -system.cpu1.not_idle_fraction 0.176107 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.823893 # Percentage of idle cycles +system.cpu1.num_mem_refs 14676854 # number of memory refs +system.cpu1.num_load_insts 8633232 # Number of load instructions +system.cpu1.num_store_insts 6043622 # Number of store instructions +system.cpu1.num_idle_cycles 1874349488.166457 # Number of idle cycles +system.cpu1.num_busy_cycles 516450086.833543 # Number of busy cycles +system.cpu1.not_idle_fraction 0.216016 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.783984 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39069 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 376769 # number of replacements -system.cpu1.icache.tags.tagsinuse 474.890792 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19001732 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 377281 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 50.364932 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 327211938000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.890792 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927521 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.927521 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19001732 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19001732 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19001732 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19001732 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19001732 # number of overall hits -system.cpu1.icache.overall_hits::total 19001732 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377281 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377281 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377281 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377281 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377281 # number of overall misses -system.cpu1.icache.overall_misses::total 377281 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5163865212 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5163865212 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5163865212 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5163865212 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5163865212 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5163865212 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379013 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19379013 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19379013 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19379013 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19379013 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19379013 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019469 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019469 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019469 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019469 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019469 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019469 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13687.053448 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13687.053448 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13687.053448 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13687.053448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13687.053448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13687.053448 # average overall miss latency +system.cpu1.kern.inst.quiesce 43916 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 469558 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.567582 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32721895 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 470070 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.610686 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 93987592500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.567582 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934702 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934702 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 33662035 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33662035 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 32721895 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32721895 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32721895 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32721895 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32721895 # number of overall hits +system.cpu1.icache.overall_hits::total 32721895 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 470070 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 470070 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 470070 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 470070 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 470070 # number of overall misses +system.cpu1.icache.overall_misses::total 470070 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6444934971 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6444934971 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6444934971 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6444934971 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6444934971 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6444934971 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33191965 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33191965 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33191965 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33191965 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33191965 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33191965 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014162 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014162 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014162 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014162 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014162 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014162 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13710.585596 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13710.585596 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13710.585596 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13710.585596 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13710.585596 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13710.585596 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1660,120 +1722,126 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377281 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 377281 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 377281 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 377281 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 377281 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 377281 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4407732788 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4407732788 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4407732788 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4407732788 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4407732788 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4407732788 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470070 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 470070 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 470070 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 470070 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 470070 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 470070 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5502849027 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5502849027 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5502849027 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5502849027 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5502849027 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5502849027 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6483750 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6483750 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6483750 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 6483750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019469 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019469 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019469 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11682.890970 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11682.890970 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11682.890970 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014162 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014162 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014162 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014162 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014162 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014162 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11706.445906 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11706.445906 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11706.445906 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11706.445906 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11706.445906 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11706.445906 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 220436 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.379597 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8230755 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 220801 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.276801 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106418022500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.379597 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920663 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920663 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 4389351 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4389351 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3673214 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3673214 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73456 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 73456 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73714 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 73714 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8062565 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8062565 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8062565 # number of overall hits -system.cpu1.dcache.overall_hits::total 8062565 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133803 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133803 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 112797 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 112797 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9752 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9752 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9418 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9418 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 246600 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 246600 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 246600 # number of overall misses -system.cpu1.dcache.overall_misses::total 246600 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1647983739 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1647983739 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4345457226 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4345457226 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77502998 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 77502998 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49351478 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 49351478 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5993440965 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5993440965 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5993440965 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5993440965 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4523154 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4523154 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3786011 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3786011 # number of WriteReq accesses(hits+misses) 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-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24304.302372 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24304.302372 # average overall miss latency +system.cpu1.dcache.tags.replacements 292078 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.633961 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11962120 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 292453 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.902709 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 85275256250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.633961 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921160 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.921160 # Average percentage of cache occupancy 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for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13012.976208 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13012.976208 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43808.625210 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 43808.625210 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8398.439620 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8398.439620 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5192.826221 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5192.826221 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27420.879483 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 27420.879483 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27420.879483 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27420.879483 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1782,66 +1850,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 199592 # number of writebacks -system.cpu1.dcache.writebacks::total 199592 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 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MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531061000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918822500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918822500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029582 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029582 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029793 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029793 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117200 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117200 # mshr miss rate for LoadLockedReq accesses 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36436.233003 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5946.677810 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5946.677810 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3242.115985 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3242.115985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265016 # number of writebacks +system.cpu1.dcache.writebacks::total 265016 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170562 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170562 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149956 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149956 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11055 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11055 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10052 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10052 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320518 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320518 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320518 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320518 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877722752 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877722752 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6246095798 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6246095798 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70722250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70722250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32100518 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32100518 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8123818550 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8123818550 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8123818550 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8123818550 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168605274000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168605274000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182596842 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182596842 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193787870842 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193787870842 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023964 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023964 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030127 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.118999 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.118999 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108319 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108319 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026501 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026501 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026501 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026501 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11009.033384 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11009.033384 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41652.856825 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41652.856825 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6397.308910 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6397.308910 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3193.445881 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3193.445881 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22262.461618 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22262.461618 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22262.461618 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22262.461618 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25345.904286 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25345.904286 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25345.904286 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25345.904286 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1855,6 +1923,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1863,10 +1933,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651879453001 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 651879453001 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651879453001 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 651879453001 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651789578751 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651789578751 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651789578751 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651789578751 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 925b86307..ea47afb6b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,7 +23,7 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -130,6 +130,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.dcache.tags @@ -146,6 +147,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.dtb] @@ -178,6 +180,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.icache.tags @@ -194,6 +197,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.interrupts] @@ -248,6 +252,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.cpu.l2cache.tags @@ -264,6 +269,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.cpu.toL2Bus] @@ -317,6 +323,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -333,6 +340,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.membus] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index eda827fb8..41742298b 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -1,7 +1,6 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -14,4 +13,3 @@ warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index b95a8c30f..866b5bc98 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:14:19 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 17:31:30 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2615716222000 because m5_exit instruction encountered +Exiting @ tick 2616536483000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index df8a2beae..9c560044d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.616536 # Nu sim_ticks 2616536483000 # Number of ticks simulated final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 343075 # Simulator instruction rate (inst/s) -host_op_rate 436578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14912044248 # Simulator tick rate (ticks/s) -host_mem_usage 444348 # Number of bytes of host memory used -host_seconds 175.46 # Real time elapsed on the host +host_inst_rate 577538 # Simulator instruction rate (inst/s) +host_op_rate 734941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25103147507 # Simulator tick rate (ticks/s) +host_mem_usage 400220 # Number of bytes of host memory used +host_seconds 104.23 # Real time elapsed on the host sim_insts 60197580 # Number of instructions simulated sim_ops 76603973 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory @@ -811,6 +813,7 @@ system.iobus.respLayer0.occupancy 2374820000 # La system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) system.iobus.respLayer1.occupancy 42035380750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 14995644 # DTB read hits @@ -886,6 +889,14 @@ system.cpu.icache.tags.warmup_cycle 19982971250 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 510.868538 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 62348185 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62348185 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 60634641 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 60634641 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 60634641 # number of demand (read+write) hits @@ -980,6 +991,18 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106711 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.774455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6898 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56267 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 17137304 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17137304 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8705 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3532 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 844551 # number of ReadReq hits @@ -1210,6 +1233,13 @@ system.cpu.dcache.tags.warmup_cycle 664004250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 511.876746 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 97755015 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 97755015 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 13195741 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13195741 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 9972594 # number of WriteReq hits @@ -1375,6 +1405,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index 44d2483e8..4f02f4af8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,12 +23,12 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -137,6 +137,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -153,6 +154,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -185,6 +187,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -201,6 +204,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -366,6 +370,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -382,6 +387,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -399,6 +405,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -415,6 +422,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr index 06edbeba7..38a425305 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr @@ -1,7 +1,6 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -11,7 +10,6 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -hack: be nice to actually delete the event here warn: LCD dual screen mode not supported warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout index 9b6e36065..312a2d840 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout @@ -1,9349 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simout -Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 07:58:36 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 17:32:17 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 -info: Using bootloader at address 0x80000000 -info: Entering event queue @ 0. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1000000000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2000000000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 3000000000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 4000000000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 5000000000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 6000000000. Starting simulation... -switching cpus -info: Entering event queue @ 6000003500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 7000003500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 8000003500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 9000003500. Starting simulation... -switching cpus -info: Entering event queue @ 9000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 10000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 11000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 12000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 13000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 14000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 15000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 16000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 17000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 18000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 19000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 20000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 21000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 22000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 23000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 24000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 25000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 26000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 27000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 28000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 29000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 30000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 31000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 32000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 33000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 34000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 35000006500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 36000006500. Starting simulation... -switching cpus -info: Entering event queue @ 36000007000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 37000007000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 38000007000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 39000007000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 40000007000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 41000007000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 42000007000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 43000007000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 44000007000. Starting simulation... -switching cpus -info: Entering event queue @ 44000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 45000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 46000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 47000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 48000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 49000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 50000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 51000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 52000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 53000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 54000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 55000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 56000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 57000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 58000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 59000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 60000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 61000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 62000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 63000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 64000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 65000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 66000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 67000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 68000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 69000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 70000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 71000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 72000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 73000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 74000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 75000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 76000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 77000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 78000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 79000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 80000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 81000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 82000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 83000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 84000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 85000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 86000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 87000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 88000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 89000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 90000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 91000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 92000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 93000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 94000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 95000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 96000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 97000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 98000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 99000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 100000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 101000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 102000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 103000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 104000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 105000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 106000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 107000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 108000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 109000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 110000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 111000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 112000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 113000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 114000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 115000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 116000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 117000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 118000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 119000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 120000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 121000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 122000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 123000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 124000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 125000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 126000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 127000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 128000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 129000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 130000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 131000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 132000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 133000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 134000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 135000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 136000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 137000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 138000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 139000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 140000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 141000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 142000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 143000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 144000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 145000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 146000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 147000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 148000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 149000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 150000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 151000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 152000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 153000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 154000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 155000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 156000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 157000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 158000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 159000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 160000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 161000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 162000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 163000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 164000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 165000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 166000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 167000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 168000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 169000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 170000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 171000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 172000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 173000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 174000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 175000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 176000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 177000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 178000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 179000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 180000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 181000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 182000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 183000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 184000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 185000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 186000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 187000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 188000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 189000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 190000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 191000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 192000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 193000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 194000010500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 195000010500. Starting simulation... -switching cpus -info: Entering event queue @ 195000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 196000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 197000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 198000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 199000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 200000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 201000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 202000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 203000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 204000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 205000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 206000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 207000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 208000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 209000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 210000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 211000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 212000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 213000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 214000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 215000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 216000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 217000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 218000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 219000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 220000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 221000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 222000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 223000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 224000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 225000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 226000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 227000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 228000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 229000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 230000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 231000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 232000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 233000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 234000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 235000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 236000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 237000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 238000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 239000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 240000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 241000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 242000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 243000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 244000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 245000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 246000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 247000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 248000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 249000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 250000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 251000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 252000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 253000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 254000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 255000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 256000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 257000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 258000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 259000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 260000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 261000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 262000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 263000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 264000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 265000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 266000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 267000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 268000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 269000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 270000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 271000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 272000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 273000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 274000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 275000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 276000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 277000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 278000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 279000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 280000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 281000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 282000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 283000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 284000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 285000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 286000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 287000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 288000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 289000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 290000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 291000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 292000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 293000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 294000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 295000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 296000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 297000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 298000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 299000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 300000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 301000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 302000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 303000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 304000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 305000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 306000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 307000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 308000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 309000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 310000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 311000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 312000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 313000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 314000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 315000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 316000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 317000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 318000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 319000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 320000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 321000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 322000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 323000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 324000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 325000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 326000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 327000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 328000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 329000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 330000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 331000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 332000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 333000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 334000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 335000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 336000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 337000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 338000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 339000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 340000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 341000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 342000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 343000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 344000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 345000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 346000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 347000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 348000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 349000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 350000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 351000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 352000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 353000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 354000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 355000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 356000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 357000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 358000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 359000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 360000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 361000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 362000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 363000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 364000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 365000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 366000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 367000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 368000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 369000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 370000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 371000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 372000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 373000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 374000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 375000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 376000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 377000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 378000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 379000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 380000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 381000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 382000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 383000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 384000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 385000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 386000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 387000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 388000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 389000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 390000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 391000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 392000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 393000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 394000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 395000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 396000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 397000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 398000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 399000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 400000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 401000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 402000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 403000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 404000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 405000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 406000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 407000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 408000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 409000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 410000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 411000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 412000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 413000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 414000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 415000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 416000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 417000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 418000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 419000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 420000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 421000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 422000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 423000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 424000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 425000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 426000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 427000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 428000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 429000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 430000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 431000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 432000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 433000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 434000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 435000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 436000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 437000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 438000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 439000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 440000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 441000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 442000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 443000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 444000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 445000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 446000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 447000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 448000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 449000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 450000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 451000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 452000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 453000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 454000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 455000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 456000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 457000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 458000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 459000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 460000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 461000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 462000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 463000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 464000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 465000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 466000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 467000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 468000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 469000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 470000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 471000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 472000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 473000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 474000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 475000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 476000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 477000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 478000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 479000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 480000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 481000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 482000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 483000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 484000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 485000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 486000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 487000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 488000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 489000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 490000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 491000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 492000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 493000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 494000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 495000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 496000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 497000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 498000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 499000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 500000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 501000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 502000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 503000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 504000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 505000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 506000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 507000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 508000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 509000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 510000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 511000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 512000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 513000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 514000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 515000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 516000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 517000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 518000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 519000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 520000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 521000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 522000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 523000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 524000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 525000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 526000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 527000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 528000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 529000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 530000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 531000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 532000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 533000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 534000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 535000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 536000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 537000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 538000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 539000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 540000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 541000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 542000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 543000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 544000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 545000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 546000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 547000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 548000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 549000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 550000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 551000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 552000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 553000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 554000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 555000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 556000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 557000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 558000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 559000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 560000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 561000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 562000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 563000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 564000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 565000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 566000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 567000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 568000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 569000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 570000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 571000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 572000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 573000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 574000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 575000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 576000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 577000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 578000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 579000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 580000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 581000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 582000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 583000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 584000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 585000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 586000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 587000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 588000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 589000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 590000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 591000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 592000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 593000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 594000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 595000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 596000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 597000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 598000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 599000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 600000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 601000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 602000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 603000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 604000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 605000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 606000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 607000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 608000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 609000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 610000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 611000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 612000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 613000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 614000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 615000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 616000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 617000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 618000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 619000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 620000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 621000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 622000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 623000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 624000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 625000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 626000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 627000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 628000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 629000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 630000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 631000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 632000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 633000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 634000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 635000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 636000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 637000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 638000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 639000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 640000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 641000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 642000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 643000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 644000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 645000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 646000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 647000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 648000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 649000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 650000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 651000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 652000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 653000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 654000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 655000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 656000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 657000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 658000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 659000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 660000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 661000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 662000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 663000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 664000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 665000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 666000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 667000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 668000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 669000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 670000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 671000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 672000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 673000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 674000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 675000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 676000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 677000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 678000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 679000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 680000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 681000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 682000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 683000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 684000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 685000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 686000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 687000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 688000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 689000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 690000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 691000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 692000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 693000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 694000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 695000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 696000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 697000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 698000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 699000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 700000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 701000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 702000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 703000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 704000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 705000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 706000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 707000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 708000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 709000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 710000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 711000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 712000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 713000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 714000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 715000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 716000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 717000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 718000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 719000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 720000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 721000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 722000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 723000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 724000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 725000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 726000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 727000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 728000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 729000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 730000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 731000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 732000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 733000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 734000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 735000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 736000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 737000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 738000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 739000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 740000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 741000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 742000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 743000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 744000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 745000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 746000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 747000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 748000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 749000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 750000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 751000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 752000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 753000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 754000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 755000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 756000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 757000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 758000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 759000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 760000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 761000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 762000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 763000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 764000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 765000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 766000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 767000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 768000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 769000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 770000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 771000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 772000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 773000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 774000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 775000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 776000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 777000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 778000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 779000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 780000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 781000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 782000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 783000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 784000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 785000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 786000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 787000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 788000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 789000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 790000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 791000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 792000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 793000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 794000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 795000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 796000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 797000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 798000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 799000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 800000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 801000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 802000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 803000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 804000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 805000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 806000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 807000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 808000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 809000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 810000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 811000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 812000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 813000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 814000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 815000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 816000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 817000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 818000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 819000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 820000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 821000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 822000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 823000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 824000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 825000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 826000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 827000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 828000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 829000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 830000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 831000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 832000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 833000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 834000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 835000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 836000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 837000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 838000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 839000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 840000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 841000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 842000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 843000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 844000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 845000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 846000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 847000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 848000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 849000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 850000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 851000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 852000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 853000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 854000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 855000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 856000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 857000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 858000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 859000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 860000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 861000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 862000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 863000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 864000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 865000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 866000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 867000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 868000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 869000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 870000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 871000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 872000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 873000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 874000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 875000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 876000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 877000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 878000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 879000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 880000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 881000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 882000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 883000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 884000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 885000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 886000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 887000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 888000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 889000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 890000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 891000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 892000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 893000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 894000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 895000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 896000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 897000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 898000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 899000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 900000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 901000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 902000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 903000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 904000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 905000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 906000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 907000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 908000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 909000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 910000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 911000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 912000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 913000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 914000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 915000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 916000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 917000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 918000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 919000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 920000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 921000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 922000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 923000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 924000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 925000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 926000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 927000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 928000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 929000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 930000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 931000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 932000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 933000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 934000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 935000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 936000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 937000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 938000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 939000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 940000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 941000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 942000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 943000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 944000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 945000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 946000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 947000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 948000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 949000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 950000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 951000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 952000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 953000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 954000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 955000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 956000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 957000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 958000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 959000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 960000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 961000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 962000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 963000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 964000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 965000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 966000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 967000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 968000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 969000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 970000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 971000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 972000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 973000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 974000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 975000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 976000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 977000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 978000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 979000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 980000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 981000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 982000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 983000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 984000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 985000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 986000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 987000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 988000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 989000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 990000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 991000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 992000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 993000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 994000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 995000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 996000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 997000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 998000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 999000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1000000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1001000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1002000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1003000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1004000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1005000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1006000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1007000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1008000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1009000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1010000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1011000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1012000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1013000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1014000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1015000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1016000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1017000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1018000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1019000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1020000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1021000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1022000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1023000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1024000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1025000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1026000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1027000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1028000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1029000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1030000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1031000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1032000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1033000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1034000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1035000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1036000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1037000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1038000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1039000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1040000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1041000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1042000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1043000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1044000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1045000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1046000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1047000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1048000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1049000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1050000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1051000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1052000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1053000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1054000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1055000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1056000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1057000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1058000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1059000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1060000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1061000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1062000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1063000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1064000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1065000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1066000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1067000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1068000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1069000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1070000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1071000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1072000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1073000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1074000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1075000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1076000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1077000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1078000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1079000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1080000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1081000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1082000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1083000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1084000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1085000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1086000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1087000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1088000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1089000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1090000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1091000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1092000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1093000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1094000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1095000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1096000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1097000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1098000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1099000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1100000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1101000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1102000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1103000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1104000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1105000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1106000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1107000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1108000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1109000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1110000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1111000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1112000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1113000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1114000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1115000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1116000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1117000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1118000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1119000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1120000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1121000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1122000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1123000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1124000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1125000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1126000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1127000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1128000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1129000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1130000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1131000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1132000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1133000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1134000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1135000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1136000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1137000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1138000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1139000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1140000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1141000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1142000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1143000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1144000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1145000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1146000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1147000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1148000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1149000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1150000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1151000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1152000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1153000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1154000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1155000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1156000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1157000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1158000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1159000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1160000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1161000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1162000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1163000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1164000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1165000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1166000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1167000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1168000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1169000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1170000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1171000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1172000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1173000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1174000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1175000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1176000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1177000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1178000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1179000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1180000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1181000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1182000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1183000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1184000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1185000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1186000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1187000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1188000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1189000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1190000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1191000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1192000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1193000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1194000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1195000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1196000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1197000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1198000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1199000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1200000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1201000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1202000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1203000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1204000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1205000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1206000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1207000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1208000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1209000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1210000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1211000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1212000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1213000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1214000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1215000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1216000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1217000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1218000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1219000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1220000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1221000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1222000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1223000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1224000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1225000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1226000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1227000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1228000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1229000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1230000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1231000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1232000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1233000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1234000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1235000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1236000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1237000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1238000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1239000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1240000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1241000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1242000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1243000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1244000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1245000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1246000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1247000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1248000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1249000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1250000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1251000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1252000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1253000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1254000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1255000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1256000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1257000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1258000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1259000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1260000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1261000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1262000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1263000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1264000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1265000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1266000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1267000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1268000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1269000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1270000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1271000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1272000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1273000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1274000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1275000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1276000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1277000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1278000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1279000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1280000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1281000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1282000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1283000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1284000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1285000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1286000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1287000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1288000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1289000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1290000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1291000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1292000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1293000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1294000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1295000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1296000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1297000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1298000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1299000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1300000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1301000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1302000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1303000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1304000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1305000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1306000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1307000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1308000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1309000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1310000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1311000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1312000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1313000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1314000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1315000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1316000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1317000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1318000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1319000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1320000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1321000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1322000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1323000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1324000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1325000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1326000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1327000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1328000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1329000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1330000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1331000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1332000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1333000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1334000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1335000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1336000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1337000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1338000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1339000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1340000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1341000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1342000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1343000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1344000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1345000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1346000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1347000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1348000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1349000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1350000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1351000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1352000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1353000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1354000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1355000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1356000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1357000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1358000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1359000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1360000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1361000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1362000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1363000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1364000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1365000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1366000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1367000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1368000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1369000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1370000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1371000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1372000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1373000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1374000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1375000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1376000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1377000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1378000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1379000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1380000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1381000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1382000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1383000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1384000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1385000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1386000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1387000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1388000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1389000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1390000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1391000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1392000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1393000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1394000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1395000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1396000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1397000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1398000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1399000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1400000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1401000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1402000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1403000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1404000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1405000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1406000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1407000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1408000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1409000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1410000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1411000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1412000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1413000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1414000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1415000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1416000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1417000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1418000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1419000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1420000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1421000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1422000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1423000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1424000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1425000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1426000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1427000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1428000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1429000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1430000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1431000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1432000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1433000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1434000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1435000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1436000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1437000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1438000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1439000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1440000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1441000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1442000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1443000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1444000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1445000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1446000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1447000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1448000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1449000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1450000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1451000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1452000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1453000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1454000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1455000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1456000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1457000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1458000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1459000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1460000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1461000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1462000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1463000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1464000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1465000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1466000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1467000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1468000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1469000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1470000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1471000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1472000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1473000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1474000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1475000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1476000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1477000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1478000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1479000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1480000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1481000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1482000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1483000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1484000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1485000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1486000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1487000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1488000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1489000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1490000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1491000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1492000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1493000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1494000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1495000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1496000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1497000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1498000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1499000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1500000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1501000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1502000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1503000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1504000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1505000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1506000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1507000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1508000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1509000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1510000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1511000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1512000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1513000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1514000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1515000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1516000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1517000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1518000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1519000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1520000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1521000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1522000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1523000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1524000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1525000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1526000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1527000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1528000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1529000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1530000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1531000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1532000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1533000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1534000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1535000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1536000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1537000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1538000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1539000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1540000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1541000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1542000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1543000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1544000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1545000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1546000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1547000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1548000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1549000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1550000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1551000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1552000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1553000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1554000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1555000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1556000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1557000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1558000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1559000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1560000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1561000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1562000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1563000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1564000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1565000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1566000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1567000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1568000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1569000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1570000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1571000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1572000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1573000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1574000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1575000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1576000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1577000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1578000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1579000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1580000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1581000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1582000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1583000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1584000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1585000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1586000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1587000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1588000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1589000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1590000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1591000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1592000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1593000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1594000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1595000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1596000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1597000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1598000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1599000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1600000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1601000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1602000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1603000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1604000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1605000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1606000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1607000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1608000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1609000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1610000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1611000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1612000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1613000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1614000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1615000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1616000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1617000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1618000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1619000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1620000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1621000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1622000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1623000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1624000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1625000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1626000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1627000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1628000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1629000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1630000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1631000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1632000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1633000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1634000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1635000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1636000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1637000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1638000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1639000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1640000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1641000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1642000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1643000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1644000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1645000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1646000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1647000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1648000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1649000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1650000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1651000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1652000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1653000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1654000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1655000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1656000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1657000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1658000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1659000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1660000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1661000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1662000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1663000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1664000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1665000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1666000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1667000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1668000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1669000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1670000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1671000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1672000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1673000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1674000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1675000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1676000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1677000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1678000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1679000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1680000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1681000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1682000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1683000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1684000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1685000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1686000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1687000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1688000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1689000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1690000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1691000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1692000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1693000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1694000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1695000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1696000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1697000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1698000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1699000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1700000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1701000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1702000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1703000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1704000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1705000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1706000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1707000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1708000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1709000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1710000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1711000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1712000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1713000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1714000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1715000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1716000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1717000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1718000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1719000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1720000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1721000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1722000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1723000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1724000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1725000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1726000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1727000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1728000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1729000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1730000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1731000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1732000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1733000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1734000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1735000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1736000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1737000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1738000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1739000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1740000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1741000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1742000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1743000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1744000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1745000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1746000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1747000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1748000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1749000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1750000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1751000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1752000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1753000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1754000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1755000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1756000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1757000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1758000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1759000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1760000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1761000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1762000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1763000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1764000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1765000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1766000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1767000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1768000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1769000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1770000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1771000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1772000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1773000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1774000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1775000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1776000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1777000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1778000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1779000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1780000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1781000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1782000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1783000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1784000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1785000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1786000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1787000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1788000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1789000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1790000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1791000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1792000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1793000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1794000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1795000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1796000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1797000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1798000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1799000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1800000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1801000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1802000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1803000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1804000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1805000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1806000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1807000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1808000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1809000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1810000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1811000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1812000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1813000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1814000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1815000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1816000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1817000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1818000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1819000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1820000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1821000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1822000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1823000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1824000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1825000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1826000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1827000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1828000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1829000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1830000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1831000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1832000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1833000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1834000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1835000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1836000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1837000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1838000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1839000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1840000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1841000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1842000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1843000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1844000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1845000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1846000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1847000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1848000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1849000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1850000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1851000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1852000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1853000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1854000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1855000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1856000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1857000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1858000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1859000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1860000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1861000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1862000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1863000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1864000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1865000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1866000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1867000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1868000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1869000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1870000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1871000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1872000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1873000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1874000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1875000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1876000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1877000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1878000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1879000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1880000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1881000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1882000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1883000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1884000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1885000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1886000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1887000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1888000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1889000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1890000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1891000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1892000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1893000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1894000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1895000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1896000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1897000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1898000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1899000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1900000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1901000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1902000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1903000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1904000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1905000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1906000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1907000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1908000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1909000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1910000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1911000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1912000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1913000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1914000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1915000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1916000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1917000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1918000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1919000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1920000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1921000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1922000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1923000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1924000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1925000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1926000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1927000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1928000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1929000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1930000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1931000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1932000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1933000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1934000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1935000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1936000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1937000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1938000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1939000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1940000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1941000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1942000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1943000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1944000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1945000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1946000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1947000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1948000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1949000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1950000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1951000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1952000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1953000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1954000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1955000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1956000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1957000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1958000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1959000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1960000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1961000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1962000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1963000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1964000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1965000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1966000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1967000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1968000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1969000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1970000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1971000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1972000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1973000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1974000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1975000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1976000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1977000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1978000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1979000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1980000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1981000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1982000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1983000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1984000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1985000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1986000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1987000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1988000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1989000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1990000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1991000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1992000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1993000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1994000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1995000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1996000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1997000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1998000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 1999000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2000000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2001000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2002000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2003000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2004000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2005000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2006000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2007000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2008000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2009000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2010000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2011000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2012000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2013000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2014000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2015000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2016000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2017000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2018000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2019000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2020000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2021000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2022000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2023000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2024000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2025000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2026000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2027000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2028000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2029000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2030000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2031000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2032000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2033000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2034000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2035000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2036000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2037000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2038000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2039000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2040000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2041000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2042000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2043000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2044000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2045000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2046000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2047000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2048000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2049000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2050000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2051000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2052000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2053000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2054000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2055000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2056000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2057000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2058000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2059000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2060000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2061000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2062000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2063000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2064000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2065000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2066000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2067000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2068000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2069000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2070000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2071000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2072000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2073000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2074000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2075000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2076000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2077000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2078000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2079000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2080000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2081000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2082000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2083000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2084000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2085000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2086000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2087000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2088000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2089000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2090000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2091000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2092000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2093000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2094000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2095000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2096000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2097000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2098000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2099000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2100000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2101000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2102000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2103000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2104000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2105000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2106000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2107000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2108000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2109000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2110000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2111000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2112000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2113000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2114000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2115000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2116000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2117000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2118000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2119000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2120000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2121000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2122000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2123000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2124000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2125000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2126000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2127000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2128000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2129000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2130000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2131000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2132000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2133000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2134000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2135000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2136000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2137000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2138000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2139000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2140000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2141000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2142000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2143000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2144000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2145000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2146000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2147000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2148000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2149000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2150000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2151000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2152000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2153000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2154000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2155000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2156000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2157000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2158000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2159000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2160000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2161000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2162000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2163000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2164000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2165000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2166000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2167000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2168000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2169000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2170000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2171000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2172000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2173000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2174000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2175000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2176000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2177000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2178000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2179000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2180000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2181000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2182000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2183000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2184000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2185000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2186000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2187000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2188000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2189000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2190000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2191000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2192000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2193000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2194000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2195000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2196000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2197000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2198000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2199000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2200000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2201000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2202000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2203000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2204000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2205000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2206000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2207000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2208000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2209000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2210000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2211000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2212000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2213000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2214000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2215000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2216000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2217000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2218000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2219000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2220000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2221000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2222000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2223000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2224000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2225000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2226000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2227000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2228000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2229000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2230000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2231000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2232000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2233000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2234000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2235000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2236000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2237000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2238000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2239000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2240000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2241000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2242000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2243000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2244000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2245000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2246000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2247000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2248000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2249000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2250000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2251000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2252000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2253000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2254000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2255000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2256000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2257000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2258000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2259000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2260000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2261000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2262000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2263000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2264000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2265000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2266000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2267000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2268000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2269000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2270000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2271000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2272000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2273000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2274000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2275000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2276000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2277000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2278000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2279000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2280000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2281000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2282000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2283000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2284000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2285000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2286000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2287000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2288000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2289000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2290000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2291000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2292000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2293000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2294000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2295000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2296000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2297000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2298000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2299000013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2300000013500. Starting simulation... -switching cpus -info: Entering event queue @ 2300000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2301000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2302000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2303000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2304000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2305000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2306000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2307000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2308000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2309000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2310000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2311000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2312000016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2313000016000. Starting simulation... -switching cpus -info: Entering event queue @ 2313000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2314000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2315000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2316000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2317000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2318000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2319000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2320000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2321000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2322000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2323000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2324000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2325000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2326000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2327000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2328000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2329000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2330000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -switching cpus -info: Entering event queue @ 2331000020000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2332000020000. Starting simulation... -switching cpus -info: Entering event queue @ 2332000020500. Starting simulation... diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 7eb912550..af2c3099c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,25 +4,15 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 840369 # Simulator instruction rate (inst/s) -host_op_rate 1080663 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32452660609 # Simulator tick rate (ticks/s) -host_mem_usage 444352 # Number of bytes of host memory used -host_seconds 71.88 # Real time elapsed on the host +host_inst_rate 1583722 # Simulator instruction rate (inst/s) +host_op_rate 2036569 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61158803315 # Simulator tick rate (ticks/s) +host_mem_usage 399324 # Number of bytes of host memory used +host_seconds 38.14 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory @@ -74,9 +64,22 @@ system.physmem.bw_total::cpu0.data 3386724 # To system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 55969561 # Throughput (bytes/s) system.membus.data_through_bus 130566366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 62242 # number of replacements system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. @@ -98,6 +101,18 @@ system.l2c.tags.occ_percent::cpu0.data 0.048104 # Av system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3589 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9187 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52391 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17104735 # Number of tag accesses +system.l2c.tags.data_accesses 17104735 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits @@ -321,6 +336,14 @@ system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 78 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 62285702 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62285702 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits @@ -377,6 +400,13 @@ system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 97632366 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 97632366 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits @@ -526,6 +556,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 299ddfd61..9b7646241 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic mem_ranges=0:134217727 @@ -144,6 +144,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.dcache.tags @@ -160,6 +161,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.dtb] @@ -192,6 +194,7 @@ mshrs=10 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=1024 system=system tags=system.cpu.dtb_walker_cache.tags @@ -208,6 +211,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=1024 [system.cpu.icache] @@ -225,6 +229,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.icache.tags @@ -241,6 +246,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.interrupts] @@ -289,6 +295,7 @@ mshrs=10 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=1024 system=system tags=system.cpu.itb_walker_cache.tags @@ -305,6 +312,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=1024 [system.cpu.l2cache] @@ -322,6 +330,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.cpu.l2cache.tags @@ -338,6 +347,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.cpu.toL2Bus] @@ -804,6 +814,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -820,6 +831,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.membus] @@ -1149,7 +1161,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1172,7 +1184,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr index 347fa32d8..bb1874a4f 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr @@ -1,4 +1,3 @@ -warn: add_child('terminal'): child 'terminal' already has parent warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections @@ -7,4 +6,3 @@ warn: x86 cpuid: unknown family 0x8086 warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index bbf756dc6..04f5d2889 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:42:07 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 17:30:13 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112126311000 because m5_exit instruction encountered +Exiting @ tick 5112126264500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 8eed6a1f4..168ad24c1 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 5.112126 # Nu sim_ticks 5112126264500 # Number of ticks simulated final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1049292 # Simulator instruction rate (inst/s) -host_op_rate 2148359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26829969216 # Simulator tick rate (ticks/s) -host_mem_usage 634884 # Number of bytes of host memory used -host_seconds 190.54 # Real time elapsed on the host +host_inst_rate 1777208 # Simulator instruction rate (inst/s) +host_op_rate 3638722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45442487875 # Simulator tick rate (ticks/s) +host_mem_usage 590176 # Number of bytes of host memory used +host_seconds 112.50 # Real time elapsed on the host sim_insts 199929810 # Number of instructions simulated sim_ops 409343850 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -58,6 +60,11 @@ system.iocache.tags.warmup_cycle 4994846763009 # C system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428616 # Number of tag accesses +system.iocache.tags.data_accesses 428616 # Number of data accesses system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -107,6 +114,8 @@ system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.iobus.throughput 2555207 # Throughput (bytes/s) system.iobus.data_through_bus 13062542 # Total data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 10224253904 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -142,6 +151,13 @@ system.cpu.icache.tags.warmup_cycle 148848615500 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 245107932 # Number of tag accesses +system.cpu.icache.tags.data_accesses 245107932 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 243525778 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 243525778 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 243525778 # number of demand (read+write) hits @@ -184,6 +200,13 @@ system.cpu.itb_walker_cache.tags.warmup_cycle 5102116468000 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026303 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 28774 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 28774 # Number of data accesses system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -232,6 +255,13 @@ system.cpu.dtb_walker_cache.tags.warmup_cycle 5100462243000 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 52398 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52398 # Number of data accesses system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits @@ -276,6 +306,13 @@ system.cpu.dcache.tags.warmup_cycle 7549500 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88813841 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88813841 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 12077531 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 12077531 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 8095378 # number of WriteReq hits @@ -339,6 +376,15 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20892 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39453 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32198887 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32198887 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 777739 # number of ReadReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index 4c888767a..d9f47005d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -14,10 +16,11 @@ boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table +eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -38,6 +41,7 @@ system_port=system.membus.slave[1] [system.acpi_description_table_pointer] type=X86ACPIRSDP children=xsdt +eventq_index=0 oem_id= revision=2 rsdt=Null @@ -48,6 +52,7 @@ type=X86ACPIXSDT creator_id= creator_revision=0 entries= +eventq_index=0 oem_id= oem_revision=0 oem_table_id= @@ -56,6 +61,7 @@ oem_table_id= type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 @@ -66,6 +72,7 @@ slave=system.iobus.master[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 @@ -75,6 +82,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -87,6 +95,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -111,6 +120,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -118,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -126,6 +137,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.dcache.tags @@ -140,18 +152,22 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -162,6 +178,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -170,6 +187,7 @@ mshrs=10 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=1024 system=system tags=system.cpu.dtb_walker_cache.tags @@ -184,7 +202,9 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=1024 [system.cpu.icache] @@ -193,6 +213,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -201,6 +222,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.icache.tags @@ -215,12 +237,15 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -231,16 +256,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -251,6 +279,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -259,6 +288,7 @@ mshrs=10 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=1024 system=system tags=system.cpu.itb_walker_cache.tags @@ -273,7 +303,9 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=1024 [system.cpu.l2cache] @@ -282,6 +314,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -290,6 +323,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.cpu.l2cache.tags @@ -304,12 +338,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -319,44 +356,52 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 entries3 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +eventq_index=0 [system.e820_table.entries0] type=X86E820Entry addr=0 +eventq_index=0 range_type=1 size=654336 [system.e820_table.entries1] type=X86E820Entry addr=654336 +eventq_index=0 range_type=2 size=394240 [system.e820_table.entries2] type=X86E820Entry addr=1048576 +eventq_index=0 range_type=1 size=133169152 [system.e820_table.entries3] type=X86E820Entry addr=4294901760 +eventq_index=0 range_type=2 size=65536 [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 +eventq_index=0 imcr_present=true spec_rev=4 @@ -364,6 +409,7 @@ spec_rev=4 type=X86IntelMPConfigTable children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +eventq_index=0 ext_entries=system.intel_mp_table.ext_entries local_apic=4276092928 oem_id= @@ -376,6 +422,7 @@ spec_rev=4 type=X86IntelMPProcessor bootstrap=true enable=true +eventq_index=0 family=0 feature_flags=0 local_apic_id=0 @@ -387,6 +434,7 @@ stepping=0 type=X86IntelMPIOAPIC address=4273995776 enable=true +eventq_index=0 id=1 version=17 @@ -394,16 +442,19 @@ version=17 type=X86IntelMPBus bus_id=0 bus_type=ISA +eventq_index=0 [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 bus_type=PCI +eventq_index=0 [system.intel_mp_table.base_entries04] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=16 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=1 @@ -414,6 +465,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -424,6 +476,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=2 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -434,6 +487,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -444,6 +498,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=1 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -454,6 +509,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -464,6 +520,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=3 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -474,6 +531,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -484,6 +542,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=4 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -494,6 +553,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -504,6 +564,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=5 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -514,6 +575,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -524,6 +586,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=6 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -534,6 +597,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -544,6 +608,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=7 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -554,6 +619,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -564,6 +630,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=8 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -574,6 +641,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -584,6 +652,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=9 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -594,6 +663,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -604,6 +674,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=10 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -614,6 +685,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -624,6 +696,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=11 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -634,6 +707,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -644,6 +718,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=12 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -654,6 +729,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -664,6 +740,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=13 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -674,6 +751,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -684,6 +762,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=14 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -693,16 +772,19 @@ trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy bus_id=0 +eventq_index=0 parent_bus=1 subtractive_decode=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -716,6 +798,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -724,6 +807,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -738,13 +822,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.membus] type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -756,6 +843,7 @@ slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side sy [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -772,13 +860,15 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +eventq_index=0 intrctrl=system.intrctrl system=system [system.pc.behind_pci] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -797,6 +887,7 @@ pio=system.iobus.master[12] type=Uart8250 children=terminal clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -806,13 +897,7 @@ pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.pc.com_1.terminal] -type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -821,6 +906,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -838,6 +924,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -855,6 +942,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -872,6 +960,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -889,6 +978,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -907,6 +997,7 @@ pio=system.iobus.master[11] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.pc @@ -919,6 +1010,7 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 +eventq_index=0 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -931,6 +1023,7 @@ speaker=system.pc.south_bridge.speaker type=Cmos children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -940,10 +1033,12 @@ pio=system.iobus.master[1] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.dma1] type=I8237 clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -972,6 +1067,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -981,8 +1077,40 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=128 Revision=0 Status=640 @@ -994,6 +1122,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=4 @@ -1010,19 +1139,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks0.image [system.pc.south_bridge.ide.disks0.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +eventq_index=0 +image_file=/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1030,102 +1162,120 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks1.image [system.pc.south_bridge.ide.disks1.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks1.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines0.sink source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=0 [system.pc.south_bridge.int_lines1] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines1.sink source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=2 [system.pc.south_bridge.int_lines2] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines2.sink source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines3] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines3.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines4.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines5.sink source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=1 [system.pc.south_bridge.int_lines6] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines6.sink source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 clk_domain=system.clk_domain +eventq_index=0 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1140,6 +1290,7 @@ children=keyboard_int_pin mouse_int_pin clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 +eventq_index=0 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 @@ -1149,14 +1300,17 @@ pio=system.iobus.master[5] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.keyboard.mouse_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic1] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1167,11 +1321,13 @@ pio=system.iobus.master[6] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic2] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1182,11 +1338,13 @@ pio=system.iobus.master[7] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pit] type=I8254 children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1195,10 +1353,12 @@ pio=system.iobus.master[8] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.speaker] type=PcSpeaker clk_domain=system.clk_domain +eventq_index=0 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1217,6 +1377,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1228,19 +1389,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[3] [system.smbios_table] type=X86SMBiosSMBiosTable children=structures +eventq_index=0 major_version=2 minor_version=5 structures=system.smbios_table.structures @@ -1251,6 +1416,7 @@ characteristic_ext_bytes= characteristics= emb_cont_firmware_major=0 emb_cont_firmware_minor=0 +eventq_index=0 major=0 minor=0 release_date=06/08/2008 @@ -1261,5 +1427,6 @@ version= [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr index 347fa32d8..bb1874a4f 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr @@ -1,4 +1,3 @@ -warn: add_child('terminal'): child 'terminal' already has parent warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections @@ -7,4 +6,3 @@ warn: x86 cpuid: unknown family 0x8086 warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 3c12ad36c..f1feb2eac 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:55:08 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 17:30:19 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5192277855000 because m5_exit instruction encountered +Exiting @ tick 5196390180000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 79d47dc5b..b371db56a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 5.196390 # Nu sim_ticks 5196390180000 # Number of ticks simulated final_tick 5196390180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 893068 # Simulator instruction rate (inst/s) -host_op_rate 1721530 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36161085452 # Simulator tick rate (ticks/s) -host_mem_usage 586592 # Number of bytes of host memory used -host_seconds 143.70 # Real time elapsed on the host +host_inst_rate 991078 # Simulator instruction rate (inst/s) +host_op_rate 1910460 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40129605273 # Simulator tick rate (ticks/s) +host_mem_usage 591204 # Number of bytes of host memory used +host_seconds 129.49 # Real time elapsed on the host sim_insts 128334813 # Number of instructions simulated sim_ops 247385808 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 2883712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -419,6 +421,11 @@ system.iocache.tags.warmup_cycle 5049776837000 # C system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.113099 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007069 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.007069 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428004 # Number of tag accesses +system.iocache.tags.data_accesses 428004 # Number of data accesses system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses system.iocache.ReadReq_misses::total 836 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -616,6 +623,8 @@ system.iobus.respLayer1.occupancy 52989250 # La system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 10392780360 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -651,6 +660,14 @@ system.cpu.icache.tags.warmup_cycle 161436066250 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 510.351939 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.996781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.996781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 146161971 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146161971 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 144584753 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 144584753 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 144584753 # number of demand (read+write) hits @@ -729,6 +746,14 @@ system.cpu.itb_walker_cache.tags.warmup_cycle 5169682535000 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069761 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191860 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.191860 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29050 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29050 # Number of data accesses system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7617 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 7617 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -813,6 +838,14 @@ system.cpu.dtb_walker_cache.tags.warmup_cycle 5168018375000 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052475 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315780 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315780 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53026 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53026 # Number of data accesses system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12806 # number of ReadReq hits system.cpu.dtb_walker_cache.ReadReq_hits::total 12806 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12806 # number of demand (read+write) hits @@ -893,6 +926,14 @@ system.cpu.dcache.tags.warmup_cycle 50992250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 511.997026 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88253354 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88253354 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 11993197 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 11993197 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 8040328 # number of WriteReq hits @@ -1047,6 +1088,15 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052573 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.170366 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.987720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64716 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2864 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4951 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56789 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987488 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32180081 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32180081 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6740 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2903 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 775712 # number of ReadReq hits diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 0062dcbb2..71b238fb8 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -5,16 +5,17 @@ boot_cpu_frequency=250 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=drivesys.clk_domain -console=/dist/m5/system/binaries/console +console=/dist/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=drivesys.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal -readfile=/z/m5/regression/zizzer/gem5/configs/boot/netperf-server.rcS +pal=/dist/binaries/ts_osfpal +readfile=/work/gem5.ext/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -31,6 +32,7 @@ system_port=drivesys.membus.slave[0] type=Bridge clk_domain=drivesys.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -40,6 +42,7 @@ slave=drivesys.membus.master[0] [drivesys.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=drivesys.voltage_domain [drivesys.cpu] @@ -52,6 +55,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=drivesys.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -82,43 +86,53 @@ icache_port=drivesys.membus.slave[1] [drivesys.cpu.clk_domain] type=SrcClockDomain clock=250 +eventq_index=0 voltage_domain=drivesys.voltage_domain [drivesys.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [drivesys.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [drivesys.cpu.isa] type=AlphaISA +eventq_index=0 +system=drivesys [drivesys.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [drivesys.cpu.tracer] type=ExeTracer +eventq_index=0 [drivesys.disk0] type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=drivesys.disk0.image [drivesys.disk0.image] type=CowDiskImage children=child child=drivesys.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [drivesys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/dist/disks/linux-latest.img read_only=true [drivesys.disk2] @@ -126,29 +140,34 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=drivesys.disk2.image [drivesys.disk2.image] type=CowDiskImage children=child child=drivesys.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [drivesys.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/dist/disks/linux-bigswap2.img read_only=true [drivesys.intrctrl] type=IntrControl +eventq_index=0 sys=drivesys [drivesys.iobridge] type=Bridge clk_domain=drivesys.clk_domain delay=50000 +eventq_index=0 ranges=0:134217727 req_size=16 resp_size=16 @@ -158,6 +177,7 @@ slave=drivesys.iobus.master[29] [drivesys.iobus] type=NoncoherentBus clk_domain=drivesys.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -169,6 +189,7 @@ slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet. type=CoherentBus children=badaddr_responder clk_domain=drivesys.clk_domain +eventq_index=0 header_cycles=1 system=drivesys use_default_range=false @@ -180,6 +201,7 @@ slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port dri [drivesys.membus.badaddr_responder] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -199,6 +221,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=drivesys.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -210,15 +233,18 @@ port=drivesys.membus.master[1] type=SimpleDisk children=disk disk=drivesys.simple_disk.disk +eventq_index=0 system=drivesys [drivesys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/dist/disks/linux-latest.img read_only=true [drivesys.terminal] type=Terminal +eventq_index=0 intr_control=drivesys.intrctrl number=0 output=true @@ -227,6 +253,7 @@ port=3456 [drivesys.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=drivesys.intrctrl system=drivesys @@ -235,6 +262,7 @@ type=AlphaBackdoor clk_domain=drivesys.clk_domain cpu=drivesys.cpu disk=drivesys.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=drivesys.tsunami @@ -245,6 +273,7 @@ pio=drivesys.iobus.master[24] [drivesys.tsunami.cchip] type=TsunamiCChip clk_domain=drivesys.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=drivesys @@ -274,6 +303,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -283,8 +313,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -301,6 +363,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:02 intr_delay=10000000 pci_bus=0 @@ -325,11 +388,13 @@ pio=drivesys.iobus.master[27] [drivesys.tsunami.ethernet.clk_domain] type=SrcClockDomain clock=2000 +eventq_index=0 voltage_domain=drivesys.voltage_domain [drivesys.tsunami.fake_OROM] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -347,6 +412,7 @@ pio=drivesys.iobus.master[8] [drivesys.tsunami.fake_ata0] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -364,6 +430,7 @@ pio=drivesys.iobus.master[19] [drivesys.tsunami.fake_ata1] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -381,6 +448,7 @@ pio=drivesys.iobus.master[20] [drivesys.tsunami.fake_pnp_addr] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -398,6 +466,7 @@ pio=drivesys.iobus.master[9] [drivesys.tsunami.fake_pnp_read0] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -415,6 +484,7 @@ pio=drivesys.iobus.master[11] [drivesys.tsunami.fake_pnp_read1] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -432,6 +502,7 @@ pio=drivesys.iobus.master[12] [drivesys.tsunami.fake_pnp_read2] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -449,6 +520,7 @@ pio=drivesys.iobus.master[13] [drivesys.tsunami.fake_pnp_read3] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -466,6 +538,7 @@ pio=drivesys.iobus.master[14] [drivesys.tsunami.fake_pnp_read4] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -483,6 +556,7 @@ pio=drivesys.iobus.master[15] [drivesys.tsunami.fake_pnp_read5] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -500,6 +574,7 @@ pio=drivesys.iobus.master[16] [drivesys.tsunami.fake_pnp_read6] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -517,6 +592,7 @@ pio=drivesys.iobus.master[17] [drivesys.tsunami.fake_pnp_read7] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -534,6 +610,7 @@ pio=drivesys.iobus.master[18] [drivesys.tsunami.fake_pnp_write] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -551,6 +628,7 @@ pio=drivesys.iobus.master[10] [drivesys.tsunami.fake_ppc] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -568,6 +646,7 @@ pio=drivesys.iobus.master[7] [drivesys.tsunami.fake_sm_chip] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -585,6 +664,7 @@ pio=drivesys.iobus.master[2] [drivesys.tsunami.fake_uart1] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -602,6 +682,7 @@ pio=drivesys.iobus.master[3] [drivesys.tsunami.fake_uart2] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -619,6 +700,7 @@ pio=drivesys.iobus.master[4] [drivesys.tsunami.fake_uart3] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -636,6 +718,7 @@ pio=drivesys.iobus.master[5] [drivesys.tsunami.fake_uart4] type=IsaFake clk_domain=drivesys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -654,6 +737,7 @@ pio=drivesys.iobus.master[6] type=BadDevice clk_domain=drivesys.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=drivesys @@ -681,6 +765,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -690,8 +775,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -703,6 +820,7 @@ clk_domain=drivesys.clk_domain config_latency=20000 ctrl_offset=0 disks=drivesys.disk0 drivesys.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -717,6 +835,7 @@ pio=drivesys.iobus.master[25] [drivesys.tsunami.io] type=TsunamiIO clk_domain=drivesys.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -729,6 +848,7 @@ pio=drivesys.iobus.master[22] [drivesys.tsunami.pchip] type=TsunamiPChip clk_domain=drivesys.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=drivesys @@ -739,6 +859,7 @@ pio=drivesys.iobus.master[1] type=PciConfigAll bus=0 clk_domain=drivesys.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=drivesys.tsunami @@ -749,6 +870,7 @@ pio=drivesys.iobus.default [drivesys.tsunami.uart] type=Uart8250 clk_domain=drivesys.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=drivesys.tsunami @@ -758,10 +880,12 @@ pio=drivesys.iobus.master[23] [drivesys.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 [etherdump] type=EtherDump +eventq_index=0 file=ethertrace maxlen=96 @@ -770,6 +894,7 @@ type=EtherLink delay=0 delay_var=0 dump=etherdump +eventq_index=0 speed=8000.000000 int0=testsys.tsunami.ethernet.interface int1=drivesys.tsunami.ethernet.interface @@ -777,7 +902,9 @@ int1=drivesys.tsunami.ethernet.interface [root] type=Root children=drivesys etherdump etherlink testsys +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -789,16 +916,17 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=testsys.clk_domain -console=/dist/m5/system/binaries/console +console=/dist/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=testsys.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal -readfile=/z/m5/regression/zizzer/gem5/configs/boot/netperf-stream-client.rcS +pal=/dist/binaries/ts_osfpal +readfile=/work/gem5.ext/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -815,6 +943,7 @@ system_port=testsys.membus.slave[0] type=Bridge clk_domain=testsys.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -824,6 +953,7 @@ slave=testsys.membus.master[0] [testsys.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=testsys.voltage_domain [testsys.cpu] @@ -836,6 +966,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=testsys.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -866,43 +997,53 @@ icache_port=testsys.membus.slave[1] [testsys.cpu.clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=testsys.voltage_domain [testsys.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [testsys.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [testsys.cpu.isa] type=AlphaISA +eventq_index=0 +system=testsys [testsys.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [testsys.cpu.tracer] type=ExeTracer +eventq_index=0 [testsys.disk0] type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=testsys.disk0.image [testsys.disk0.image] type=CowDiskImage children=child child=testsys.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [testsys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/dist/disks/linux-latest.img read_only=true [testsys.disk2] @@ -910,29 +1051,34 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=testsys.disk2.image [testsys.disk2.image] type=CowDiskImage children=child child=testsys.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [testsys.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/dist/disks/linux-bigswap2.img read_only=true [testsys.intrctrl] type=IntrControl +eventq_index=0 sys=testsys [testsys.iobridge] type=Bridge clk_domain=testsys.clk_domain delay=50000 +eventq_index=0 ranges=0:134217727 req_size=16 resp_size=16 @@ -942,6 +1088,7 @@ slave=testsys.iobus.master[29] [testsys.iobus] type=NoncoherentBus clk_domain=testsys.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -953,6 +1100,7 @@ slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma type=CoherentBus children=badaddr_responder clk_domain=testsys.clk_domain +eventq_index=0 header_cycles=1 system=testsys use_default_range=false @@ -964,6 +1112,7 @@ slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsy [testsys.membus.badaddr_responder] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -983,6 +1132,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=testsys.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -994,15 +1144,18 @@ port=testsys.membus.master[1] type=SimpleDisk children=disk disk=testsys.simple_disk.disk +eventq_index=0 system=testsys [testsys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/dist/disks/linux-latest.img read_only=true [testsys.terminal] type=Terminal +eventq_index=0 intr_control=testsys.intrctrl number=0 output=true @@ -1011,6 +1164,7 @@ port=3456 [testsys.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=testsys.intrctrl system=testsys @@ -1019,6 +1173,7 @@ type=AlphaBackdoor clk_domain=testsys.clk_domain cpu=testsys.cpu disk=testsys.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=testsys.tsunami @@ -1029,6 +1184,7 @@ pio=testsys.iobus.master[24] [testsys.tsunami.cchip] type=TsunamiCChip clk_domain=testsys.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=testsys @@ -1058,6 +1214,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -1067,8 +1224,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -1085,6 +1274,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -1109,11 +1299,13 @@ pio=testsys.iobus.master[27] [testsys.tsunami.ethernet.clk_domain] type=SrcClockDomain clock=2000 +eventq_index=0 voltage_domain=testsys.voltage_domain [testsys.tsunami.fake_OROM] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -1131,6 +1323,7 @@ pio=testsys.iobus.master[8] [testsys.tsunami.fake_ata0] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -1148,6 +1341,7 @@ pio=testsys.iobus.master[19] [testsys.tsunami.fake_ata1] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -1165,6 +1359,7 @@ pio=testsys.iobus.master[20] [testsys.tsunami.fake_pnp_addr] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -1182,6 +1377,7 @@ pio=testsys.iobus.master[9] [testsys.tsunami.fake_pnp_read0] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -1199,6 +1395,7 @@ pio=testsys.iobus.master[11] [testsys.tsunami.fake_pnp_read1] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -1216,6 +1413,7 @@ pio=testsys.iobus.master[12] [testsys.tsunami.fake_pnp_read2] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -1233,6 +1431,7 @@ pio=testsys.iobus.master[13] [testsys.tsunami.fake_pnp_read3] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -1250,6 +1449,7 @@ pio=testsys.iobus.master[14] [testsys.tsunami.fake_pnp_read4] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -1267,6 +1467,7 @@ pio=testsys.iobus.master[15] [testsys.tsunami.fake_pnp_read5] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -1284,6 +1485,7 @@ pio=testsys.iobus.master[16] [testsys.tsunami.fake_pnp_read6] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -1301,6 +1503,7 @@ pio=testsys.iobus.master[17] [testsys.tsunami.fake_pnp_read7] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -1318,6 +1521,7 @@ pio=testsys.iobus.master[18] [testsys.tsunami.fake_pnp_write] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -1335,6 +1539,7 @@ pio=testsys.iobus.master[10] [testsys.tsunami.fake_ppc] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -1352,6 +1557,7 @@ pio=testsys.iobus.master[7] [testsys.tsunami.fake_sm_chip] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -1369,6 +1575,7 @@ pio=testsys.iobus.master[2] [testsys.tsunami.fake_uart1] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -1386,6 +1593,7 @@ pio=testsys.iobus.master[3] [testsys.tsunami.fake_uart2] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -1403,6 +1611,7 @@ pio=testsys.iobus.master[4] [testsys.tsunami.fake_uart3] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -1420,6 +1629,7 @@ pio=testsys.iobus.master[5] [testsys.tsunami.fake_uart4] type=IsaFake clk_domain=testsys.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -1438,6 +1648,7 @@ pio=testsys.iobus.master[6] type=BadDevice clk_domain=testsys.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=testsys @@ -1465,6 +1676,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -1474,8 +1686,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1487,6 +1731,7 @@ clk_domain=testsys.clk_domain config_latency=20000 ctrl_offset=0 disks=testsys.disk0 testsys.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -1501,6 +1746,7 @@ pio=testsys.iobus.master[25] [testsys.tsunami.io] type=TsunamiIO clk_domain=testsys.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -1513,6 +1759,7 @@ pio=testsys.iobus.master[22] [testsys.tsunami.pchip] type=TsunamiPChip clk_domain=testsys.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=testsys @@ -1523,6 +1770,7 @@ pio=testsys.iobus.master[1] type=PciConfigAll bus=0 clk_domain=testsys.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=testsys.tsunami @@ -1533,6 +1781,7 @@ pio=testsys.iobus.default [testsys.tsunami.uart] type=Uart8250 clk_domain=testsys.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=testsys.tsunami @@ -1542,5 +1791,6 @@ pio=testsys.iobus.master[23] [testsys.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr index 22a941a4b..c0d08bdf9 100755 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr @@ -1,8 +1,5 @@ warn: Sockets disabled, not accepting terminal connections -warn: CoherentBus testsys.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections -warn: CoherentBus drivesys.membus has no snooping ports attached! warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Obsolete M5 ivlb instruction encountered. -hack: be nice to actually delete the event here diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index af627b8fa..75ac3ebe6 100755 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -1,16 +1,14 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:52 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:25:12 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 4321621592000 because checkpoint diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 4ccc9d7bc..cf63db341 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.200409 # Nu sim_ticks 200409284500 # Number of ticks simulated final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 21337245 # Simulator instruction rate (inst/s) -host_op_rate 21337231 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8163912733 # Simulator tick rate (ticks/s) -host_mem_usage 473328 # Number of bytes of host memory used -host_seconds 24.55 # Real time elapsed on the host +host_inst_rate 22333008 # Simulator instruction rate (inst/s) +host_op_rate 22332995 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8544906534 # Simulator tick rate (ticks/s) +host_mem_usage 473604 # Number of bytes of host memory used +host_seconds 23.45 # Real time elapsed on the host sim_insts 523790075 # Number of instructions simulated sim_ops 523790075 # Number of ops (including micro ops) simulated +testsys.voltage_domain.voltage 1 # Voltage in Volts +testsys.clk_domain.clock 1000 # Clock period in ticks testsys.physmem.bytes_read::cpu.inst 81046720 # Number of bytes read from this memory testsys.physmem.bytes_read::cpu.data 27826276 # Number of bytes read from this memory testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory @@ -55,6 +57,7 @@ testsys.disk2.dma_read_txs 0 # Nu testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. +testsys.cpu.clk_domain.clock 500 # Clock period in ticks testsys.cpu.dtb.fetch_hits 0 # ITB hits testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv @@ -178,6 +181,7 @@ testsys.cpu.kern.mode_ticks::kernel 994603000 60.01% 60.01% # nu testsys.cpu.kern.mode_ticks::user 533068000 32.16% 92.17% # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::idle 129740500 7.83% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 438 # number of times the context was actually changed +testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted testsys.tsunami.ethernet.rxBytes 798 # Bytes Received testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted @@ -229,6 +233,8 @@ testsys.tsunami.ethernet.postedInterrupts 2385819 # n testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped testsys.iobus.throughput 290423421 # Throughput (bytes/s) testsys.iobus.data_through_bus 58203550 # Total data (bytes) +drivesys.voltage_domain.voltage 1 # Voltage in Volts +drivesys.clk_domain.clock 1000 # Clock period in ticks drivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory drivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory drivesys.physmem.bytes_read::tsunami.ethernet 57260526 # Number of bytes read from this memory @@ -273,6 +279,7 @@ drivesys.disk2.dma_read_txs 0 # Nu drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. +drivesys.cpu.clk_domain.clock 250 # Clock period in ticks drivesys.cpu.dtb.fetch_hits 0 # ITB hits drivesys.cpu.dtb.fetch_misses 0 # ITB misses drivesys.cpu.dtb.fetch_acv 0 # ITB acv @@ -386,6 +393,7 @@ drivesys.cpu.kern.mode_ticks::kernel 78134250 2.63% 2.63% # nu drivesys.cpu.kern.mode_ticks::user 319668250 10.78% 13.41% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::idle 2567942000 86.59% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed +drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted @@ -445,13 +453,15 @@ sim_seconds 0.000407 # Nu sim_ticks 407341500 # Number of ticks simulated final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10977168844 # Simulator instruction rate (inst/s) -host_op_rate 10973505866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8529941400 # Simulator tick rate (ticks/s) -host_mem_usage 473328 # Number of bytes of host memory used +host_inst_rate 11306223920 # Simulator instruction rate (inst/s) +host_op_rate 11302970418 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8786485437 # Simulator tick rate (ticks/s) +host_mem_usage 473604 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host sim_insts 523862353 # Number of instructions simulated sim_ops 523862353 # Number of ops (including micro ops) simulated +testsys.voltage_domain.voltage 1 # Voltage in Volts +testsys.clk_domain.clock 1000 # Clock period in ticks testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory testsys.physmem.bytes_read::cpu.data 49936 # Number of bytes read from this memory testsys.physmem.bytes_read::tsunami.ethernet 116376 # Number of bytes read from this memory @@ -493,6 +503,7 @@ testsys.disk2.dma_read_txs 0 # Nu testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. +testsys.cpu.clk_domain.clock 500 # Clock period in ticks testsys.cpu.dtb.fetch_hits 0 # ITB hits testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv @@ -588,6 +599,7 @@ testsys.cpu.kern.mode_ticks::kernel 0 # nu testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode testsys.cpu.kern.swap_context 0 # number of times the context was actually changed +testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA testsys.tsunami.ethernet.descDmaReadBytes 116376 # number of descriptor bytes read w/ DMA @@ -621,6 +633,8 @@ testsys.tsunami.ethernet.postedInterrupts 4849 # n testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped testsys.iobus.throughput 290429529 # Throughput (bytes/s) testsys.iobus.data_through_bus 118304 # Total data (bytes) +drivesys.voltage_domain.voltage 1 # Voltage in Volts +drivesys.clk_domain.clock 1000 # Clock period in ticks drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory drivesys.physmem.bytes_read::tsunami.ethernet 116400 # Number of bytes read from this memory @@ -662,6 +676,7 @@ drivesys.disk2.dma_read_txs 0 # Nu drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. +drivesys.cpu.clk_domain.clock 250 # Clock period in ticks drivesys.cpu.dtb.fetch_hits 0 # ITB hits drivesys.cpu.dtb.fetch_misses 0 # ITB misses drivesys.cpu.dtb.fetch_acv 0 # ITB acv @@ -757,6 +772,7 @@ drivesys.cpu.kern.mode_ticks::kernel 0 # nu drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed +drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA drivesys.tsunami.ethernet.descDmaReadBytes 116400 # number of descriptor bytes read w/ DMA |