diff options
Diffstat (limited to 'tests/quick/fs')
12 files changed, 6499 insertions, 4909 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index dd98a6573..e45dffe9c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.870325 # Nu sim_ticks 1870325497500 # Number of ticks simulated final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3609656 # Simulator instruction rate (inst/s) -host_op_rate 3609654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 106905838632 # Simulator tick rate (ticks/s) -host_mem_usage 305660 # Number of bytes of host memory used -host_seconds 17.50 # Real time elapsed on the host +host_inst_rate 3096593 # Simulator instruction rate (inst/s) +host_op_rate 3096591 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91710635166 # Simulator tick rate (ticks/s) +host_mem_usage 308248 # Number of bytes of host memory used +host_seconds 20.39 # Real time elapsed on the host sim_insts 63151114 # Number of instructions simulated sim_ops 63151114 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory @@ -170,6 +170,9 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -191,6 +194,9 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests +system.membus.throughput 42148404 # Throughput (bytes/s) +system.membus.data_through_bus 78831234 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.l2c.replacements 1000406 # number of replacements system.l2c.tagsinuse 65381.817483 # Cycle average of tags in use system.l2c.total_refs 2465980 # Total number of references to valid blocks. @@ -550,6 +556,11 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.throughput 131960056 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 246797826 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10432 # Total snoop data (bytes) +system.iobus.throughput 1460513 # Throughput (bytes/s) +system.iobus.data_through_bus 2731634 # Total data (bytes) system.cpu0.icache.replacements 883989 # number of replacements system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use system.cpu0.icache.total_refs 56307893 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 2e73db07d..5057d01db 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829331 # Nu sim_ticks 1829330593000 # Number of ticks simulated final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3233953 # Simulator instruction rate (inst/s) -host_op_rate 3233951 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98537371937 # Simulator tick rate (ticks/s) -host_mem_usage 303612 # Number of bytes of host memory used -host_seconds 18.56 # Real time elapsed on the host +host_inst_rate 1529223 # Simulator instruction rate (inst/s) +host_op_rate 1529222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46594888750 # Simulator tick rate (ticks/s) +host_mem_usage 306208 # Number of bytes of host memory used +host_seconds 39.26 # Real time elapsed on the host sim_insts 60037737 # Number of instructions simulated sim_ops 60037737 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory @@ -160,6 +160,9 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -181,6 +184,9 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests +system.membus.throughput 42552299 # Throughput (bytes/s) +system.membus.data_through_bus 77842222 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.replacements 41686 # number of replacements system.iocache.tagsinuse 1.225558 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -407,6 +413,8 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.iobus.throughput 1480182 # Throughput (bytes/s) +system.iobus.data_through_bus 2707742 # Total data (bytes) system.cpu.icache.replacements 919577 # number of replacements system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks. @@ -593,5 +601,8 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 132867618 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 243048686 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 02fd81ba8..a249cee6b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.955749 # Number of seconds simulated -sim_ticks 1955749107000 # Number of ticks simulated -final_tick 1955749107000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.959865 # Number of seconds simulated +sim_ticks 1959865139500 # Number of ticks simulated +final_tick 1959865139500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 473674 # Simulator instruction rate (inst/s) -host_op_rate 473674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15599111797 # Simulator tick rate (ticks/s) -host_mem_usage 350548 # Number of bytes of host memory used -host_seconds 125.38 # Real time elapsed on the host -sim_insts 59387196 # Number of instructions simulated -sim_ops 59387196 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 829760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24747584 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 34368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 397760 # Number of bytes read from this memory -system.physmem.bytes_read::total 28660288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 829760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 34368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7682240 # Number of bytes written to this memory -system.physmem.bytes_written::total 7682240 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386681 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 537 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6215 # Number of read requests responded to by this memory -system.physmem.num_reads::total 447817 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120035 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120035 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12653762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1355397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 17573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 203380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14654379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424267 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 17573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441840 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3928029 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3928029 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3928029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12653762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1355397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 17573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 203380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18582408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 447817 # Total number of read requests seen -system.physmem.writeReqs 120035 # Total number of write requests seen -system.physmem.cpureqs 571031 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28660288 # Total number of bytes read from memory -system.physmem.bytesWritten 7682240 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28660288 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7682240 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3170 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28057 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27780 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28035 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27895 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28089 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28029 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27787 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27735 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7483 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7551 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7343 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7442 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7393 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7470 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7849 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7658 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7804 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7502 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7272 # Track writes on a per bank basis +host_inst_rate 1047911 # Simulator instruction rate (inst/s) +host_op_rate 1047910 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33678986014 # Simulator tick rate (ticks/s) +host_mem_usage 308256 # Number of bytes of host memory used +host_seconds 58.19 # Real time elapsed on the host +sim_insts 60980539 # Number of instructions simulated +sim_ops 60980539 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 833408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24886848 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 338688 # Number of bytes read from this memory +system.physmem.bytes_read::total 28741440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7743232 # Number of bytes written to this memory +system.physmem.bytes_written::total 7743232 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13022 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388857 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5292 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449085 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120988 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120988 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12698245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1352583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 172812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14665009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441369 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3950900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3950900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3950900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12698245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1352583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 172812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18615909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449085 # Total number of read requests seen +system.physmem.writeReqs 120988 # Total number of write requests seen +system.physmem.cpureqs 577269 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28741440 # Total number of bytes read from memory +system.physmem.bytesWritten 7743232 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28741440 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7743232 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 62 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 7195 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27762 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27763 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28133 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28181 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28656 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28031 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7895 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7532 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7275 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7314 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7754 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7257 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7316 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7137 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7066 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7523 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7683 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8132 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8336 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7679 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 9 # Number of times wr buffer was full causing retry -system.physmem.totGap 1955741979500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry +system.physmem.totGap 1959858128500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 447817 # Categorize read packet sizes +system.physmem.readPktSize::6 449085 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 120035 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407051 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1540 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120988 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 408321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3003 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1429 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1415 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -138,224 +138,391 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.totQLat 4786344500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13401468250 # Sum of mem lat for all requests -system.physmem.totBusLat 2238740000 # Total cycles spent in databus access -system.physmem.totBankLat 6376383750 # Total cycles spent in bank access -system.physmem.avgQLat 10689.82 # Average queueing delay per request -system.physmem.avgBankLat 14241.01 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40092 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 909.867305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 223.303664 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2368.170282 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14180 35.37% 35.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6168 15.38% 50.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3902 9.73% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2490 6.21% 66.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1693 4.22% 70.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1359 3.39% 74.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1096 2.73% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 872 2.17% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 629 1.57% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 634 1.58% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 494 1.23% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 427 1.07% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 257 0.64% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 230 0.57% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 171 0.43% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 248 0.62% 86.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 146 0.36% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 121 0.30% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 95 0.24% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 102 0.25% 88.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 86 0.21% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 112 0.28% 88.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 1028 2.56% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 203 0.51% 91.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 118 0.29% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 93 0.23% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 68 0.17% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 46 0.11% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 38 0.09% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 17 0.04% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 32 0.08% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 9 0.02% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 5 0.01% 92.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 7 0.02% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 4 0.01% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.00% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.00% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 2 0.00% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.00% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 2 0.00% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 1 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 2 0.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 4 0.01% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 2 0.00% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 3 0.01% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 3 0.01% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 1 0.00% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 2 0.00% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 3 0.01% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.00% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 6 0.01% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2435 6.07% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 243 0.61% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 6 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 10 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17155 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40092 # Bytes accessed per row activation +system.physmem.totQLat 3740449750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12011516000 # Sum of mem lat for all requests +system.physmem.totBusLat 2245115000 # Total cycles spent in databus access +system.physmem.totBankLat 6025951250 # Total cycles spent in bank access +system.physmem.avgQLat 8330.20 # Average queueing delay per request +system.physmem.avgBankLat 13420.14 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29930.83 # Average memory access latency -system.physmem.avgRdBW 14.65 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.93 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 26750.34 # Average memory access latency +system.physmem.avgRdBW 14.67 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.67 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 6.57 # Average write queue length over time -system.physmem.readRowHits 419819 # Number of row buffer hits during reads -system.physmem.writeRowHits 92219 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.83 # Row buffer hit rate for writes -system.physmem.avgGap 3444105.12 # Average gap between requests -system.l2c.replacements 340805 # number of replacements -system.l2c.tagsinuse 65304.474621 # Cycle average of tags in use -system.l2c.total_refs 2495359 # Total number of references to valid blocks. -system.l2c.sampled_refs 405916 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.147476 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6939667751 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55622.298055 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4855.652105 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4698.077679 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 117.035866 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 11.410916 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.848729 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.074091 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.071687 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001786 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000174 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996467 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 903439 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 772649 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86404 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 33735 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1796227 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 821961 # number of Writeback hits -system.l2c.Writeback_hits::total 821961 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 223 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 42 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 172231 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 12736 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 184967 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 903439 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 944880 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 86404 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 46471 # number of demand (read+write) hits -system.l2c.demand_hits::total 1981194 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 903439 # number of overall hits -system.l2c.overall_hits::cpu0.data 944880 # number of overall hits -system.l2c.overall_hits::cpu1.inst 86404 # number of overall hits -system.l2c.overall_hits::cpu1.data 46471 # number of overall hits -system.l2c.overall_hits::total 1981194 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12965 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271584 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 548 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 188 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285285 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2447 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 485 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2932 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 28 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 101 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115482 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6045 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121527 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12965 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387066 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 548 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6233 # number of demand (read+write) misses -system.l2c.demand_misses::total 406812 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12965 # number of overall misses -system.l2c.overall_misses::cpu0.data 387066 # number of overall misses -system.l2c.overall_misses::cpu1.inst 548 # number of overall misses -system.l2c.overall_misses::cpu1.data 6233 # number of overall misses -system.l2c.overall_misses::total 406812 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 808064500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11672931500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 35081000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 14352500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 12530429500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1060000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 227000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1287000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 115000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 137500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5534141500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 342947000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5877088500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 808064500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 17207073000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 35081000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 357299500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 18407518000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 808064500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 17207073000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 35081000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 357299500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 18407518000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 916404 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1044233 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 86952 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 33923 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2081512 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 821961 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 821961 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2616 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3155 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 49 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 94 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 143 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 287713 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18781 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306494 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 916404 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1331946 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 86952 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 52704 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2388006 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 916404 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1331946 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 86952 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 52704 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2388006 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014148 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.260080 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.006302 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.005542 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.137057 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935398 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.899814 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.929319 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.571429 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776596 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.706294 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.401379 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.321868 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.396507 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014148 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290602 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.006302 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.118264 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.170356 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014148 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290602 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.006302 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.118264 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.170356 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 62326.610104 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 42980.924870 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64016.423358 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76343.085106 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 43922.496801 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 433.183490 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 468.041237 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 438.949523 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 803.571429 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1575.342466 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1361.386139 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 47922.113403 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 56732.340778 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 48360.352021 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 62326.610104 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 44455.139434 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 64016.423358 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 57323.840847 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 45248.217850 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 62326.610104 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 44455.139434 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 64016.423358 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 57323.840847 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 45248.217850 # average overall miss latency +system.physmem.avgWrQLen 10.21 # Average write queue length over time +system.physmem.readRowHits 433314 # Number of row buffer hits during reads +system.physmem.writeRowHits 96597 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.84 # Row buffer hit rate for writes +system.physmem.avgGap 3437907.30 # Average gap between requests +system.membus.throughput 18676649 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292796 # Transaction distribution +system.membus.trans_dist::ReadResp 292796 # Transaction distribution +system.membus.trans_dist::WriteReq 14151 # Transaction distribution +system.membus.trans_dist::WriteResp 14151 # Transaction distribution +system.membus.trans_dist::Writeback 120988 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16779 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11846 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7198 # Transaction distribution +system.membus.trans_dist::ReadExReq 164928 # Transaction distribution +system.membus.trans_dist::ReadExResp 164057 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 974452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 42700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1056418 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1099118 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82626 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31259138 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 82626 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 36484672 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36567298 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36567298 # Total data (bytes) +system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 43346000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1579141500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3832845053 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 376210250 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.l2c.replacements 342163 # number of replacements +system.l2c.tagsinuse 65224.613124 # Cycle average of tags in use +system.l2c.total_refs 2440483 # Total number of references to valid blocks. +system.l2c.sampled_refs 407350 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.991121 # Average number of references to valid blocks. +system.l2c.warmup_cycle 8355445750 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55361.728852 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4802.377103 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4855.919486 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 161.173506 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 43.414178 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.844753 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.073278 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.074095 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002459 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000662 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.995249 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 678870 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 661225 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 323259 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 109447 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1772801 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 790404 # number of Writeback hits +system.l2c.Writeback_hits::total 790404 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 565 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 747 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 127727 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 43997 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 171724 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 678870 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 788952 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 323259 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 153444 # number of demand (read+write) hits +system.l2c.demand_hits::total 1944525 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 678870 # number of overall hits +system.l2c.overall_hits::cpu0.data 788952 # number of overall hits +system.l2c.overall_hits::cpu1.inst 323259 # number of overall hits +system.l2c.overall_hits::cpu1.data 153444 # number of overall hits +system.l2c.overall_hits::total 1944525 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13022 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271666 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 241 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285434 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2971 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1796 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4767 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 957 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 952 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1909 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 117966 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5061 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 123027 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13022 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 389632 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 505 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 5302 # number of demand (read+write) misses +system.l2c.demand_misses::total 408461 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13022 # number of overall misses +system.l2c.overall_misses::cpu0.data 389632 # number of overall misses +system.l2c.overall_misses::cpu1.inst 505 # number of overall misses +system.l2c.overall_misses::cpu1.data 5302 # number of overall misses +system.l2c.overall_misses::total 408461 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1040882000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 16855181499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 39850000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 21000500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 17956913999 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1322500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 10129500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11452000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 954000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 204000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1158000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7822362000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 373828000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8196190000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1040882000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 24677543499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 39850000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 394828500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 26153103999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1040882000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 24677543499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 39850000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 394828500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 26153103999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 691892 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 932891 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 323764 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 109688 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2058235 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 790404 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 790404 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3153 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2361 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5514 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 995 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 975 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1970 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 245693 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 49058 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 294751 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 691892 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1178584 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 323764 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 158746 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2352986 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 691892 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1178584 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 323764 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 158746 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2352986 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018821 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.291209 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.001560 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.002197 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.138679 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942277 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760695 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.864527 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961809 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976410 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969036 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.480136 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.103164 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.417393 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018821 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.330593 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001560 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.033399 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173593 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018821 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.330593 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001560 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.033399 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173593 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79932.575641 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 62043.765134 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78910.891089 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 87139.004149 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 62910.914604 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 445.136318 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5640.033408 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2402.349486 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 996.865204 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 214.285714 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 606.600314 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66310.309750 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73864.453665 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 66621.066920 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 79932.575641 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 63335.515304 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 78910.891089 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 74467.842324 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 64028.399282 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 79932.575641 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 63335.515304 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 78910.891089 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 74467.842324 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 64028.399282 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,119 +531,119 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 78515 # number of writebacks -system.l2c.writebacks::total 78515 # number of writebacks +system.l2c.writebacks::writebacks 79468 # number of writebacks +system.l2c.writebacks::total 79468 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 12965 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271584 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 537 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 188 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285274 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2447 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 485 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2932 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 28 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 101 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 115482 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6045 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121527 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12965 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387066 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 537 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6233 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 406801 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12965 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387066 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 537 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6233 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 406801 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 644929955 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8338657576 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 27777281 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12004183 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 9023368995 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24640443 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4857984 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29498427 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 280028 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 730073 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 1010101 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4108313953 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 267375786 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4375689739 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 644929955 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 12446971529 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 27777281 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 279379969 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 13399058734 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 644929955 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 12446971529 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 27777281 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 279379969 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 13399058734 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372993500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18178500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1391172000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1972884000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 501380500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2474264500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3345877500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 519559000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3865436500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014148 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.260080 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006176 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.005542 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.137051 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.935398 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.899814 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.929319 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.571429 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776596 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706294 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.401379 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.321868 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.396507 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014148 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290602 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006176 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.118264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.170352 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014148 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290602 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006176 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.118264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.170352 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30703.788058 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63852.037234 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 31630.534136 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10069.653862 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10016.461856 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10060.855048 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13022 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271666 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 494 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 241 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285423 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2971 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1796 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4767 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 957 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 952 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1909 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 117966 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5061 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 123027 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13022 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 389632 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 494 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 5302 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 408450 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13022 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 389632 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 494 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 5302 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 408450 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 877008002 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13524537499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 32847250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 18012000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 14452404751 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29895468 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17998795 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47894263 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9591457 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9520952 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 19112409 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6366934262 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 311018260 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6677952522 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 877008002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 19891471761 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 32847250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 329030260 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 21130357273 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 877008002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 19891471761 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 32847250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 329030260 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 21130357273 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373163000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17611000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1390774000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2158791500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 683644500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2842436000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3531954500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701255500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4233210000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.291209 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002197 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138674 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942277 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760695 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.864527 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961809 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976410 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969036 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480136 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.103164 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.417393 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.330593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.033399 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173588 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.330593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.033399 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173588 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49783.695785 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74738.589212 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 50635.039051 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10062.426119 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.600780 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10047.044892 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.421108 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35575.361987 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44230.899256 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 36005.906004 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32157.232950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44822.712819 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 32937.624868 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32157.232950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44822.712819 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 32937.624868 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.738607 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53972.621450 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61453.914246 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 54280.381721 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51051.945839 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62057.763108 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 51733.032863 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51051.945839 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62057.763108 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 51733.032863 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -488,14 +655,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.572926 # Cycle average of tags in use +system.iocache.tagsinuse 0.570240 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1747683301000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.572926 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035808 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035808 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1753558786000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.570240 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035640 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035640 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -504,14 +671,14 @@ system.iocache.demand_misses::tsunami.ide 41726 # n system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10655791911 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10655791911 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10676834909 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10676834909 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10676834909 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10676834909 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21457883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21457883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10416109037 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10416109037 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10437566920 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10437566920 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10437566920 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10437566920 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -528,19 +695,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256444.741793 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256444.741793 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255879.665173 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255879.665173 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255879.665173 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255879.665173 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285803 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123321.166667 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123321.166667 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 250676.478557 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 250676.478557 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 250145.399032 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 250145.399032 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 250145.399032 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 250145.399032 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 272227 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27265 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27211 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.482413 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.004300 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -554,14 +721,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41726 system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8493795674 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8493795674 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8505789923 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8505789923 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8505789923 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8505789923 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12409133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12409133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8254729537 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8254729537 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8267138670 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8267138670 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8267138670 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8267138670 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -570,14 +737,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204413.642520 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204413.642520 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203848.677635 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203848.677635 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203848.677635 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203848.677635 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71316.856322 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71316.856322 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 198660.221818 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 198660.221818 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198129.192110 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 198129.192110 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198129.192110 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 198129.192110 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -595,22 +762,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8641604 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 7504093 # DTB read hits +system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 6049321 # DTB write hits -system.cpu0.dtb.write_misses 813 # DTB write misses -system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 14690925 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses -system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3853653 # ITB hits -system.cpu0.itb.fetch_misses 3871 # ITB misses +system.cpu0.dtb.read_accesses 524069 # DTB read accesses +system.cpu0.dtb.write_hits 5095666 # DTB write hits +system.cpu0.dtb.write_misses 910 # DTB write misses +system.cpu0.dtb.write_acv 133 # DTB write access violations +system.cpu0.dtb.write_accesses 202595 # DTB write accesses +system.cpu0.dtb.data_hits 12599759 # DTB hits +system.cpu0.dtb.data_misses 8675 # DTB misses +system.cpu0.dtb.data_acv 343 # DTB access violations +system.cpu0.dtb.data_accesses 726664 # DTB accesses +system.cpu0.itb.fetch_hits 3641096 # ITB hits +system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3857524 # ITB accesses +system.cpu0.itb.fetch_accesses 3645080 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -623,117 +790,117 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3910164768 # number of cpu cycles simulated +system.cpu0.numCycles 3919730279 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54125350 # Number of instructions committed -system.cpu0.committedOps 54125350 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50093853 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 294168 # Number of float alu accesses -system.cpu0.num_func_calls 1428171 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6241814 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50093853 # number of integer instructions -system.cpu0.num_fp_insts 294168 # number of float instructions -system.cpu0.num_int_register_reads 68603455 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37120934 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 143452 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 146554 # number of times the floating registers were written -system.cpu0.num_mem_refs 14736943 # number of memory refs -system.cpu0.num_load_insts 8672910 # Number of load instructions -system.cpu0.num_store_insts 6064033 # Number of store instructions -system.cpu0.num_idle_cycles 3679227117.452844 # Number of idle cycles -system.cpu0.num_busy_cycles 230937650.547156 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059061 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940939 # Percentage of idle cycles +system.cpu0.committedInsts 47851975 # Number of instructions committed +system.cpu0.committedOps 47851975 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44398232 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 209056 # Number of float alu accesses +system.cpu0.num_func_calls 1198231 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5625657 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44398232 # number of integer instructions +system.cpu0.num_fp_insts 209056 # number of float instructions +system.cpu0.num_int_register_reads 61087554 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33073995 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102127 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 103890 # number of times the floating registers were written +system.cpu0.num_mem_refs 12640550 # number of memory refs +system.cpu0.num_load_insts 7531710 # Number of load instructions +system.cpu0.num_store_insts 5108840 # Number of store instructions +system.cpu0.num_idle_cycles 3699529015.998113 # Number of idle cycles +system.cpu0.num_busy_cycles 220201263.001888 # Number of busy cycles +system.cpu0.not_idle_fraction 0.056178 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.943822 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 203014 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72751 40.62% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1976 1.10% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 7 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104234 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 179099 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71384 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1976 1.36% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 7 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71377 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144875 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898825619000 97.12% 97.12% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94636000 0.00% 97.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 768885000 0.04% 97.17% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5899500 0.00% 97.17% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 55387314500 2.83% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1955082354000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981210 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6830 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164217 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56358 40.22% 40.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1973 1.41% 41.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 445 0.32% 42.04% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81223 57.96% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 140130 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55870 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1973 1.73% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 445 0.39% 51.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55425 48.69% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113844 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1901694919500 97.03% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94927000 0.00% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 766727000 0.04% 97.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 329552000 0.02% 97.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56978256500 2.91% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1959864382000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991341 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684777 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808910 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 222 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.682381 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812417 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 89 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3897 2.07% 2.12% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed -system.cpu0.kern.callpal::swpipl 172231 91.49% 93.64% # number of callpals executed -system.cpu0.kern.callpal::rdps 6679 3.55% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4753 2.52% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 188243 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7307 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1284 # number of protection mode switches +system.cpu0.kern.callpal::wripir 528 0.36% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3061 2.06% 2.42% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed +system.cpu0.kern.callpal::swpipl 133182 89.70% 92.16% # number of callpals executed +system.cpu0.kern.callpal::rdps 6700 4.51% 96.67% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.67% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.67% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.68% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.68% # number of callpals executed +system.cpu0.kern.callpal::rti 4398 2.96% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 148480 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6996 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1284 -system.cpu0.kern.mode_good::user 1284 +system.cpu0.kern.mode_good::kernel 1372 +system.cpu0.kern.mode_good::user 1373 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175722 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.196112 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.298917 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1951356000500 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3486973000 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327996 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1956039363000 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3825014500 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3898 # number of times the context was actually changed +system.cpu0.kern.swap_context 3062 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -765,51 +932,180 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 915791 # number of replacements -system.cpu0.icache.tagsinuse 509.170825 # Cycle average of tags in use -system.cpu0.icache.total_refs 53217526 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 916303 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.078524 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 32591402000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.170825 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53217526 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53217526 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53217526 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53217526 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53217526 # number of overall hits -system.cpu0.icache.overall_hits::total 53217526 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 916424 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916424 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 916424 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916424 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 916424 # number of overall misses -system.cpu0.icache.overall_misses::total 916424 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12661489500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12661489500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12661489500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12661489500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12661489500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12661489500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54133950 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54133950 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54133950 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54133950 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54133950 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54133950 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016929 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016929 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016929 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016929 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016929 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016929 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13816.191523 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13816.191523 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13816.191523 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13816.191523 # average overall miss latency +system.toL2Bus.throughput 103923821 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2101274 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2101259 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14151 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14151 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 790404 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17004 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11907 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28911 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 338243 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296693 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1383805 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3109039 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 647529 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 472865 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5613238 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 44281088 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118941040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 20720896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 17326866 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 201269890 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 201259586 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2417088 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4784493652 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3113609997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 5406966495 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1456953977 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 808879499 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 1400220 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55703 # Transaction distribution +system.iobus.trans_dist::WriteResp 55703 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126152 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 82626 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 56360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2744242 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2744242 # Total data (bytes) +system.iobus.reqLayer0.occupancy 13445000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 378246920 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 28549000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.icache.replacements 691283 # number of replacements +system.cpu0.icache.tagsinuse 508.523038 # Cycle average of tags in use +system.cpu0.icache.total_refs 47169081 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 691795 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.183611 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 38900732000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.523038 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993209 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993209 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47169081 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47169081 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47169081 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47169081 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47169081 # number of overall hits +system.cpu0.icache.overall_hits::total 47169081 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 691913 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 691913 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 691913 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 691913 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 691913 # number of overall misses +system.cpu0.icache.overall_misses::total 691913 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9946018500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9946018500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9946018500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9946018500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9946018500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9946018500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47860994 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47860994 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47860994 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47860994 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47860994 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47860994 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014457 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014457 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014457 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014457 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014457 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014457 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14374.666324 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14374.666324 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14374.666324 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14374.666324 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -818,112 +1114,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 916424 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 916424 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 916424 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 916424 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 916424 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 916424 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10828641500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10828641500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10828641500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10828641500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10828641500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10828641500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016929 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016929 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016929 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11816.191523 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11816.191523 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11816.191523 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 691913 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 691913 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 691913 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 691913 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 691913 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 691913 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8562191003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8562191003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8562191003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8562191003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8562191003 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8562191003 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014457 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014457 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014457 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12374.664160 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1338546 # number of replacements -system.cpu0.dcache.tagsinuse 506.515538 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13360558 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338960 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.978310 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 94365000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.515538 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989288 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989288 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7428425 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7428425 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5564911 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5564911 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176719 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 176719 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191683 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191683 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12993336 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12993336 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12993336 # number of overall hits -system.cpu0.dcache.overall_hits::total 12993336 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1036642 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1036642 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 291308 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 291308 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16366 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16366 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 435 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 435 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1327950 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1327950 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1327950 # number of overall misses -system.cpu0.dcache.overall_misses::total 1327950 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22380575500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 22380575500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8193151000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8193151000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 214111000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 214111000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2551500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2551500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 30573726500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 30573726500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 30573726500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 30573726500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8465067 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8465067 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5856219 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5856219 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193085 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 193085 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192118 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192118 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14321286 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14321286 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14321286 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14321286 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122461 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122461 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049743 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049743 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084761 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084761 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002264 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002264 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092726 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092726 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092726 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092726 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21589.493287 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21589.493287 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28125.389622 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 28125.389622 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13082.671392 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13082.671392 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5865.517241 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5865.517241 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23023.251252 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 23023.251252 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23023.251252 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23023.251252 # average overall miss latency +system.cpu0.dcache.replacements 1181525 # number of replacements +system.cpu0.dcache.tagsinuse 505.231432 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11411955 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1182037 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.654482 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 105721000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.231432 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.986780 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.986780 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6427043 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6427043 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4684362 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4684362 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139576 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139576 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146814 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 146814 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11111405 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11111405 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11111405 # number of overall hits +system.cpu0.dcache.overall_hits::total 11111405 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 936498 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 936498 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 255602 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 255602 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13508 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5738 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5738 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1192100 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1192100 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1192100 # number of overall misses +system.cpu0.dcache.overall_misses::total 1192100 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26205591500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 26205591500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9945079500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9945079500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 146904500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 146904500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44028500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44028500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 36150671000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 36150671000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 36150671000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 36150671000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7363541 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7363541 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4939964 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4939964 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153084 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 153084 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152552 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 152552 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12303505 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12303505 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12303505 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12303505 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127180 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127180 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051742 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051742 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088239 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088239 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037613 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037613 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096891 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096891 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096891 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096891 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27982.538671 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27982.538671 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38908.457289 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38908.457289 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10875.370151 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10875.370151 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7673.143953 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7673.143953 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 30325.200067 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 30325.200067 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -932,62 +1228,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 791336 # number of writebacks -system.cpu0.dcache.writebacks::total 791336 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036642 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1036642 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291308 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 291308 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16366 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16366 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 435 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 435 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327950 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1327950 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1327950 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1327950 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20307291500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20307291500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7610535000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7610535000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181379000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181379000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1681500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1681500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27917826500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 27917826500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27917826500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 27917826500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465371000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465371000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092831000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092831000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3558202000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3558202000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122461 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122461 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049743 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049743 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084761 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084761 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002264 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002264 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092726 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092726 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092726 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092726 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19589.493287 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19589.493287 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26125.389622 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26125.389622 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11082.671392 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11082.671392 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3865.517241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3865.517241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21023.251252 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21023.251252 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 678820 # number of writebacks +system.cpu0.dcache.writebacks::total 678820 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 936498 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 936498 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255602 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 255602 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13508 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13508 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5737 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5737 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1192100 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1192100 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1192100 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1192100 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24332593005 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24332593005 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9433875500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9433875500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 119888500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 119888500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32554500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32554500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 33766468505 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 33766468505 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 33766468505 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 33766468505 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465600500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465600500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2289389000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2289389000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3754989500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3754989500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127180 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127180 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051742 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051742 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088239 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088239 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037607 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037607 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096891 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096891 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096891 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096891 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25982.536006 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25982.536006 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36908.457289 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36908.457289 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8875.370151 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8875.370151 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5674.481436 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5674.481436 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -999,22 +1295,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1047303 # DTB read hits -system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_hits 2417907 # DTB read hits +system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 650380 # DTB write hits -system.cpu1.dtb.write_misses 341 # DTB write misses -system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 1697683 # DTB hits -system.cpu1.dtb.data_misses 3333 # DTB misses -system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1487846 # ITB hits -system.cpu1.itb.fetch_misses 1216 # ITB misses +system.cpu1.dtb.read_accesses 205337 # DTB read accesses +system.cpu1.dtb.write_hits 1735068 # DTB write hits +system.cpu1.dtb.write_misses 235 # DTB write misses +system.cpu1.dtb.write_acv 24 # DTB write access violations +system.cpu1.dtb.write_accesses 89739 # DTB write accesses +system.cpu1.dtb.data_hits 4152975 # DTB hits +system.cpu1.dtb.data_misses 2855 # DTB misses +system.cpu1.dtb.data_acv 24 # DTB access violations +system.cpu1.dtb.data_accesses 295076 # DTB accesses +system.cpu1.itb.fetch_hits 1826925 # ITB hits +system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1489062 # ITB accesses +system.cpu1.itb.fetch_accesses 1827989 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1027,141 +1323,141 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3911498214 # number of cpu cycles simulated +system.cpu1.numCycles 3917974909 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5261846 # Number of instructions committed -system.cpu1.committedOps 5261846 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4930311 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses -system.cpu1.num_func_calls 156775 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 508835 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4930311 # number of integer instructions -system.cpu1.num_fp_insts 34031 # number of float instructions -system.cpu1.num_int_register_reads 6861337 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3717514 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written -system.cpu1.num_mem_refs 1707139 # number of memory refs -system.cpu1.num_load_insts 1053310 # Number of load instructions -system.cpu1.num_store_insts 653829 # Number of store instructions -system.cpu1.num_idle_cycles 3891938527.998010 # Number of idle cycles -system.cpu1.num_busy_cycles 19559686.001990 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005001 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994999 # Percentage of idle cycles +system.cpu1.committedInsts 13128564 # Number of instructions committed +system.cpu1.committedOps 13128564 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12090481 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 177902 # Number of float alu accesses +system.cpu1.num_func_calls 416956 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1297332 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12090481 # number of integer instructions +system.cpu1.num_fp_insts 177902 # number of float instructions +system.cpu1.num_int_register_reads 16603924 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8888139 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 92328 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 94344 # number of times the floating registers were written +system.cpu1.num_mem_refs 4176284 # number of memory refs +system.cpu1.num_load_insts 2431879 # Number of load instructions +system.cpu1.num_store_insts 1744405 # Number of store instructions +system.cpu1.num_idle_cycles 3867819461.141509 # Number of idle cycles +system.cpu1.num_busy_cycles 50155447.858491 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012801 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987199 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2300 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 35556 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 8967 31.73% 31.73% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 6.97% 38.70% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 89 0.31% 39.02% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17234 60.98% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28260 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 8957 45.05% 45.05% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 9.91% 54.95% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 89 0.45% 55.40% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 8868 44.60% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 19884 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1918859770000 98.11% 98.11% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 708002500 0.04% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 60314000 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 36120248500 1.85% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1955748335000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998885 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 79425 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27091 38.34% 38.34% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.79% 41.13% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 528 0.75% 41.87% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41074 58.13% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 70662 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26202 48.19% 48.19% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.62% 51.81% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 528 0.97% 52.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25675 47.22% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 54374 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1908747944000 97.44% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700841000 0.04% 97.47% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 369371500 0.02% 97.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 49169268000 2.51% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1958987424500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967185 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.514564 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.703609 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 104 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.625091 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.769494 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 7 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed -system.cpu1.kern.callpal::swpipl 23668 81.85% 83.08% # number of callpals executed -system.cpu1.kern.callpal::rdps 2171 7.51% 90.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed -system.cpu1.kern.callpal::rti 2532 8.76% 99.37% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 445 0.61% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2045 2.80% 3.42% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.42% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.43% # number of callpals executed +system.cpu1.kern.callpal::swpipl 64414 88.26% 91.69% # number of callpals executed +system.cpu1.kern.callpal::rdps 2145 2.94% 94.63% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.63% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.63% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.64% # number of callpals executed +system.cpu1.kern.callpal::rti 3751 5.14% 99.78% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 28917 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 802 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2068 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 477 -system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 13 -system.cpu1.kern.mode_switch_good::kernel 0.594763 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 72984 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1994 # number of protection mode switches +system.cpu1.kern.mode_switch::user 369 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 821 +system.cpu1.kern.mode_good::user 369 +system.cpu1.kern.mode_good::idle 452 +system.cpu1.kern.mode_switch_good::kernel 0.411735 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.006286 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.286143 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3597793000 0.18% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1722339500 0.09% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1950428198000 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 338 # number of times the context was actually changed -system.cpu1.icache.replacements 86405 # number of replacements -system.cpu1.icache.tagsinuse 422.462851 # Cycle average of tags in use -system.cpu1.icache.total_refs 5178256 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 86917 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.577022 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1939963886500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 422.462851 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.825123 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.825123 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5178256 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5178256 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5178256 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5178256 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5178256 # number of overall hits -system.cpu1.icache.overall_hits::total 5178256 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 86953 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 86953 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 86953 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 86953 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 86953 # number of overall misses -system.cpu1.icache.overall_misses::total 86953 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1177160000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1177160000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1177160000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1177160000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1177160000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1177160000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5265209 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5265209 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5265209 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5265209 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5265209 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5265209 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016515 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016515 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016515 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016515 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016515 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016515 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13537.888284 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13537.888284 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13537.888284 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13537.888284 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13537.888284 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13537.888284 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.154636 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.310632 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 18283551000 0.93% 0.93% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1485621000 0.08% 1.01% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1938326244500 98.99% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2046 # number of times the context was actually changed +system.cpu1.icache.replacements 323214 # number of replacements +system.cpu1.icache.tagsinuse 446.824291 # Cycle average of tags in use +system.cpu1.icache.total_refs 12807678 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 323725 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 39.563450 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1958057375000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 446.824291 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.872704 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.872704 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12807678 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12807678 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12807678 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12807678 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12807678 # number of overall hits +system.cpu1.icache.overall_hits::total 12807678 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 323765 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 323765 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 323765 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 323765 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 323765 # number of overall misses +system.cpu1.icache.overall_misses::total 323765 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4261948000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4261948000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4261948000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4261948000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4261948000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4261948000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13131443 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13131443 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13131443 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13131443 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13131443 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13131443 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024656 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024656 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024656 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024656 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024656 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024656 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13163.708245 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13163.708245 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13163.708245 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13163.708245 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1170,112 +1466,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86953 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 86953 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 86953 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 86953 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 86953 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 86953 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1003254000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1003254000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1003254000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1003254000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1003254000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1003254000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016515 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016515 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016515 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11537.888284 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11537.888284 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11537.888284 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 323765 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 323765 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 323765 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 323765 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 323765 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 323765 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3614406523 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3614406523 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3614406523 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3614406523 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3614406523 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3614406523 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024656 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024656 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024656 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11163.672797 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11163.672797 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11163.672797 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 52787 # number of replacements -system.cpu1.dcache.tagsinuse 417.162104 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1641435 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 53299 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.796732 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1919955450000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 417.162104 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.814770 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.814770 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1001433 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1001433 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 616401 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 616401 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10836 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 10836 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1617834 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1617834 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1617834 # number of overall hits -system.cpu1.dcache.overall_hits::total 1617834 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 37022 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 37022 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 20409 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 20409 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 934 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 934 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 508 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 508 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 57431 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 57431 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 57431 # number of overall misses -system.cpu1.dcache.overall_misses::total 57431 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 462724500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 462724500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 544418500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 544418500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10274000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 10274000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3750500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3750500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1007143000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 1007143000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 1007143000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 1007143000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038455 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1038455 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 636810 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 636810 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 11770 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 11770 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11711 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 11711 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1675265 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1675265 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1675265 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1675265 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035651 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035651 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032049 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.032049 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.079354 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.079354 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.043378 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.043378 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034282 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034282 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034282 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034282 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12498.635946 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12498.635946 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26675.412808 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26675.412808 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11000 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11000 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7382.874016 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7382.874016 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17536.574324 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17536.574324 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17536.574324 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17536.574324 # average overall miss latency +system.cpu1.dcache.replacements 161925 # number of replacements +system.cpu1.dcache.tagsinuse 486.809606 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3976206 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 162254 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.506058 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70872567000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 486.809606 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.950800 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.950800 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2251927 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2251927 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1621193 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1621193 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49026 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 49026 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 51669 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 51669 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3873120 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3873120 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3873120 # number of overall hits +system.cpu1.dcache.overall_hits::total 3873120 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118911 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118911 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 58093 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 58093 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9306 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9306 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6171 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6171 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 177004 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 177004 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 177004 # number of overall misses +system.cpu1.dcache.overall_misses::total 177004 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440878500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1440878500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1041850000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1041850000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84410500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 84410500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44897500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 44897500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2482728500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2482728500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2482728500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2482728500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2370838 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2370838 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1679286 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1679286 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58332 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 58332 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 57840 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 57840 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4050124 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4050124 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4050124 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4050124 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050156 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050156 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034594 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034594 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159535 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159535 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106691 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106691 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043703 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043703 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043703 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043703 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12117.285196 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12117.285196 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17934.174513 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17934.174513 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9070.545884 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9070.545884 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7275.563118 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7275.563118 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14026.397709 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14026.397709 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14026.397709 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14026.397709 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1284,62 +1580,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 30625 # number of writebacks -system.cpu1.dcache.writebacks::total 30625 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37022 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 37022 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20409 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 20409 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 934 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 934 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 508 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 508 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 57431 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 57431 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 57431 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 57431 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 388680500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 388680500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 503600500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 503600500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8406000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8406000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2734500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2734500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 892281000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 892281000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 892281000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 892281000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 530266500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 530266500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 549654000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 549654000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035651 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035651 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032049 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032049 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.079354 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.079354 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043378 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043378 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034282 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034282 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10498.635946 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10498.635946 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24675.412808 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24675.412808 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9000 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9000 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5382.874016 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5382.874016 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 111584 # number of writebacks +system.cpu1.dcache.writebacks::total 111584 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118911 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118911 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58093 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 58093 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9306 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9306 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6171 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6171 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 177004 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 177004 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 177004 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 177004 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203056001 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203056001 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 925664000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 925664000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65798500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 65798500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32557500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32557500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2128720001 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2128720001 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2128720001 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2128720001 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18768000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 722866000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 722866000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 741634000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 741634000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050156 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050156 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034594 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034594 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159535 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159535 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106691 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106691 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043703 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043703 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10117.281000 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10117.281000 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15934.174513 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15934.174513 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7070.545884 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7070.545884 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5275.887214 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5275.887214 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 0c66e643a..e58c25cf4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.913475 # Number of seconds simulated -sim_ticks 1913474690000 # Number of ticks simulated -final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.918467 # Number of seconds simulated +sim_ticks 1918467182000 # Number of ticks simulated +final_tick 1918467182000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 985591 # Simulator instruction rate (inst/s) -host_op_rate 985591 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33597920761 # Simulator tick rate (ticks/s) -host_mem_usage 329492 # Number of bytes of host memory used -host_seconds 56.95 # Real time elapsed on the host -sim_insts 56131527 # Number of instructions simulated -sim_ops 56131527 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24859456 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory -system.physmem.bytes_read::total 28362112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404992 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404992 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388429 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443158 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115703 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115703 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 444511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12991787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1386010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14822308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 444511 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 444511 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3869919 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3869919 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3869919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 444511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12991787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1386010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443158 # Total number of read requests seen -system.physmem.writeReqs 115703 # Total number of write requests seen -system.physmem.cpureqs 559001 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28362112 # Total number of bytes read from memory -system.physmem.bytesWritten 7404992 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7404992 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q +host_inst_rate 829809 # Simulator instruction rate (inst/s) +host_op_rate 829809 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28329510825 # Simulator tick rate (ticks/s) +host_mem_usage 306208 # Number of bytes of host memory used +host_seconds 67.72 # Real time elapsed on the host +sim_insts 56194431 # Number of instructions simulated +sim_ops 56194431 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859200 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28362304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404544 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404544 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388425 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 443161 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115696 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115696 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12957845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1382537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14783836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443454 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443454 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3859615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3859615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3859615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12957845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1382537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18643451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443161 # Total number of read requests seen +system.physmem.writeReqs 115696 # Total number of write requests seen +system.physmem.cpureqs 558987 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28362304 # Total number of bytes read from memory +system.physmem.bytesWritten 7404544 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28362304 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7404544 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 54 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27906 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27828 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27614 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28005 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27558 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27591 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27731 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27560 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7488 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7040 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7173 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7315 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7581 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7063 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7148 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 27850 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28128 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28329 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28032 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 26738 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 26867 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27091 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27474 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28202 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28119 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28095 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7621 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7634 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7863 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7544 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7117 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6982 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6321 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6315 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7316 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6513 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6910 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7064 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7822 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7859 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7707 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 1913462790000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1918455311000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 443158 # Categorize read packet sizes +system.physmem.readPktSize::6 443161 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 115703 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 402453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115696 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 402425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -128,19 +128,19 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see @@ -151,45 +151,213 @@ system.physmem.wrQLenPdf::19 5030 # Wh system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.totQLat 4710239250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13222743000 # Sum of mem lat for all requests -system.physmem.totBusLat 2215485000 # Total cycles spent in databus access -system.physmem.totBankLat 6297018750 # Total cycles spent in bank access -system.physmem.avgQLat 10630.27 # Average queueing delay per request -system.physmem.avgBankLat 14211.38 # Average bank access latency per request +system.physmem.wrQLenPdf::23 1461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 37346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 957.575108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.677714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2441.521254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 13136 35.17% 35.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5703 15.27% 50.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3412 9.14% 59.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2227 5.96% 65.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1623 4.35% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1358 3.64% 73.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 966 2.59% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 781 2.09% 78.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 632 1.69% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 563 1.51% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 543 1.45% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 430 1.15% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 310 0.83% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 236 0.63% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 166 0.44% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 218 0.58% 86.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 124 0.33% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 90 0.24% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 81 0.22% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 99 0.27% 87.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 87 0.23% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 95 0.25% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 1075 2.88% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 150 0.40% 91.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 90 0.24% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 48 0.13% 91.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 42 0.11% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 35 0.09% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 29 0.08% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 22 0.06% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 18 0.05% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 29 0.08% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 17 0.05% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 5 0.01% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 12 0.03% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 7 0.02% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 8 0.02% 92.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 4 0.01% 92.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 6 0.02% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 3 0.01% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 5 0.01% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 4 0.01% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 4 0.01% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 6 0.02% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 4 0.01% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 5 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 3 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.00% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 2 0.01% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 3 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 3 0.01% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 3 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 2 0.01% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 2 0.01% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 2 0.01% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 2 0.01% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 2 0.01% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 2 0.01% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 4 0.01% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2437 6.53% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 2 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 15 0.04% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 239 0.64% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 8 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 2 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16899 2 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37346 # Bytes accessed per row activation +system.physmem.totQLat 3689041500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11833576500 # Sum of mem lat for all requests +system.physmem.totBusLat 2215535000 # Total cycles spent in databus access +system.physmem.totBankLat 5929000000 # Total cycles spent in bank access +system.physmem.avgQLat 8325.40 # Average queueing delay per request +system.physmem.avgBankLat 13380.52 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29841.64 # Average memory access latency -system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 26705.91 # Average memory access latency +system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.86 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.64 # Average write queue length over time -system.physmem.readRowHits 415747 # Number of row buffer hits during reads -system.physmem.writeRowHits 89943 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes -system.physmem.avgGap 3423861.73 # Average gap between requests +system.physmem.avgWrQLen 11.67 # Average write queue length over time +system.physmem.readRowHits 427971 # Number of row buffer hits during reads +system.physmem.writeRowHits 93480 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes +system.physmem.avgGap 3432819.69 # Average gap between requests +system.membus.throughput 18685123 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292355 # Transaction distribution +system.membus.trans_dist::ReadResp 292355 # Transaction distribution +system.membus.trans_dist::WriteReq 9649 # Transaction distribution +system.membus.trans_dist::WriteResp 9649 # Transaction distribution +system.membus.trans_dist::Writeback 115696 # Transaction distribution +system.membus.trans_dist::UpgradeReq 132 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 158289 # Transaction distribution +system.membus.trans_dist::ReadExResp 158289 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878153 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911311 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1002833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1035991 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457728 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30502284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 35766848 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 35811404 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35811404 # Total data (bytes) +system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 32374500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1489970000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3747469854 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 376209000 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.364719 # Cycle average of tags in use +system.iocache.tagsinuse 1.345466 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745699710000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.364719 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.085295 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.085295 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1752554384000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.345466 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084092 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -198,14 +366,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10653273426 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10653273426 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10674201424 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10674201424 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10674201424 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10674201424 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21342883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21342883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10435666030 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10435666030 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10457008913 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10457008913 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10457008913 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10457008913 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -222,19 +390,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256384.131353 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256384.131353 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255822.682421 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255822.682421 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255822.682421 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255822.682421 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285520 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123369.265896 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251147.141654 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 251147.141654 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 250617.349623 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 250617.349623 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 250617.349623 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 250617.349623 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 271244 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27149 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27003 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.516778 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.044958 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -248,14 +416,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8491263947 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8491263947 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8503195196 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8503195196 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8503195196 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8503195196 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8274278780 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8274278780 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8286624913 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8286624913 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8286624913 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8286624913 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -264,14 +432,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204352.713395 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204352.713395 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203791.376777 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203791.376777 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203791.376777 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203791.376777 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199130.698402 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199130.698402 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198600.956573 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 198600.956573 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198600.956573 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 198600.956573 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -289,22 +457,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9056964 # DTB read hits -system.cpu.dtb.read_misses 10329 # DTB read misses +system.cpu.dtb.read_hits 9066498 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352252 # DTB write hits +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6357377 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15409216 # DTB hits -system.cpu.dtb.data_misses 11471 # DTB misses +system.cpu.dtb.data_hits 15423875 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974658 # ITB hits -system.cpu.itb.fetch_misses 5006 # ITB misses +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4974559 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979664 # ITB accesses +system.cpu.itb.fetch_accesses 4979569 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,51 +485,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3826949380 # number of cpu cycles simulated +system.cpu.numCycles 3836934364 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56131527 # Number of instructions committed -system.cpu.committedOps 56131527 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52005592 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1482234 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6464100 # number of instructions that are conditional controls -system.cpu.num_int_insts 52005592 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71250465 # number of times the integer registers were read -system.cpu.num_int_register_writes 38480970 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15461819 # number of memory refs -system.cpu.num_load_insts 9093811 # Number of load instructions -system.cpu.num_store_insts 6368008 # Number of store instructions -system.cpu.num_idle_cycles 3593002703.998122 # Number of idle cycles -system.cpu.num_busy_cycles 233946676.001878 # Number of busy cycles -system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.938869 # Percentage of idle cycles +system.cpu.committedInsts 56194431 # Number of instructions committed +system.cpu.committedOps 56194431 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52065988 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses +system.cpu.num_func_calls 1483664 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469615 # number of instructions that are conditional controls +system.cpu.num_int_insts 52065988 # number of integer instructions +system.cpu.num_fp_insts 324527 # number of float instructions +system.cpu.num_int_register_reads 71339773 # number of times the integer registers were read +system.cpu.num_int_register_writes 38529890 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written +system.cpu.num_mem_refs 15476497 # number of memory refs +system.cpu.num_load_insts 9103354 # Number of load instructions +system.cpu.num_store_insts 6373143 # Number of store instructions +system.cpu.num_idle_cycles 3587701469.998130 # Number of idle cycles +system.cpu.num_busy_cycles 249232894.001870 # Number of busy cycles +system.cpu.not_idle_fraction 0.064956 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.935044 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212010 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212005 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74904 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1933 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106230 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183193 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106221 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183187 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73537 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858610730000 97.13% 97.13% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54034649000 2.82% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73537 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149136 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857459158500 96.82% 96.82% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91312500 0.00% 96.82% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 736664500 0.04% 96.86% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 60179312500 3.14% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1918466448000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692196 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814049 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692302 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814119 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -397,33 +565,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175970 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175968 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5158 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192916 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches -system.cpu.kern.mode_switch::user 1742 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.callpal::total 192914 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1742 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323898 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 171 +system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081584 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45394332000 2.37% 2.37% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5131699000 0.27% 2.64% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1862947923000 97.36% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.kern.mode_ticks::kernel 46102035000 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5243076000 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1867121335000 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4179 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -455,51 +623,145 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927958 # number of replacements -system.cpu.icache.tagsinuse 509.106403 # Cycle average of tags in use -system.cpu.icache.total_refs 55214738 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928469 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.468585 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 32313596000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.106403 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.994348 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.994348 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55214738 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55214738 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55214738 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55214738 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55214738 # number of overall hits -system.cpu.icache.overall_hits::total 55214738 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928628 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928628 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928628 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928628 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928628 # number of overall misses -system.cpu.icache.overall_misses::total 928628 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770432000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12770432000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12770432000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12770432000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12770432000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12770432000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56143366 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56143366 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56143366 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56143366 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56143366 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56143366 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016540 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.935113 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13751.935113 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13751.935113 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13751.935113 # average overall miss latency +system.iobus.throughput 1410587 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7103 # Transaction distribution +system.iobus.trans_dist::ReadResp 7103 # Transaction distribution +system.iobus.trans_dist::WriteReq 51201 # Transaction distribution +system.iobus.trans_dist::WriteResp 51201 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2706164 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 378256913 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42010000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 928573 # number of replacements +system.cpu.icache.tagsinuse 508.447268 # Cycle average of tags in use +system.cpu.icache.total_refs 55277021 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 929084 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.496258 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 38501717000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 508.447268 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993061 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993061 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55277021 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55277021 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55277021 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55277021 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55277021 # number of overall hits +system.cpu.icache.overall_hits::total 55277021 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929244 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929244 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929244 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929244 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929244 # number of overall misses +system.cpu.icache.overall_misses::total 929244 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12990910500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12990910500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12990910500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12990910500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12990910500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12990910500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56206265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56206265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56206265 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56206265 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56206265 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56206265 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016533 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016533 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016533 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016533 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016533 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016533 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13980.085424 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13980.085424 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13980.085424 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13980.085424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13980.085424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13980.085424 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -508,126 +770,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10913176000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10913176000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10913176000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10913176000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10913176000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10913176000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.935113 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.935113 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.935113 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.935113 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.935113 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11751.935113 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929244 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929244 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929244 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929244 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929244 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929244 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11132422500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11132422500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11132422500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11132422500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11132422500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11132422500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016533 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016533 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016533 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11980.085424 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11980.085424 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11980.085424 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11980.085424 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11980.085424 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11980.085424 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 336244 # number of replacements -system.cpu.l2cache.tagsinuse 65321.744334 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2445560 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401406 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.092485 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 5250002751 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 55750.890947 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4786.700562 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4784.152824 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.850691 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073039 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.073000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.996731 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 915318 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 813988 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1729306 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 834499 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834499 # number of Writeback hits +system.cpu.l2cache.replacements 336249 # number of replacements +system.cpu.l2cache.tagsinuse 65299.317705 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2448334 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 401410 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.099335 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 6517964750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 55625.043454 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4760.305477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4913.968774 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.848771 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.072636 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.074981 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.996389 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 915931 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 815128 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1731059 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 835526 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 835526 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187514 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187514 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 915318 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001502 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1916820 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 915318 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1001502 # number of overall hits -system.cpu.l2cache.overall_hits::total 1916820 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271963 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285253 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187585 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187585 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 915931 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002713 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918644 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 915931 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002713 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918644 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13293 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 271959 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 285252 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 116856 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 116856 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388819 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402109 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388819 # number of overall misses -system.cpu.l2cache.overall_misses::total 402109 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831348000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11699456000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12530804000 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses::cpu.inst 13293 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388815 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 402108 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13293 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388815 # number of overall misses +system.cpu.l2cache.overall_misses::total 402108 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1043848500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16878045500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17921894000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 189500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 189500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5596921000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5596921000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 831348000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17296377000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18127725000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 831348000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17296377000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18127725000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 928608 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1085951 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2014559 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 834499 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 834499 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7749920500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7749920500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1043848500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 24627966000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25671814500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1043848500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 24627966000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25671814500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 929224 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1087087 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2016311 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 835526 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 835526 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 928608 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390321 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2318929 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 928608 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390321 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2318929 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014312 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250438 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141596 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304441 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304441 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929224 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1391528 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320752 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929224 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1391528 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320752 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014305 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250172 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141472 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383927 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383927 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014312 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279661 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173403 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014312 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279661 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173403 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62554.401806 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43018.557671 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 43928.736946 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383838 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383838 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014305 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173266 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014305 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173266 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78526.179192 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62060.992650 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 62828.285165 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47895.880400 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47895.880400 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62554.401806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44484.392481 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 45081.619660 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62554.401806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44484.392481 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 45081.619660 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66320.261690 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66320.261690 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78526.179192 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63341.090236 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 63843.083202 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78526.179192 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63341.090236 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 63843.083202 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -636,66 +898,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74191 # number of writebacks -system.cpu.l2cache.writebacks::total 74191 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285253 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 74184 # number of writebacks +system.cpu.l2cache.writebacks::total 74184 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285252 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116856 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 116856 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388819 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402109 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388819 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402109 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666421030 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8360475460 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9026896490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388815 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402108 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13293 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388815 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402108 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 879542258 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13544515256 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14424057514 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4160156080 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4160156080 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666421030 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12520631540 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13187052570 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666421030 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12520631540 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13187052570 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895853000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895853000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229999000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229999000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250438 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6316543121 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6316543121 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 879542258 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19861058377 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20740600635 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 879542258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19861058377 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20740600635 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895431500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895431500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229576500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229576500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014305 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250172 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141472 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383927 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383927 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279661 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173403 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279661 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173403 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50144.547028 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30741.223843 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31645.228937 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383838 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383838 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014305 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173266 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014305 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173266 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66165.820958 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49803.519119 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50566.017115 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35600.705826 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35600.705826 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54054.076136 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54054.076136 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66165.820958 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51080.998359 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 51579.676691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66165.820958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51080.998359 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51579.676691 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -703,79 +965,79 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1389808 # number of replacements -system.cpu.dcache.tagsinuse 511.980871 # Cycle average of tags in use -system.cpu.dcache.total_refs 14037921 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1390320 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.096899 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.980871 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807387 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807387 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848285 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848285 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199228 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199228 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655672 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655672 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655672 # number of overall hits -system.cpu.dcache.overall_hits::total 13655672 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1068707 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1068707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304387 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304387 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373094 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373094 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373094 # number of overall misses -system.cpu.dcache.overall_misses::total 1373094 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22868320000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22868320000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385649000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8385649000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228869000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228869000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31253969000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31253969000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31253969000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31253969000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8876094 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8876094 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152672 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152672 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199228 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199228 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15028766 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15028766 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15028766 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15028766 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120403 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120403 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049472 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049472 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091364 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091364 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091364 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091364 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21398.119410 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21398.119410 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.300726 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.300726 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13272.384598 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13272.384598 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22761.711143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22761.711143 # average overall miss latency +system.cpu.dcache.replacements 1391015 # number of replacements +system.cpu.dcache.tagsinuse 511.979232 # Cycle average of tags in use +system.cpu.dcache.total_refs 14051400 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1391527 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.097828 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 105127000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.979232 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7815804 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815804 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853333 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853333 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182999 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182999 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199247 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199247 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13669137 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13669137 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13669137 # number of overall hits +system.cpu.dcache.overall_hits::total 13669137 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069817 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069817 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304458 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304458 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17270 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17270 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374275 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374275 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374275 # number of overall misses +system.cpu.dcache.overall_misses::total 1374275 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28060990500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28060990500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10539571500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10539571500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229596000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229596000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38600562000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38600562000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38600562000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38600562000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8885621 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8885621 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157791 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157791 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200269 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200269 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199247 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199247 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15043412 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15043412 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15043412 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15043412 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120399 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120399 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049443 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049443 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086234 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086234 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091354 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091354 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091354 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091354 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.710782 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.710782 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34617.489112 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34617.489112 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13294.499131 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13294.499131 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28087.946008 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28087.946008 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28087.946008 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28087.946008 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -784,54 +1046,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks -system.cpu.dcache.writebacks::total 834499 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068707 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1068707 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304387 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304387 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373094 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373094 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373094 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373094 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730906000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730906000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776875000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776875000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194381000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194381000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507781000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28507781000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507781000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28507781000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19398.119410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19398.119410 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.300726 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.300726 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835526 # number of writebacks +system.cpu.dcache.writebacks::total 835526 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069817 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069817 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304458 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304458 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17270 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17270 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374275 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374275 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374275 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374275 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25921356500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25921356500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9930655500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9930655500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195056000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195056000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35852012000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 35852012000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35852012000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 35852012000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435454500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435454500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120399 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120399 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086234 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086234 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091354 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091354 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091354 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091354 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24229.710782 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24229.710782 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32617.489112 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32617.489112 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11294.499131 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11294.499131 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26087.946008 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26087.946008 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26087.946008 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26087.946008 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -839,5 +1101,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 105322456 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2023434 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 345993 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304442 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858468 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651931 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 5510399 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59470336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142586060 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 202056396 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 202046348 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2426797500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1393866000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2099055000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 9a52baa4f..57671b2bd 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1025890 # Simulator instruction rate (inst/s) -host_op_rate 1320831 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15183699019 # Simulator tick rate (ticks/s) -host_mem_usage 392232 # Number of bytes of host memory used -host_seconds 60.07 # Real time elapsed on the host +host_inst_rate 749434 # Simulator instruction rate (inst/s) +host_op_rate 964895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11092016800 # Simulator tick rate (ticks/s) +host_mem_usage 399496 # Number of bytes of host memory used +host_seconds 82.23 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory @@ -188,6 +188,9 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -227,6 +230,9 @@ system.realview.nvmem.bw_inst_read::total 75 # I system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 64986577 # Throughput (bytes/s) +system.membus.data_through_bus 59274047 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.l2c.replacements 70658 # number of replacements system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use system.l2c.total_refs 1623339 # Total number of references to valid blocks. @@ -409,6 +415,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 154009014 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 140471123 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.iobus.throughput 45730949 # Throughput (bytes/s) +system.iobus.data_through_bus 41711051 # Total data (bytes) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 7975768 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 9271f187d..979b75345 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1712706 # Simulator instruction rate (inst/s) -host_op_rate 2202434 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66139785958 # Simulator tick rate (ticks/s) -host_mem_usage 391204 # Number of bytes of host memory used -host_seconds 35.27 # Real time elapsed on the host +host_inst_rate 692273 # Simulator instruction rate (inst/s) +host_op_rate 890221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26733610702 # Simulator tick rate (ticks/s) +host_mem_usage 396420 # Number of bytes of host memory used +host_seconds 87.26 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -171,6 +171,9 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -204,12 +207,17 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55969585 # Throughput (bytes/s) +system.membus.data_through_bus 130566422 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.iobus.throughput 48895252 # Throughput (bytes/s) +system.iobus.data_through_bus 114063346 # Total data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 14971214 # DTB read hits @@ -490,6 +498,9 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks system.cpu.dcache.writebacks::total 592643 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 99dfbb1fa..7372967ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,147 +1,147 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.183438 # Number of seconds simulated -sim_ticks 1183437503500 # Number of ticks simulated -final_tick 1183437503500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.194897 # Number of seconds simulated +sim_ticks 1194896580500 # Number of ticks simulated +final_tick 1194896580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 462248 # Simulator instruction rate (inst/s) -host_op_rate 589061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8900686287 # Simulator tick rate (ticks/s) -host_mem_usage 440324 # Number of bytes of host memory used -host_seconds 132.96 # Real time elapsed on the host -sim_insts 61460532 # Number of instructions simulated -sim_ops 78321652 # Number of ops (including micro ops) simulated +host_inst_rate 311660 # Simulator instruction rate (inst/s) +host_op_rate 397163 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6068013925 # Simulator tick rate (ticks/s) +host_mem_usage 403588 # Number of bytes of host memory used +host_seconds 196.92 # Real time elapsed on the host +sim_insts 61371297 # Number of instructions simulated +sim_ops 78208202 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4708980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4819184 # Number of bytes read from this memory -system.physmem.bytes_read::total 62150116 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4119552 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7146896 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 463972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6626100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 255836 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory +system.physmem.bytes_read::total 62155108 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 255836 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4136192 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 7163536 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12372 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73650 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75326 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654550 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64368 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821204 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43859107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 332783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3979069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 273072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4072191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52516602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 332783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 273072 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3481005 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14365 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2543729 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6039099 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3481005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43859107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 332783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3993434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 273072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6615920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58555700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654550 # Total number of read requests seen -system.physmem.writeReqs 821204 # Total number of write requests seen -system.physmem.cpureqs 235817 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425891200 # Total number of bytes read from memory -system.physmem.bytesWritten 52557056 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62150116 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7146896 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11788 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 422295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415259 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415167 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415977 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415766 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415044 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 414930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50890 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51482 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50751 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51227 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51302 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51806 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51075 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51789 # Track writes on a per bank basis +system.physmem.num_reads::cpu0.inst 13468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4079 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654628 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64628 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 821464 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43438497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 388295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5545333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2430537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52017144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 388295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602402 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3461548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2533528 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5995110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3461548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43438497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 388295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8078862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 214107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2430570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58012254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654628 # Total number of read requests seen +system.physmem.writeReqs 821464 # Total number of write requests seen +system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425896192 # Total number of bytes read from memory +system.physmem.bytesWritten 52573696 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62155108 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7163536 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 139 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 10646 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415731 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 416079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415727 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51082 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51694 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1183433014000 # Total gap between requests +system.physmem.totGap 1194892168500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159661 # Categorize read packet sizes +system.physmem.readPktSize::6 159739 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64368 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 571102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 408461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 415701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1537889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1165282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1169319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1141412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 48416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 68998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 48154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64628 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 581008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 419779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 439715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1589810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1189300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1185139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1157962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 15424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 15138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4046 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,59 +156,336 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 147040385750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 189361608250 # Sum of mem lat for all requests -system.physmem.totBusLat 33272265000 # Total cycles spent in databus access -system.physmem.totBankLat 9048957500 # Total cycles spent in bank access -system.physmem.avgQLat 22096.54 # Average queueing delay per request -system.physmem.avgBankLat 1359.83 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 34609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 13824.665723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 735.190153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 27804.066503 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 7914 22.87% 22.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 4043 11.68% 34.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2692 7.78% 42.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1927 5.57% 47.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1400 4.05% 51.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1123 3.24% 55.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 878 2.54% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 878 2.54% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 638 1.84% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 541 1.56% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 480 1.39% 65.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 476 1.38% 66.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 262 0.76% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 253 0.73% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 191 0.55% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 292 0.84% 69.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 145 0.42% 69.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 146 0.42% 70.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 123 0.36% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 107 0.31% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 79 0.23% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 170 0.49% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 246 0.71% 74.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 151 0.44% 75.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 129 0.37% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 98 0.28% 76.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 72 0.21% 76.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 51 0.15% 76.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 51 0.15% 76.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 71 0.21% 76.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 44 0.13% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 29 0.08% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 19 0.05% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 23 0.07% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 27 0.08% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 13 0.04% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 9 0.03% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 14 0.04% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 11 0.03% 77.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 12 0.03% 77.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 14 0.04% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 6 0.02% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 77.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 15 0.04% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 4 0.01% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 7 0.02% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 4 0.01% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 14 0.04% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 11 0.03% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 7 0.02% 77.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 7 0.02% 77.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 11 0.03% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 8 0.02% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 5 0.01% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 12 0.03% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 8 0.02% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 41 0.12% 78.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 3 0.01% 78.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 4 0.01% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 4 0.01% 78.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 5 0.01% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 4 0.01% 78.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 5 0.01% 78.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 9 0.03% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 1 0.00% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 5 0.01% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 3 0.01% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 10 0.03% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 3 0.01% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 2 0.01% 78.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 5 0.01% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 2 0.01% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 3 0.01% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 6 0.02% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5823 2 0.01% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 3 0.01% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 5 0.01% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 4 0.01% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 3 0.01% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 3 0.01% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 170 0.49% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 3 0.01% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 1 0.00% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 4 0.01% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 4 0.01% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 2 0.01% 79.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 5 0.01% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 3 0.01% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 21 0.06% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 3 0.01% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 3 0.01% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 2 0.01% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 3 0.01% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 4 0.01% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 4 0.01% 79.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 5 0.01% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 2 0.01% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 2 0.01% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 4 0.01% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 318 0.92% 80.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 1 0.00% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 2 0.01% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 4 0.01% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9535 2 0.01% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 2 0.01% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 17 0.05% 80.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10815 1 0.00% 80.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11071 2 0.01% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11263 1 0.00% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 2 0.01% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11583 2 0.01% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12799 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13631 2 0.01% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 2 0.01% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15935 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16767 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 1 0.00% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17343 1 0.00% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 2 0.01% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17791 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17919 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 2 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21055 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22591 3 0.01% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23103 2 0.01% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 3 0.01% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23871 1 0.00% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24127 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24191 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24383 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24895 2 0.01% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25279 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25919 2 0.01% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 1 0.00% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26943 3 0.01% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27199 1 0.00% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27903 1 0.00% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27967 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-28031 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 2 0.01% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28991 2 0.01% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29247 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 4 0.01% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 5 0.01% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31103 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31423 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31743 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32063 2 0.01% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32831 6 0.02% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 1 0.00% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33472-33535 5 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33599 49 0.14% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33663 2 0.01% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34879 1 0.00% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35135 1 0.00% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38079 1 0.00% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39487 1 0.00% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-41023 1 0.00% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 2 0.01% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42175 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43327 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46911 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48447 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48576-48639 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53311 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53504-53567 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53760-53823 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54016-54079 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54528-54591 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55744-55807 1 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55808-55871 2 0.01% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 3 0.01% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56576-56639 1 0.00% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58880-58943 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59520-59583 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60479 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60608-60671 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 1 0.00% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 7 0.02% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 6201 17.92% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65920-65983 1 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66304-66367 1 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74240-74303 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::76480-76543 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::76864-76927 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::84416-84479 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::86848-86911 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::87040-87103 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::87424-87487 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97024-97087 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97472-97535 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97600-97663 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109120-109183 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::110080-110143 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::111168-111231 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::114496-114559 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120896-120959 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121152-121215 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121728-121791 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::122112-122175 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131135 336 0.97% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 34609 # Bytes accessed per row activation +system.physmem.totQLat 134116991750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 175932036750 # Sum of mem lat for all requests +system.physmem.totBusLat 33272445000 # Total cycles spent in databus access +system.physmem.totBankLat 8542600000 # Total cycles spent in bank access +system.physmem.avgQLat 20154.36 # Average queueing delay per request +system.physmem.avgBankLat 1283.73 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28456.37 # Average memory access latency -system.physmem.avgRdBW 359.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.41 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.52 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 26438.10 # Average memory access latency +system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 11.75 # Average write queue length over time -system.physmem.readRowHits 6612404 # Number of row buffer hits during reads -system.physmem.writeRowHits 800418 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.47 # Row buffer hit rate for writes -system.physmem.avgGap 158302.83 # Average gap between requests +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 12.03 # Average write queue length over time +system.physmem.readRowHits 6636609 # Number of row buffer hits during reads +system.physmem.writeRowHits 804716 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes +system.physmem.avgGap 159828.45 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -219,245 +496,306 @@ system.realview.nvmem.num_reads::cpu0.inst 5 # system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69541 # number of replacements -system.l2c.tagsinuse 53035.489918 # Cycle average of tags in use -system.l2c.total_refs 1672596 # Total number of references to valid blocks. -system.l2c.sampled_refs 134740 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.413507 # Average number of references to valid blocks. +system.membus.throughput 60028731 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703147 # Transaction distribution +system.membus.trans_dist::ReadResp 7703147 # Transaction distribution +system.membus.trans_dist::WriteReq 767201 # Transaction distribution +system.membus.trans_dist::WriteResp 767201 # Transaction distribution +system.membus.trans_dist::Writeback 64628 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27727 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16403 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10646 # Transaction distribution +system.membus.trans_dist::ReadExReq 137752 # Transaction distribution +system.membus.trans_dist::ReadExResp 137298 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966658 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4359022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 14942786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17335150 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19823614 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 69318644 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 71728126 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71728126 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1224802500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 9206920000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) +system.membus.reqLayer3.occupancy 7965000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 5076821641 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.respLayer2.occupancy 14663419999 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.l2c.replacements 69621 # number of replacements +system.l2c.tagsinuse 53152.412760 # Cycle average of tags in use +system.l2c.total_refs 1651309 # Total number of references to valid blocks. +system.l2c.sampled_refs 134782 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.251703 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40180.165903 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001420 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3726.817906 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4242.402809 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.742182 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2823.857423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2059.501869 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613101 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40039.064508 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 2.667880 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.001518 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4643.192238 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 5788.281913 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 1923.389950 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 755.813095 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.610948 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056867 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064734 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.043089 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031426 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809257 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 3941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1769 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419774 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205645 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5809 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2015 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464124 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143605 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1246682 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571448 # number of Writeback hits -system.l2c.Writeback_hits::total 571448 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1206 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 615 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1821 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56897 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52477 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109374 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3941 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1769 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419774 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262542 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5809 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2015 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464124 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196082 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356056 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3941 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1769 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419774 # number of overall hits -system.l2c.overall_hits::cpu0.data 262542 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5809 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2015 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464124 # number of overall hits -system.l2c.overall_hits::cpu1.data 196082 # number of overall hits -system.l2c.overall_hits::total 1356056 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses +system.l2c.occ_percent::cpu0.inst 0.070849 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.088322 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.029349 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.011533 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.811041 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1439 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 483114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 241880 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1868 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 372301 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 110577 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1219485 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 576235 # number of Writeback hits +system.l2c.Writeback_hits::total 576235 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1306 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 431 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 99 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65556 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 45402 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 110958 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1439 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 483114 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 307436 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1868 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 372301 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 155979 # number of demand (read+write) hits +system.l2c.demand_hits::total 1330443 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1439 # number of overall hits +system.l2c.overall_hits::cpu0.inst 483114 # number of overall hits +system.l2c.overall_hits::cpu0.data 307436 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1868 # number of overall hits +system.l2c.overall_hits::cpu1.inst 372301 # number of overall hits +system.l2c.overall_hits::cpu1.data 155979 # number of overall hits +system.l2c.overall_hits::total 1330443 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5740 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7867 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3619 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22277 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4714 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3582 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8296 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 566 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1045 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67030 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72802 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139832 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 6836 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9717 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3992 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22442 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3986 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3365 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 7351 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 384 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 475 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 859 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 95133 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 44601 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139734 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5740 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74897 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76421 # number of demand (read+write) misses -system.l2c.demand_misses::total 162109 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses +system.l2c.demand_misses::cpu0.inst 6836 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 104850 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3992 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 46491 # number of demand (read+write) misses +system.l2c.demand_misses::total 162176 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5740 # number of overall misses -system.l2c.overall_misses::cpu0.data 74897 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses -system.l2c.overall_misses::cpu1.data 76421 # number of overall misses -system.l2c.overall_misses::total 162109 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 301916500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 419391498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 276443000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 222520500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1220670498 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 12958000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12012000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24970000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1618000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2458500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4076500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3033840500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3448903999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6482744499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 301916500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3453231998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 276443000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3671424499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7703414997 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 301916500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3453231998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 276443000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3671424499 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7703414997 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 3942 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1771 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 425514 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 213512 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5813 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2015 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 469168 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 147224 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1268959 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 571448 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 571448 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5920 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4197 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10117 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 780 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 583 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1363 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 123927 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 125279 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249206 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 3942 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1771 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 425514 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337439 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5813 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2015 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 469168 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 272503 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1518165 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 3942 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1771 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 425514 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337439 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5813 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2015 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 469168 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 272503 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1518165 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000254 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001129 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013490 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036846 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010751 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024582 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017555 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.796284 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.853467 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.820006 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.725641 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.821612 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.766691 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.540883 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.581119 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.561110 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000254 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001129 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013490 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.221957 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010751 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.280441 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.106780 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000254 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001129 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013490 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.221957 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000688 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010751 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.280441 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.106780 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52598.693380 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 53310.219652 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54806.304520 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 61486.736668 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 54795.102482 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2748.833263 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3353.433836 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3009.884282 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2858.657244 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5132.567850 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3900.956938 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 45260.935402 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47373.753455 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 46360.950991 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52598.693380 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 46106.412780 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 54806.304520 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 48042.089203 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 47519.971112 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52598.693380 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 46106.412780 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 54806.304520 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 48042.089203 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 47519.971112 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 6836 # number of overall misses +system.l2c.overall_misses::cpu0.data 104850 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3992 # number of overall misses +system.l2c.overall_misses::cpu1.data 46491 # number of overall misses +system.l2c.overall_misses::total 162176 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 395000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 487167000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 686875999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 283916500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 153770500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1612336499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 11351000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12155500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 23506500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1843000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1049000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2892000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6211024494 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 2810090500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9021114994 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 395000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 487167000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 6897900493 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 89000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 283916500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2963861000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10633451493 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 395000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 487167000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 6897900493 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 89000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 283916500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2963861000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10633451493 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4528 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1441 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 489950 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 251597 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 3782 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1869 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 376293 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 112467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1241927 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 576235 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 576235 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5292 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3796 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 9088 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 641 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 574 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1215 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 160689 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 90003 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 250692 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4528 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1441 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 489950 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 412286 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 3782 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1869 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 376293 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 202470 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1492619 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4528 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1441 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 489950 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 412286 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 3782 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1869 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 376293 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 202470 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1492619 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001388 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038621 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000535 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010609 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.016805 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018070 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.753212 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.886459 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.808869 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.599064 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.827526 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.706996 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.592032 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.495550 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.557393 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001388 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013952 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.254314 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000535 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010609 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.229619 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.108652 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001388 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013952 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.254314 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000535 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010609 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.229619 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.108652 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71264.921006 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 70688.072347 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71121.367735 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 81360.052910 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 71844.599367 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2847.717010 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3612.332838 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3197.728200 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4799.479167 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2208.421053 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3366.705471 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65287.802277 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63005.100782 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 64559.198148 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71264.921006 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 65788.273658 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71121.367735 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 63751.285195 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 65567.355792 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71264.921006 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 65788.273658 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71121.367735 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 63751.285195 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 65567.355792 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -466,159 +804,159 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64368 # number of writebacks -system.l2c.writebacks::total 64368 # number of writebacks +system.l2c.writebacks::writebacks 64628 # number of writebacks +system.l2c.writebacks::total 64628 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5739 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7867 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3619 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22276 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4714 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3582 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8296 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 566 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 479 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1045 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67030 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72802 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139832 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6835 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 9717 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3992 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1890 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22441 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 3986 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3365 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 7351 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 384 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 475 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 859 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 95133 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 44601 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139734 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5739 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 74897 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 76421 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 162108 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6835 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 104850 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3992 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 46491 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162175 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5739 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 74897 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 76421 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 162108 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 57502 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229892733 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 321315860 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 197504 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 213223286 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 177293869 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 942037005 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47255656 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 35939553 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 83195209 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5679055 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4807974 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10487029 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2184620679 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2537912723 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4722533402 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 57502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 229892733 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2505936539 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197504 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 213223286 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2715206592 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5664570407 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 57502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 229892733 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2505936539 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197504 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 213223286 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2715206592 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5664570407 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209633632 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12454752325 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3167837 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154325993526 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166993547320 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000474745 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209478823 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9209953568 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209633632 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13455227070 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3167837 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162535472349 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 176203500888 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000254 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001129 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013487 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036846 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017555 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.796284 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.853467 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.820006 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.725641 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.821612 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.766691 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540883 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581119 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.561110 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000254 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001129 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013487 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.221957 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.280441 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.106779 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000254 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001129 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013487 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.221957 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.280441 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.106779 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40843.505784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48989.739983 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 42289.325058 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10024.534578 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.376047 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.352097 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10033.666078 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.524008 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.434450 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32591.685499 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34860.480797 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 33772.908934 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33458.436773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35529.587312 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 34943.188535 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33458.436773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35529.587312 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34943.188535 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 6835 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 104850 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3992 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 46491 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162175 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 345500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 401430000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 565873249 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 233821750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 130194500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1331838749 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39898978 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33754347 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 73653325 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3848381 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4768474 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 8616855 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5004861313 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2258786863 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7263648176 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 345500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 401430000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5570734562 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 233821750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2388981363 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8595486925 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 345500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 401430000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5570734562 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 233821750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2388981363 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8595486925 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 340227750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648650244 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4863250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154086171248 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167079912492 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16271278232 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486203500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16757481732 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 340227750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919928476 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4863250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154572374748 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183837394224 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038621 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016805 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018070 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.753212 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.886459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.808869 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599064 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827526 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706996 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592032 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495550 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.557393 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108651 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108651 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58235.386333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68885.978836 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59348.458135 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.778726 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.009510 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.497347 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.825521 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.892632 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.263097 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52609.097926 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50644.309836 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 51981.966994 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -639,28 +977,237 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 118409228 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2504917 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2504917 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576235 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 27028 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16759 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993919 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951089 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5837 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 14921 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753559 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2879854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6195 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11995 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7617369 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31383352 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53719796 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 5764 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083148 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27940806 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7476 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 15128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 137173582 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137173582 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4313200 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4765991701 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2214801410 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2446229482 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 10393499 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1696938433 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 2203617971 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 4326998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 45438572 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution +system.iobus.trans_dist::WriteReq 7946 # Transaction distribution +system.iobus.trans_dist::WriteResp 7946 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382564 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 15358692 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389882 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 54294394 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294394 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 4037000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 12976128000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7074446 # DTB read hits -system.cpu0.dtb.read_misses 3765 # DTB read misses -system.cpu0.dtb.write_hits 5659669 # DTB write hits -system.cpu0.dtb.write_misses 803 # DTB write misses +system.cpu0.dtb.read_hits 9653493 # DTB read hits +system.cpu0.dtb.read_misses 3738 # DTB read misses +system.cpu0.dtb.write_hits 7597651 # DTB write hits +system.cpu0.dtb.write_misses 1585 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1806 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7078211 # DTB read accesses -system.cpu0.dtb.write_accesses 5660472 # DTB write accesses +system.cpu0.dtb.read_accesses 9657231 # DTB read accesses +system.cpu0.dtb.write_accesses 7599236 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12734115 # DTB hits -system.cpu0.dtb.misses 4568 # DTB misses -system.cpu0.dtb.accesses 12738683 # DTB accesses -system.cpu0.itb.inst_hits 29576941 # ITB inst hits +system.cpu0.dtb.hits 17251144 # DTB hits +system.cpu0.dtb.misses 5323 # DTB misses +system.cpu0.dtb.accesses 17256467 # DTB accesses +system.cpu0.itb.inst_hits 43299111 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -677,79 +1224,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29579146 # ITB inst accesses -system.cpu0.itb.hits 29576941 # DTB hits +system.cpu0.itb.inst_accesses 43301316 # ITB inst accesses +system.cpu0.itb.hits 43299111 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29579146 # DTB accesses -system.cpu0.numCycles 2366875007 # number of cpu cycles simulated +system.cpu0.itb.accesses 43301316 # DTB accesses +system.cpu0.numCycles 2389793161 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28878978 # Number of instructions committed -system.cpu0.committedOps 37226861 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33113061 # Number of integer alu accesses +system.cpu0.committedInsts 42572187 # Number of instructions committed +system.cpu0.committedOps 53304847 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48061724 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241874 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373945 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33113061 # number of integer instructions +system.cpu0.num_func_calls 1403541 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582883 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48061724 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190134215 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36237784 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272457591 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52272439 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13402466 # number of memory refs -system.cpu0.num_load_insts 7412077 # Number of load instructions -system.cpu0.num_store_insts 5990389 # Number of store instructions -system.cpu0.num_idle_cycles 2224972760.370120 # Number of idle cycles -system.cpu0.num_busy_cycles 141902246.629880 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059953 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940047 # Percentage of idle cycles +system.cpu0.num_mem_refs 18020656 # number of memory refs +system.cpu0.num_load_insts 10037354 # Number of load instructions +system.cpu0.num_store_insts 7983302 # Number of store instructions +system.cpu0.num_idle_cycles 2150335736.878201 # Number of idle cycles +system.cpu0.num_busy_cycles 239457424.121800 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100200 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899800 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed -system.cpu0.icache.replacements 425548 # number of replacements -system.cpu0.icache.tagsinuse 509.590371 # Cycle average of tags in use -system.cpu0.icache.total_refs 29150863 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 426060 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.419619 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75070085000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.590371 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995294 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995294 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29150863 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29150863 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29150863 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29150863 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29150863 # number of overall hits -system.cpu0.icache.overall_hits::total 29150863 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 426061 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 426061 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 426061 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 426061 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 426061 # number of overall misses -system.cpu0.icache.overall_misses::total 426061 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5812849500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5812849500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5812849500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5812849500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5812849500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5812849500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29576924 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29576924 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29576924 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29576924 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29576924 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29576924 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13643.233011 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13643.233011 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13643.233011 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13643.233011 # average overall miss latency +system.cpu0.kern.inst.quiesce 51313 # number of quiesce instructions executed +system.cpu0.icache.replacements 490180 # number of replacements +system.cpu0.icache.tagsinuse 509.396236 # Cycle average of tags in use +system.cpu0.icache.total_refs 42808401 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 490692 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 87.240878 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 76020026000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.396236 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994915 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994915 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42808401 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42808401 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42808401 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42808401 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42808401 # number of overall hits +system.cpu0.icache.overall_hits::total 42808401 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490693 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490693 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490693 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490693 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490693 # number of overall misses +system.cpu0.icache.overall_misses::total 490693 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812744000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6812744000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6812744000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6812744000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6812744000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6812744000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43299094 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43299094 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43299094 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43299094 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43299094 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43299094 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011333 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011333 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011333 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011333 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011333 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011333 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13883.923349 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13883.923349 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13883.923349 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13883.923349 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -758,120 +1305,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 426061 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 426061 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 426061 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 426061 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 426061 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 426061 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4960727500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4960727500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4960727500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4960727500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4960727500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4960727500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11643.233011 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11643.233011 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11643.233011 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490693 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490693 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490693 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490693 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490693 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490693 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5831313090 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5831313090 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5831313090 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5831313090 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5831313090 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5831313090 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 430167000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 430167000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 430167000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 430167000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011333 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011333 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011333 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11883.831826 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330262 # number of replacements -system.cpu0.dcache.tagsinuse 452.976504 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12279097 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 330774 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.122316 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 473556000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 452.976504 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.884720 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.884720 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6604621 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6604621 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5354486 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5354486 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147953 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147953 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149702 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149702 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11959107 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11959107 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11959107 # number of overall hits -system.cpu0.dcache.overall_hits::total 11959107 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 227474 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 227474 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141720 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141720 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9335 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9335 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7505 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7505 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369194 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 369194 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 369194 # number of overall misses -system.cpu0.dcache.overall_misses::total 369194 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3141338000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3141338000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4161237500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4161237500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88637000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88637000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44352500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44352500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 7302575500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 7302575500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7302575500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7302575500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6832095 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6832095 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496206 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5496206 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157288 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157288 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157207 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157207 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12328301 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12328301 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12328301 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12328301 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033295 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033295 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025785 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025785 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059350 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059350 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047740 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047740 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029947 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029947 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029947 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029947 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13809.657367 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13809.657367 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29362.387101 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29362.387101 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9495.125870 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9495.125870 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5909.726849 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5909.726849 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19779.778382 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19779.778382 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19779.778382 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19779.778382 # average overall miss latency +system.cpu0.dcache.replacements 406656 # number of replacements +system.cpu0.dcache.tagsinuse 471.250698 # Cycle average of tags in use +system.cpu0.dcache.total_refs 15968393 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 407168 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 39.218192 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 652579000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 471.250698 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.920412 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.920412 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9137588 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9137588 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6495058 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6495058 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156529 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156529 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159015 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 159015 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 15632646 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 15632646 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 15632646 # number of overall hits +system.cpu0.dcache.overall_hits::total 15632646 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 263671 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 263671 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 176701 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 176701 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9917 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9917 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7374 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7374 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 440372 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 440372 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 440372 # number of overall misses +system.cpu0.dcache.overall_misses::total 440372 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3870373500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3870373500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7511792500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7511792500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99127000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 99127000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40277500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 40277500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11382166000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11382166000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11382166000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11382166000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9401259 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9401259 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6671759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166446 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 166446 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166389 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166389 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16073018 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16073018 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16073018 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16073018 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028046 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028046 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026485 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026485 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059581 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059581 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044318 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044318 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14678.798579 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14678.798579 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42511.318555 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42511.318555 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9995.664011 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9995.664011 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5462.096555 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5462.096555 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25846.706875 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25846.706875 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -880,66 +1427,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306255 # number of writebacks -system.cpu0.dcache.writebacks::total 306255 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227474 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227474 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141720 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141720 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9335 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9335 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7498 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7498 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369194 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369194 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369194 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369194 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2686390000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2686390000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3877797500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3877797500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69967000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69967000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29358500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29358500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 376588 # number of writebacks +system.cpu0.dcache.writebacks::total 376588 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263671 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 263671 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176701 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176701 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9917 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9917 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7370 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7370 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440372 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440372 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440372 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440372 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3343027009 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3343027009 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7158388504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7158388504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79292501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79292501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25539500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25539500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6564187500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6564187500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6564187500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6564187500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562288000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562288000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128633000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128633000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690921000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690921000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033295 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033295 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025785 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025785 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059350 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059350 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047695 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047695 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029947 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029947 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11809.657367 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11809.657367 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27362.387101 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27362.387101 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7495.125870 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7495.125870 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.510803 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.510803 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10501415513 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10501415513 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10501415513 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10501415513 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765210500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765210500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807067504 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807067504 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572278004 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572278004 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12678.781546 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12678.781546 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40511.307259 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40511.307259 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7995.613694 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7995.613694 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3465.332429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3465.332429 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -949,26 +1496,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8312224 # DTB read hits -system.cpu1.dtb.read_misses 3649 # DTB read misses -system.cpu1.dtb.write_hits 5828610 # DTB write hits -system.cpu1.dtb.write_misses 1432 # DTB write misses +system.cpu1.dtb.read_hits 5706432 # DTB read hits +system.cpu1.dtb.read_misses 3576 # DTB read misses +system.cpu1.dtb.write_hits 3873109 # DTB write hits +system.cpu1.dtb.write_misses 645 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8315873 # DTB read accesses -system.cpu1.dtb.write_accesses 5830042 # DTB write accesses +system.cpu1.dtb.read_accesses 5710008 # DTB read accesses +system.cpu1.dtb.write_accesses 3873754 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14140834 # DTB hits -system.cpu1.dtb.misses 5081 # DTB misses -system.cpu1.dtb.accesses 14145915 # DTB accesses -system.cpu1.itb.inst_hits 33192056 # ITB inst hits +system.cpu1.dtb.hits 9579541 # DTB hits +system.cpu1.dtb.misses 4221 # DTB misses +system.cpu1.dtb.accesses 9583762 # DTB accesses +system.cpu1.itb.inst_hits 19379683 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -985,79 +1532,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33194227 # ITB inst accesses -system.cpu1.itb.hits 33192056 # DTB hits +system.cpu1.itb.inst_accesses 19381854 # ITB inst accesses +system.cpu1.itb.hits 19379683 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33194227 # DTB accesses -system.cpu1.numCycles 2365415230 # number of cpu cycles simulated +system.cpu1.itb.accesses 19381854 # DTB accesses +system.cpu1.numCycles 2388360365 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32581554 # Number of instructions committed -system.cpu1.committedOps 41094791 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37318858 # Number of integer alu accesses +system.cpu1.committedInsts 18799110 # Number of instructions committed +system.cpu1.committedOps 24903355 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22267252 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962092 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732954 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37318858 # number of integer instructions +system.cpu1.num_func_calls 796685 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514656 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22267252 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213696952 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39459665 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130770555 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23319815 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14678596 # number of memory refs -system.cpu1.num_load_insts 8634126 # Number of load instructions -system.cpu1.num_store_insts 6044470 # Number of store instructions -system.cpu1.num_idle_cycles 1868274479.951726 # Number of idle cycles -system.cpu1.num_busy_cycles 497140750.048273 # Number of busy cycles -system.cpu1.not_idle_fraction 0.210171 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.789829 # Percentage of idle cycles +system.cpu1.num_mem_refs 10014978 # number of memory refs +system.cpu1.num_load_insts 5983060 # Number of load instructions +system.cpu1.num_store_insts 4031918 # Number of store instructions +system.cpu1.num_idle_cycles 1968746844.438183 # Number of idle cycles +system.cpu1.num_busy_cycles 419613520.561817 # Number of busy cycles +system.cpu1.not_idle_fraction 0.175691 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.824309 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43886 # number of quiesce instructions executed -system.cpu1.icache.replacements 469169 # number of replacements -system.cpu1.icache.tagsinuse 478.729775 # Cycle average of tags in use -system.cpu1.icache.total_refs 32722371 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469681 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.669352 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92399174500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.729775 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935019 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935019 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32722371 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32722371 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32722371 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32722371 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32722371 # number of overall hits -system.cpu1.icache.overall_hits::total 32722371 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469681 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469681 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469681 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469681 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469681 # number of overall misses -system.cpu1.icache.overall_misses::total 469681 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6362521500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6362521500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6362521500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6362521500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6362521500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6362521500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33192052 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33192052 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33192052 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33192052 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33192052 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33192052 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014150 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014150 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014150 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014150 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014150 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014150 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13546.474096 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13546.474096 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13546.474096 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13546.474096 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13546.474096 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13546.474096 # average overall miss latency +system.cpu1.kern.inst.quiesce 39066 # number of quiesce instructions executed +system.cpu1.icache.replacements 376556 # number of replacements +system.cpu1.icache.tagsinuse 474.951242 # Cycle average of tags in use +system.cpu1.icache.total_refs 19002611 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 377068 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 50.395714 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 327008186500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 474.951242 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.927639 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.927639 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19002611 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19002611 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19002611 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19002611 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19002611 # number of overall hits +system.cpu1.icache.overall_hits::total 19002611 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377068 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377068 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377068 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377068 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377068 # number of overall misses +system.cpu1.icache.overall_misses::total 377068 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5155062500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5155062500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5155062500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5155062500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5155062500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5155062500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379679 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19379679 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19379679 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19379679 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19379679 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19379679 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019457 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019457 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019457 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019457 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019457 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019457 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.439899 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.439899 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13671.439899 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13671.439899 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1066,120 +1613,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469681 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 469681 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 469681 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 469681 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 469681 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 469681 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5423159500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5423159500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5423159500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5423159500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5423159500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5423159500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4481000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4481000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4481000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 4481000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014150 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014150 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014150 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11546.474096 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11546.474096 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11546.474096 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377068 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 377068 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 377068 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 377068 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 377068 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 377068 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4400893067 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4400893067 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4400893067 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4400893067 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4400893067 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4400893067 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6177000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6177000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6177000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6177000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019457 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019457 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019457 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.351234 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.351234 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.351234 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 292058 # number of replacements -system.cpu1.dcache.tagsinuse 471.819179 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11963833 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 292409 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.914722 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 83872114000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 471.819179 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.921522 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.921522 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6947661 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6947661 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4828322 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4828322 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81798 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81798 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82734 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82734 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11775983 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11775983 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11775983 # number of overall hits -system.cpu1.dcache.overall_hits::total 11775983 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170592 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170592 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 149961 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 149961 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11053 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11053 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10044 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10044 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320553 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320553 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320553 # number of overall misses -system.cpu1.dcache.overall_misses::total 320553 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2164105500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2164105500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4535823500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4535823500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92227500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 92227500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51992500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 51992500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6699929000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6699929000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6699929000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6699929000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118253 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7118253 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4978283 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4978283 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92851 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 92851 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92778 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92778 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12096536 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12096536 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12096536 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12096536 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023965 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023965 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030123 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030123 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119040 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119040 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108258 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108258 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026500 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026500 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026500 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026500 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12685.855726 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12685.855726 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30246.687472 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30246.687472 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8344.114720 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8344.114720 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5176.473517 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5176.473517 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20901.158311 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20901.158311 # average overall miss latency +system.cpu1.dcache.replacements 220463 # number of replacements +system.cpu1.dcache.tagsinuse 471.524014 # Cycle average of tags in use +system.cpu1.dcache.total_refs 8230847 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 220830 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 37.272323 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 106217593500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 471.524014 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.920945 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.920945 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 4389322 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4389322 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3673243 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3673243 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73459 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 73459 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73734 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 73734 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8062565 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8062565 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8062565 # number of overall hits +system.cpu1.dcache.overall_hits::total 8062565 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133853 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133853 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 112791 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 112791 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9745 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9745 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9392 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9392 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 246644 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 246644 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 246644 # number of overall misses +system.cpu1.dcache.overall_misses::total 246644 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1652691000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1652691000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3703180000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3703180000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77927500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77927500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48937000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 48937000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5355871000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5355871000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5355871000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5355871000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4523175 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4523175 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3786034 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3786034 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83204 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 83204 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83126 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83126 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8309209 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8309209 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8309209 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8309209 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029593 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.029593 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029791 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029791 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117122 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117122 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112985 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112985 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029683 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029683 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029683 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.029683 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12347.059834 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12347.059834 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32832.229522 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32832.229522 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7996.664956 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7996.664956 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5210.498296 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5210.498296 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21714.985972 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21714.985972 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1188,66 +1735,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265193 # number of writebacks -system.cpu1.dcache.writebacks::total 265193 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170592 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170592 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149961 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149961 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11053 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11053 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10042 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10042 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320553 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320553 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320553 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320553 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1822921500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1822921500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4235901500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4235901500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70121500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70121500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31910500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31910500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 199647 # number of writebacks +system.cpu1.dcache.writebacks::total 199647 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133853 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133853 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112791 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112791 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9745 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9745 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9391 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9391 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246644 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246644 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246644 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246644 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384976517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384976517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3477593010 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3477593010 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58436502 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58436502 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30157000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30157000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6058823000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6058823000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6058823000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6058823000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642031500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642031500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668268500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668268500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186310300000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186310300000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023965 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023965 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119040 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119040 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108237 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108237 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026500 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026500 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10685.855726 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10685.855726 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28246.687472 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28246.687472 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6344.114720 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6344.114720 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3177.703645 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3177.703645 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4862569527 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4862569527 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4862569527 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4862569527 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387734500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387734500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531024500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531024500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029593 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029593 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029791 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029791 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117122 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117122 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112973 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112973 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029683 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029683 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10346.996459 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10346.996459 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30832.185281 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30832.185281 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5996.562545 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5996.562545 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3211.266106 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3211.266106 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1269,10 +1816,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509664351240 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 509664351240 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509664351240 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 509664351240 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 626235127001 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 626235127001 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 626235127001 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 626235127001 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 4975edc6e..934a4cb6c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603674 # Number of seconds simulated -sim_ticks 2603674284000 # Number of ticks simulated -final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.615622 # Number of seconds simulated +sim_ticks 2615622384000 # Number of ticks simulated +final_tick 2615622384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271279 # Simulator instruction rate (inst/s) -host_op_rate 345198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11733407598 # Simulator tick rate (ticks/s) -host_mem_usage 403640 # Number of bytes of host memory used -host_seconds 221.90 # Real time elapsed on the host -sim_insts 60197457 # Number of instructions simulated -sim_ops 76600355 # Number of ops (including micro ops) simulated +host_inst_rate 264818 # Simulator instruction rate (inst/s) +host_op_rate 336993 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11506330329 # Simulator tick rate (ticks/s) +host_mem_usage 396436 # Number of bytes of host memory used +host_seconds 227.32 # Real time elapsed on the host +sim_insts 60198587 # Number of instructions simulated +sim_ops 76605405 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory -system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory +system.physmem.bytes_read::total 132481840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3709760 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory +system.physmem.bytes_written::total 6725832 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494761 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57965 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494095 # Total number of read requests seen -system.physmem.writeReqs 811481 # Total number of write requests seen -system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991622080 # Total number of bytes read from memory -system.physmem.bytesWritten 51934784 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis +system.physmem.num_writes::total 811983 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46904092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3476496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50650216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1418309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153099 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2571408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1418309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46904092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4629595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53221624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494761 # Total number of read requests seen +system.physmem.writeReqs 811983 # Total number of write requests seen +system.physmem.cpureqs 215166 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991664704 # Total number of bytes read from memory +system.physmem.bytesWritten 51966912 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132481840 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6725832 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 301 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967904 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 967946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 974722 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 968494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968523 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 968301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 967930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967683 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49010 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50853 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51430 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51246 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50878 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 50871 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50825 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 50676 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603669924000 # Total gap between requests +system.physmem.totGap 2615618000000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152019 # Categorize read packet sizes +system.physmem.readPktSize::6 152685 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57463 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1115862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976049 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3645924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2755202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2757935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2724600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 64133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 62351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 163253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 112534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57965 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1126555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 973164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1018253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3775658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2831038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2826406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2774250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 19136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 31670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 43534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 30921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -139,59 +139,340 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests -system.physmem.totBusLat 77468795000 # Total cycles spent in databus access -system.physmem.totBankLat 17451610000 # Total cycles spent in bank access -system.physmem.avgQLat 22040.37 # Average queueing delay per request -system.physmem.avgBankLat 1126.36 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 38567 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 27059.676926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2495.376643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33105.439598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5489 14.23% 14.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3331 8.64% 22.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2176 5.64% 28.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1697 4.40% 32.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1162 3.01% 35.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1046 2.71% 38.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 828 2.15% 40.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 748 1.94% 42.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 582 1.51% 44.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 509 1.32% 45.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 411 1.07% 46.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 479 1.24% 47.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 285 0.74% 48.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 248 0.64% 49.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 187 0.48% 49.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 239 0.62% 50.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 141 0.37% 50.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 137 0.36% 51.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 106 0.27% 51.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 105 0.27% 51.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 92 0.24% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 151 0.39% 52.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 970 2.52% 54.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 135 0.35% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 110 0.29% 55.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 77 0.20% 56.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 66 0.17% 56.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 47 0.12% 56.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 64 0.17% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 37 0.10% 57.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 25 0.06% 57.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 18 0.05% 57.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 25 0.06% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 26 0.07% 57.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 13 0.03% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 25 0.06% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 14 0.04% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 8 0.02% 57.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 18 0.05% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 9 0.02% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 17 0.04% 57.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 7 0.02% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 12 0.03% 57.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 12 0.03% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 3 0.01% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 9 0.02% 57.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 9 0.02% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 4 0.01% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 44 0.11% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 3 0.01% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 2 0.01% 58.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 5 0.01% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 2 0.01% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 2 0.01% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 7 0.02% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 6 0.02% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 1 0.00% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 12 0.03% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 3 0.01% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 7 0.02% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 2 0.01% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 2 0.01% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 2 0.01% 58.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 6 0.02% 58.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 3 0.01% 58.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 2 0.01% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 3 0.01% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 180 0.47% 58.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 1 0.00% 58.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 3 0.01% 58.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 5 0.01% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 3 0.01% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 2 0.01% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 11 0.03% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 3 0.01% 59.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 4 0.01% 59.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 4 0.01% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 3 0.01% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 1 0.00% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 6 0.02% 59.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 4 0.01% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 5 0.01% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 3 0.01% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9535 2 0.01% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10815 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11263 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 2 0.01% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11583 2 0.01% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11647 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11839 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12351 3 0.01% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12607 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13631 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 2 0.01% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14655 2 0.01% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 3 0.01% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15743 1 0.00% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 2 0.01% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17983 1 0.00% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 2 0.01% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19071 1 0.00% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 3 0.01% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 2 0.01% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 2 0.01% 60.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22591 4 0.01% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23103 3 0.01% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 5 0.01% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24127 2 0.01% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-25023 1 0.00% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 3 0.01% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25919 2 0.01% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26431 1 0.00% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 4 0.01% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26943 1 0.00% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28159 1 0.00% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 1 0.00% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28991 1 0.00% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29439 1 0.00% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 6 0.02% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 2 0.01% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 3 0.01% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 3 0.01% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 5 0.01% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 4 0.01% 60.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33599 56 0.15% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33663 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34111 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37439 1 0.00% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38975 1 0.00% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39999 2 0.01% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42303 1 0.00% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42559 2 0.01% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43583 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45119 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45631 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 2 0.01% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49727 2 0.01% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52480-52543 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52992-53055 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 3 0.01% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57088-57151 1 0.00% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60479 2 0.01% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61503 1 0.00% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 2 0.01% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63808-63871 1 0.00% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64575 1 0.00% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 14789 38.35% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-74047 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::83008-83071 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::93120-93183 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97152-97215 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97408-97471 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::103680-103743 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::104768-104831 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::106432-106495 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109760-109823 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::110912-110975 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::114240-114303 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::115328-115391 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::116992-117055 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120320-120383 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121472-121535 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::124416-124479 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::127552-127615 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128640-128703 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130496-130559 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::161408-161471 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::190336-190399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38567 # Bytes accessed per row activation +system.physmem.totQLat 306544443250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 400266823250 # Sum of mem lat for all requests +system.physmem.totBusLat 77472300000 # Total cycles spent in databus access +system.physmem.totBankLat 16250080000 # Total cycles spent in bank access +system.physmem.avgQLat 19784.13 # Average queueing delay per request +system.physmem.avgBankLat 1048.77 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28166.74 # Average memory access latency -system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 25832.90 # Average memory access latency +system.physmem.avgRdBW 379.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.13 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 12.40 # Average write queue length over time -system.physmem.readRowHits 15418728 # Number of row buffer hits during reads -system.physmem.writeRowHits 794030 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes -system.physmem.avgGap 159679.73 # Average gap between requests +system.physmem.busUtil 3.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 10.80 # Average write queue length over time +system.physmem.readRowHits 15469403 # Number of row buffer hits during reads +system.physmem.writeRowHits 798459 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes +system.physmem.avgGap 160401.00 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -204,34 +485,248 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54138467 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546589 # Transaction distribution +system.membus.trans_dist::ReadResp 16546589 # Transaction distribution +system.membus.trans_dist::WriteReq 763368 # Transaction distribution +system.membus.trans_dist::WriteResp 763368 # Transaction distribution +system.membus.trans_dist::Writeback 57965 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 132246 # Transaction distribution +system.membus.trans_dist::ReadExResp 132246 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893707 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32564555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34951403 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16524280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18922393 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 139207672 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 141605785 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141605785 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1206150500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17904777500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4945376509 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 34635651750 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.iobus.throughput 47817981 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution +system.iobus.trans_dist::WriteReq 8166 # Transaction distribution +system.iobus.trans_dist::WriteResp 8166 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073781 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 30670848000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995645 # DTB read hits -system.cpu.dtb.read_misses 7332 # DTB read misses -system.cpu.dtb.write_hits 11230857 # DTB write hits -system.cpu.dtb.write_misses 2203 # DTB write misses +system.cpu.dtb.read_hits 14996055 # DTB read hits +system.cpu.dtb.read_misses 7342 # DTB read misses +system.cpu.dtb.write_hits 11230429 # DTB write hits +system.cpu.dtb.write_misses 2216 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002977 # DTB read accesses -system.cpu.dtb.write_accesses 11233060 # DTB write accesses +system.cpu.dtb.read_accesses 15003397 # DTB read accesses +system.cpu.dtb.write_accesses 11232645 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226502 # DTB hits -system.cpu.dtb.misses 9535 # DTB misses -system.cpu.dtb.accesses 26236037 # DTB accesses -system.cpu.itb.inst_hits 61491397 # ITB inst hits +system.cpu.dtb.hits 26226484 # DTB hits +system.cpu.dtb.misses 9558 # DTB misses +system.cpu.dtb.accesses 26236042 # DTB accesses +system.cpu.itb.inst_hits 61492425 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -248,79 +743,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495868 # ITB inst accesses -system.cpu.itb.hits 61491397 # DTB hits +system.cpu.itb.inst_accesses 61496896 # ITB inst accesses +system.cpu.itb.hits 61492425 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495868 # DTB accesses -system.cpu.numCycles 5207348568 # number of cpu cycles simulated +system.cpu.itb.accesses 61496896 # DTB accesses +system.cpu.numCycles 5231244768 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197457 # Number of instructions committed -system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses +system.cpu.committedInsts 60198587 # Number of instructions committed +system.cpu.committedOps 76605405 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872209 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139722 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls -system.cpu.num_int_insts 68868122 # number of integer instructions +system.cpu.num_func_calls 2140451 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948368 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872209 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read -system.cpu.num_int_register_writes 74176013 # number of times the integer registers were written +system.cpu.num_int_register_reads 394776354 # number of times the integer registers were read +system.cpu.num_int_register_writes 74181797 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393871 # number of memory refs -system.cpu.num_load_insts 15659652 # Number of load instructions -system.cpu.num_store_insts 11734219 # Number of store instructions -system.cpu.num_idle_cycles 4579092042.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628256525.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120648 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879352 # Percentage of idle cycles +system.cpu.num_mem_refs 27393915 # number of memory refs +system.cpu.num_load_insts 15660071 # Number of load instructions +system.cpu.num_store_insts 11733844 # Number of store instructions +system.cpu.num_idle_cycles 4582065338.612248 # Number of idle cycles +system.cpu.num_busy_cycles 649179429.387752 # Number of busy cycles +system.cpu.not_idle_fraction 0.124097 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875903 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855484 # number of replacements -system.cpu.icache.tagsinuse 510.979435 # Cycle average of tags in use -system.cpu.icache.total_refs 60635401 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855996 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.836080 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.979435 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635401 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635401 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635401 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635401 # number of overall hits -system.cpu.icache.overall_hits::total 60635401 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855996 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855996 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855996 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855996 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855996 # number of overall misses -system.cpu.icache.overall_misses::total 855996 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11568776000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11568776000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11568776000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11568776000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11568776000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11568776000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13514.988388 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13514.988388 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13514.988388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13514.988388 # average overall miss latency +system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed +system.cpu.icache.replacements 856250 # number of replacements +system.cpu.icache.tagsinuse 510.885364 # Cycle average of tags in use +system.cpu.icache.total_refs 60635663 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856762 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.773054 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19768699000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.885364 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997823 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997823 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635663 # number of overall hits +system.cpu.icache.overall_hits::total 60635663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856762 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856762 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856762 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856762 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856762 # number of overall misses +system.cpu.icache.overall_misses::total 856762 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11759087500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11759087500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11759087500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11759087500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11759087500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11759087500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61492425 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61492425 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61492425 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61492425 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61492425 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61492425 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.033907 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13725.033907 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13725.033907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13725.033907 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -329,174 +824,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855996 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855996 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 855996 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 855996 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 855996 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 855996 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9856784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9856784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9856784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9856784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9856784000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9856784000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 298856500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 298856500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 298856500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11514.988388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11514.988388 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11514.988388 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11514.988388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11514.988388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11514.988388 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856762 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856762 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856762 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856762 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856762 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856762 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10045563500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10045563500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10045563500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10045563500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10045563500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10045563500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 429084500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 429084500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 429084500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 429084500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11725.033907 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11725.033907 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11725.033907 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11725.033907 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11725.033907 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11725.033907 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 61912 # number of replacements -system.cpu.l2cache.tagsinuse 50892.966587 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1682705 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127293 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.219148 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2553153097000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37868.000507 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885514 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001401 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6995.362387 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6025.716777 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.577820 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 62577 # number of replacements +system.cpu.l2cache.tagsinuse 50733.086800 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1684914 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 128011 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 13.162259 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2564823166000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37695.331461 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.884612 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000689 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 6997.589035 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6036.281004 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.575185 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.106741 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.091945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.776565 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8701 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 843754 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370328 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226331 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 596040 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 596040 # number of Writeback hits +system.cpu.l2cache.occ_percent::cpu.inst 0.106775 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.092106 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.774125 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8724 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3533 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 844523 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 369967 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226747 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595512 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595512 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 114438 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 114438 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8701 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 843754 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484766 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340769 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8701 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 843754 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484766 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340769 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113491 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113491 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 8724 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3533 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 844523 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 483458 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1340238 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 8724 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3533 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 844523 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 483458 # number of overall hits +system.cpu.l2cache.overall_hits::total 1340238 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20471 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2875 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133183 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133183 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 9833 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20439 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2885 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2885 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133877 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133877 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143042 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153654 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143710 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154316 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143042 # number of overall misses -system.cpu.l2cache.overall_misses::total 153654 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 315500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 151000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 561610000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 535948000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1098024500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 462000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 462000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6083213000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6083213000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 315500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 151000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 561610000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6619161000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7181237500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 315500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 151000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 561610000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6619161000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7181237500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8706 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 854358 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380187 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1246802 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 596040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 596040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247621 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247621 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8706 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 854358 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627808 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494423 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8706 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 854358 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627808 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494423 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012412 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025932 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016419 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537850 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.537850 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012412 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.227844 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.102818 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012412 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.227844 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.102818 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 63100 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 50333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52962.089777 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54361.294249 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53638.048947 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.695652 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.695652 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45675.596735 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45675.596735 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52962.089777 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.248123 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46736.417536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52962.089777 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.248123 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46736.417536 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143710 # number of overall misses +system.cpu.l2cache.overall_misses::total 154316 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 468000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 741931500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 698335500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1440857000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8582435500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8582435500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 468000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 122000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 741931500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9280771000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10023292500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 468000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 122000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 741931500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9280771000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10023292500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8729 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3535 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 855122 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 379800 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1247186 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 595512 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 595512 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2911 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2911 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247368 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247368 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8729 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3535 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 855122 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627168 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494554 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8729 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3535 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 855122 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627168 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494554 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000573 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012395 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025890 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016388 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991068 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991068 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541206 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541206 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000573 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012395 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229141 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103252 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000573 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012395 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229141 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103252 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93600 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70000.141523 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71019.576935 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70495.474338 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.445407 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.445407 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64106.870486 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64106.870486 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93600 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70000.141523 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64579.855264 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 64953.034682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93600 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70000.141523 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64579.855264 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 64953.034682 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,92 +1000,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57463 # number of writebacks -system.cpu.l2cache.writebacks::total 57463 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57965 # number of writebacks +system.cpu.l2cache.writebacks::total 57965 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10604 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20471 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133183 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133183 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9833 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 20439 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2885 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2885 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133877 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133877 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10604 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143042 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 153654 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143710 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154316 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10604 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143042 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 153654 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 253755 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 113753 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 430132104 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413197859 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 843697471 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28847322 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28847322 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4445123890 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4445123890 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 253755 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 113753 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 430132104 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4858321749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5288821361 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 253755 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 113753 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 430132104 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4858321749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5288821361 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209116116 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166689052786 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166898168902 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175171345 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175171345 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209116116 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175864224131 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176073340247 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016419 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537850 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537850 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.102818 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.102818 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40563.193512 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41910.727153 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41214.277319 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10033.851130 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10033.851130 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33376.060683 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33376.060683 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143710 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154316 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 404750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 611089500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 576558000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1188149750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28854885 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28854885 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6940085381 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6940085381 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 404750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 97500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 611089500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7516643381 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8128235131 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 404750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 97500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 611089500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7516643381 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8128235131 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 339371500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657063250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166996434750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16701843725 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16701843725 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 339371500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183358906975 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183698278475 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025890 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016388 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991068 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991068 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541206 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541206 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229141 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103252 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229141 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103252 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57655.392018 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58635.004576 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58131.501052 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.693241 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.693241 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51839.265751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51839.265751 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57655.392018 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52304.247311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52672.666029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57655.392018 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52304.247311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52672.666029 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -600,79 +1095,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627296 # number of replacements -system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655010 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627808 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.678733 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195118 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195118 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973036 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973036 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168154 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168154 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168154 # number of overall hits -system.cpu.dcache.overall_hits::total 23168154 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368785 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368785 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250522 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250522 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619307 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619307 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619307 # number of overall misses -system.cpu.dcache.overall_misses::total 619307 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5224078000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5224078000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8042704500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8042704500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155711000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 155711000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13266782500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13266782500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13266782500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13266782500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024504 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024504 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14165.646650 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14165.646650 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32103.785296 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32103.785296 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13656.463778 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13656.463778 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21421.980536 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21421.980536 # average overall miss latency +system.cpu.dcache.replacements 626656 # number of replacements +system.cpu.dcache.tagsinuse 511.879114 # Cycle average of tags in use +system.cpu.dcache.total_refs 23655617 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627168 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.718150 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 650249000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.879114 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999764 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999764 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195840 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195840 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972724 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972724 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236345 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236345 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247797 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247797 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23168564 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168564 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168564 # number of overall hits +system.cpu.dcache.overall_hits::total 23168564 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368347 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368347 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250279 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250279 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11453 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11453 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 618626 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618626 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618626 # number of overall misses +system.cpu.dcache.overall_misses::total 618626 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5378545500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5378545500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10531910500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10531910500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158860000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158860000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15910456000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15910456000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15910456000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15910456000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564187 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564187 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223003 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223003 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247798 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247798 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247797 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247797 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23787190 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787190 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787190 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787190 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027156 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027156 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024482 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024482 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046219 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046219 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026007 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026007 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026007 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026007 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14601.844185 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14601.844185 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42080.679961 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42080.679961 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13870.601589 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13870.601589 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25719.022479 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25719.022479 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -681,54 +1176,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596040 # number of writebacks -system.cpu.dcache.writebacks::total 596040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368785 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368785 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250522 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250522 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619307 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619307 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619307 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619307 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4486508000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4486508000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7541660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7541660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132907000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132907000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028168500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12028168500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028168500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12028168500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082624500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082624500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18709226000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18709226000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200791850500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 200791850500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024504 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12165.646650 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12165.646650 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30103.785296 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30103.785296 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11656.463778 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11656.463778 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595512 # number of writebacks +system.cpu.dcache.writebacks::total 595512 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368347 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368347 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250279 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250279 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11453 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618626 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618626 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618626 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618626 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4641851500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4641851500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031352500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031352500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135954000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135954000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14673204000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14673204000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14673204000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14673204000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050723500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050723500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234076500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234076500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284800000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284800000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026007 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026007 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12601.844185 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12601.844185 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40080.679961 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40080.679961 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11870.601589 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11870.601589 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -736,6 +1231,38 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 53002965 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 595512 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247368 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725126 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5750616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27468 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7515671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54754292 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83665829 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34916 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 138469177 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138469177 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166564 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3009252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1291764000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2507996500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 18739000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -750,10 +1277,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1470128900250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1470128900250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 1dc10f98b..35b3a08bb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,25 +4,13 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1307768 # Simulator instruction rate (inst/s) -host_op_rate 1681709 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50502250863 # Simulator tick rate (ticks/s) -host_mem_usage 395644 # Number of bytes of host memory used -host_seconds 46.19 # Real time elapsed on the host +host_inst_rate 662335 # Simulator instruction rate (inst/s) +host_op_rate 851722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25577480180 # Simulator tick rate (ticks/s) +host_mem_usage 396424 # Number of bytes of host memory used +host_seconds 91.21 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory @@ -196,6 +184,9 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -217,6 +208,21 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55969561 # Throughput (bytes/s) +system.membus.data_through_bus 130566366 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.l2c.replacements 62242 # number of replacements system.l2c.tagsinuse 50006.300222 # Cycle average of tags in use system.l2c.total_refs 1678485 # Total number of references to valid blocks. @@ -379,6 +385,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 59119250 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 137913994 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.iobus.throughput 48895252 # Throughput (bytes/s) +system.iobus.data_through_bus 114063346 # Total data (bytes) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 7929205 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 81ef154d3..3eb24dda0 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112100 # Nu sim_ticks 5112099860500 # Number of ticks simulated final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019592 # Simulator instruction rate (inst/s) -host_op_rate 2087576 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26073588986 # Simulator tick rate (ticks/s) -host_mem_usage 631672 # Number of bytes of host memory used -host_seconds 196.06 # Real time elapsed on the host +host_inst_rate 794426 # Simulator instruction rate (inst/s) +host_op_rate 1626557 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20315509625 # Simulator tick rate (ticks/s) +host_mem_usage 586244 # Number of bytes of host memory used +host_seconds 251.64 # Real time elapsed on the host sim_insts 199905607 # Number of instructions simulated sim_ops 409299132 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory @@ -168,6 +168,9 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -189,6 +192,9 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests +system.membus.throughput 9632717 # Throughput (bytes/s) +system.membus.data_through_bus 49243411 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.replacements 47568 # number of replacements system.iocache.tagsinuse 0.042441 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -245,6 +251,8 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.throughput 2555194 # Throughput (bytes/s) +system.iobus.data_through_bus 13062406 # Total data (bytes) system.cpu.numCycles 10224199744 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -455,6 +463,9 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 1535700 # number of writebacks system.cpu.dcache.writebacks::total 1535700 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 54622198 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 279208723 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 25408 # Total snoop data (bytes) system.cpu.l2cache.replacements 105930 # number of replacements system.cpu.l2cache.tagsinuse 64819.953901 # Cycle average of tags in use system.cpu.l2cache.total_refs 3456506 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 452558553..3847513ea 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,126 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.187336 # Number of seconds simulated -sim_ticks 5187335906000 # Number of ticks simulated -final_tick 5187335906000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196145 # Number of seconds simulated +sim_ticks 5196144770000 # Number of ticks simulated +final_tick 5196144770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 633010 # Simulator instruction rate (inst/s) -host_op_rate 1220249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25590316667 # Simulator tick rate (ticks/s) -host_mem_usage 632708 # Number of bytes of host memory used -host_seconds 202.71 # Real time elapsed on the host -sim_insts 128315489 # Number of instructions simulated -sim_ops 247353048 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2850304 # Number of bytes read from this memory +host_inst_rate 471788 # Simulator instruction rate (inst/s) +host_op_rate 909467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19106715414 # Simulator tick rate (ticks/s) +host_mem_usage 586268 # Number of bytes of host memory used +host_seconds 271.95 # Real time elapsed on the host +sim_insts 128304418 # Number of instructions simulated +sim_ops 247333117 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2891776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9026304 # Number of bytes read from this memory -system.physmem.bytes_read::total 12701440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8120576 # Number of bytes written to this memory -system.physmem.bytes_written::total 8120576 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44536 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8961408 # Number of bytes read from this memory +system.physmem.bytes_read::total 12677312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8105792 # Number of bytes written to this memory +system.physmem.bytes_written::total 8105792 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 45184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141036 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198460 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126884 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126884 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 549474 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140022 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198083 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126653 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126653 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 556523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1740065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2448548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1565462 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1565462 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1565462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 549474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1724626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2439753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1559963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1559963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1559963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 556523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1740065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4014010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198460 # Total number of read requests seen -system.physmem.writeReqs 126884 # Total number of write requests seen -system.physmem.cpureqs 326965 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 12701440 # Total number of bytes read from memory -system.physmem.bytesWritten 8120576 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12701440 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8120576 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 110 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1615 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12473 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 12592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12254 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12740 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12648 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7793 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7533 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7699 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7988 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7739 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 8103 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7898 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7933 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8107 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8130 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 158530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1724626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3999716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198083 # Total number of read requests seen +system.physmem.writeReqs 126653 # Total number of write requests seen +system.physmem.cpureqs 326336 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 12677312 # Total number of bytes read from memory +system.physmem.bytesWritten 8105792 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 12677312 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 8105792 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1597 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 12388 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13064 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12742 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 12822 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12061 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12170 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 11780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 11808 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 12169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12047 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7920 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8110 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8533 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 8387 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8388 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7744 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7959 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7196 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7383 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7714 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7959 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7876 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry -system.physmem.totGap 5187335842500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry +system.physmem.totGap 5196144706500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198460 # Categorize read packet sizes +system.physmem.readPktSize::6 198083 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 126884 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 155340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8720 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2004 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126653 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 154572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1095 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -132,92 +136,300 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.totQLat 4133329999 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7970683749 # Sum of mem lat for all requests -system.physmem.totBusLat 991750000 # Total cycles spent in databus access -system.physmem.totBankLat 2845603750 # Total cycles spent in bank access -system.physmem.avgQLat 20838.57 # Average queueing delay per request -system.physmem.avgBankLat 14346.38 # Average bank access latency per request +system.physmem.wrQLenPdf::0 4307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 45242 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 458.910923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.789921 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1568.289191 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 18577 41.06% 41.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 7110 15.72% 56.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4218 9.32% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2889 6.39% 72.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2001 4.42% 76.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1601 3.54% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1275 2.82% 83.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 961 2.12% 85.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 799 1.77% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 633 1.40% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 499 1.10% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 460 1.02% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 337 0.74% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 345 0.76% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 215 0.48% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 394 0.87% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 170 0.38% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 159 0.35% 94.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 128 0.28% 94.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 109 0.24% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 88 0.19% 94.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 127 0.28% 95.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 644 1.42% 96.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 160 0.35% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 109 0.24% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 90 0.20% 97.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 61 0.13% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 44 0.10% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 17 0.04% 97.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 21 0.05% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 12 0.03% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 37 0.08% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 16 0.04% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 11 0.02% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 9 0.02% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 7 0.02% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 9 0.02% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 6 0.01% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 3 0.01% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.01% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.00% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 5 0.01% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 3 0.01% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 2 0.00% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.00% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.01% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 3 0.01% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 1 0.00% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.00% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 11 0.02% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 2 0.00% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 1 0.00% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 3 0.01% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 14 0.03% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 2 0.00% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 3 0.01% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 4 0.01% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 2 0.00% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 2 0.00% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 1 0.00% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 2 0.00% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 2 0.00% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 1 0.00% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 2 0.00% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 4 0.01% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 12 0.03% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 2 0.00% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 1 0.00% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 7 0.02% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 2 0.00% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 340 0.75% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 7 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 8 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 10 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 237 0.52% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 13 0.03% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 17 0.04% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17283 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17600-17603 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17859 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 45242 # Bytes accessed per row activation +system.physmem.totQLat 3435518998 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7067756498 # Sum of mem lat for all requests +system.physmem.totBusLat 990065000 # Total cycles spent in databus access +system.physmem.totBankLat 2642172500 # Total cycles spent in bank access +system.physmem.avgQLat 17349.97 # Average queueing delay per request +system.physmem.avgBankLat 13343.43 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40184.94 # Average memory access latency -system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 35693.40 # Average memory access latency +system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 12.90 # Average write queue length over time -system.physmem.readRowHits 174211 # Number of row buffer hits during reads -system.physmem.writeRowHits 94671 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.61 # Row buffer hit rate for writes -system.physmem.avgGap 15944157.08 # Average gap between requests -system.iocache.replacements 47504 # number of replacements -system.iocache.tagsinuse 0.157150 # Cycle average of tags in use +system.physmem.avgWrQLen 9.35 # Average write queue length over time +system.physmem.readRowHits 181015 # Number of row buffer hits during reads +system.physmem.writeRowHits 98394 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.69 # Row buffer hit rate for writes +system.physmem.avgGap 16001135.40 # Average gap between requests +system.membus.throughput 4358895 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 623371 # Transaction distribution +system.membus.trans_dist::ReadResp 623371 # Transaction distribution +system.membus.trans_dist::WriteReq 13727 # Transaction distribution +system.membus.trans_dist::WriteResp 13727 # Transaction distribution +system.membus.trans_dist::Writeback 126653 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2147 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1615 # Transaction distribution +system.membus.trans_dist::ReadExReq 159120 # Transaction distribution +system.membus.trans_dist::ReadExResp 159120 # Transaction distribution +system.membus.trans_dist::MessageReq 1656 # Transaction distribution +system.membus.trans_dist::MessageResp 1656 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580408 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139407 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 139407 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 529581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 480118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1723127 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14904512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16571083 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5878592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5878592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 20783104 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22456299 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22456299 # Total data (bytes) +system.membus.snoop_data_through_bus 193152 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1348670998 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 256617500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 359320000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3312000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 2607874799 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer4.occupancy 428809000 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.replacements 47501 # number of replacements +system.iocache.tagsinuse 0.169264 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47520 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47517 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5044705088000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.157150 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.009822 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.009822 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses -system.iocache.ReadReq_misses::total 837 # number of ReadReq misses +system.iocache.warmup_cycle 5049524013000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.169264 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.010579 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.010579 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 834 # number of ReadReq misses +system.iocache.ReadReq_misses::total 834 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47557 # number of demand (read+write) misses -system.iocache.demand_misses::total 47557 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47557 # number of overall misses -system.iocache.overall_misses::total 47557 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139731143 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 139731143 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10765565415 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10765565415 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10905296558 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10905296558 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10905296558 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10905296558 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47554 # number of demand (read+write) misses +system.iocache.demand_misses::total 47554 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47554 # number of overall misses +system.iocache.overall_misses::total 47554 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142703185 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 142703185 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10862337325 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10862337325 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11005040510 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11005040510 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11005040510 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11005040510 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 834 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 834 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47557 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47557 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47557 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47557 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47554 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47554 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47554 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47554 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -226,40 +438,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166942.823178 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 166942.823178 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 230427.341931 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 230427.341931 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 229310.018672 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 229310.018672 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 229310.018672 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 229310.018672 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 177808 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171106.936451 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 171106.936451 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 232498.658497 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 232498.658497 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 231421.973125 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 231421.973125 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 174194 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16153 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16040 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.007739 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.859975 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46669 # number of writebacks system.iocache.writebacks::total 46669 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 834 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 834 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47557 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47557 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47557 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47557 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96185423 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 96185423 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8334760316 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8334760316 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8430945739 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8430945739 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8430945739 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8430945739 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47554 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47554 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47554 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47554 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99319185 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 99319185 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8432090325 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8432090325 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8531409510 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8531409510 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -268,14 +480,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114916.873357 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 114916.873357 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 178398.123202 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 178398.123202 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 177280.857476 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 177280.857476 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119087.751799 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 119087.751799 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 180481.385381 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 180481.385381 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -289,75 +501,217 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10374671812 # number of cpu cycles simulated +system.iobus.throughput 631272 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 230083 # Transaction distribution +system.iobus.trans_dist::ReadResp 230083 # Transaction distribution +system.iobus.trans_dist::WriteReq 57530 # Transaction distribution +system.iobus.trans_dist::WriteResp 57530 # Transaction distribution +system.iobus.trans_dist::MessageReq 1656 # Transaction distribution +system.iobus.trans_dist::MessageResp 1656 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 480118 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95108 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 578538 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 246342 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 3027216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3280182 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3280182 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3949664 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 424330510 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 469308000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 52196000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.numCycles 10392289540 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128315489 # Number of instructions committed -system.cpu.committedOps 247353048 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232087369 # Number of integer alu accesses +system.cpu.committedInsts 128304418 # Number of instructions committed +system.cpu.committedOps 247333117 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232067207 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2299349 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23166071 # number of instructions that are conditional controls -system.cpu.num_int_insts 232087369 # number of integer instructions +system.cpu.num_func_calls 2300061 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23160261 # number of instructions that are conditional controls +system.cpu.num_int_insts 232067207 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567244076 # number of times the integer registers were read -system.cpu.num_int_register_writes 293343891 # number of times the integer registers were written +system.cpu.num_int_register_reads 567198543 # number of times the integer registers were read +system.cpu.num_int_register_writes 293301890 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22240299 # number of memory refs -system.cpu.num_load_insts 13876403 # Number of load instructions -system.cpu.num_store_insts 8363896 # Number of store instructions -system.cpu.num_idle_cycles 9773542516.998116 # Number of idle cycles -system.cpu.num_busy_cycles 601129295.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057942 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942058 # Percentage of idle cycles +system.cpu.num_mem_refs 22245318 # number of memory refs +system.cpu.num_load_insts 13878816 # Number of load instructions +system.cpu.num_store_insts 8366502 # Number of store instructions +system.cpu.num_idle_cycles 9785692797.998116 # Number of idle cycles +system.cpu.num_busy_cycles 606596742.001883 # Number of busy cycles +system.cpu.not_idle_fraction 0.058370 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.941630 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790572 # number of replacements -system.cpu.icache.tagsinuse 510.408986 # Cycle average of tags in use -system.cpu.icache.total_refs 144555062 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791084 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.730357 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 160005789000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.408986 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996893 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996893 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144555062 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144555062 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144555062 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144555062 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144555062 # number of overall hits -system.cpu.icache.overall_hits::total 144555062 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791091 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791091 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791091 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791091 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791091 # number of overall misses -system.cpu.icache.overall_misses::total 791091 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10944017000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10944017000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10944017000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10944017000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10944017000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10944017000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145346153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145346153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145346153 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145346153 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145346153 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145346153 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005443 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005443 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005443 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005443 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005443 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005443 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.081035 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13834.081035 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.081035 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13834.081035 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.081035 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13834.081035 # average overall miss latency +system.cpu.icache.replacements 791404 # number of replacements +system.cpu.icache.tagsinuse 510.366672 # Cycle average of tags in use +system.cpu.icache.total_refs 144533937 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791916 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.511702 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 161113577000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.366672 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996810 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996810 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144533937 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144533937 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144533937 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144533937 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144533937 # number of overall hits +system.cpu.icache.overall_hits::total 144533937 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791923 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791923 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791923 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791923 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791923 # number of overall misses +system.cpu.icache.overall_misses::total 791923 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11177158500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11177158500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11177158500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11177158500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11177158500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11177158500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145325860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145325860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145325860 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145325860 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145325860 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145325860 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14113.946053 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14113.946053 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14113.946053 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14113.946053 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14113.946053 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14113.946053 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,80 +720,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791091 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791091 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791091 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791091 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791091 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791091 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9361835000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9361835000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9361835000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9361835000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9361835000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9361835000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005443 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005443 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005443 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11834.081035 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11834.081035 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11834.081035 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11834.081035 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11834.081035 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11834.081035 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791923 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791923 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791923 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791923 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791923 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791923 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9593312500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9593312500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9593312500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9593312500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9593312500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9593312500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12113.946053 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12113.946053 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12113.946053 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12113.946053 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12113.946053 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12113.946053 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3538 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.071073 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7817 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3549 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.202592 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5161021529000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.071073 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191942 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191942 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7819 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7819 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3530 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.075423 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7811 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3541 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.205874 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5166918586000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.075423 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192214 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.192214 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7833 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7833 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7821 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7821 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7821 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7821 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4399 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4399 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4399 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4399 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4399 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4399 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43289000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43289000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43289000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 43289000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43289000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 43289000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12218 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12218 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7835 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7835 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7835 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7835 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4388 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4388 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4388 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4388 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4388 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4388 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43163000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43163000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43163000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 43163000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43163000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 43163000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12220 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12220 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12220 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12220 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.360043 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.360043 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.359984 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.359984 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.359984 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.359984 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9840.645601 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9840.645601 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9840.645601 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9840.645601 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9840.645601 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9840.645601 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.359054 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.359054 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358995 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.358995 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358995 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.358995 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9836.599818 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9836.599818 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9836.599818 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9836.599818 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9836.599818 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9836.599818 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,78 +802,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 650 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 650 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4399 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4399 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4399 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4399 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4399 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4399 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34491000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34491000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34491000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34491000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34491000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34491000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.360043 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.360043 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.359984 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.359984 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.359984 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.359984 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7840.645601 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7840.645601 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7840.645601 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 619 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 619 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4388 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4388 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4388 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4388 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4388 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4388 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34387000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34387000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34387000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34387000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34387000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34387000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.359054 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.359054 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358995 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358995 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358995 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358995 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7836.599818 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7836.599818 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7836.599818 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7602 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.053533 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13277 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7616 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.743304 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5155312372000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053533 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315846 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315846 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13278 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13278 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13278 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13278 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13278 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13278 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8808 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8808 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8808 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8808 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8808 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8808 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 93210000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 93210000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 93210000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 93210000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 93210000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 93210000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22086 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22086 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22086 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22086 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22086 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22086 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398805 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398805 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398805 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398805 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398805 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398805 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10582.425068 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10582.425068 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10582.425068 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10582.425068 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10582.425068 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10582.425068 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7412 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.056524 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13351 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7427 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.797630 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5162997491000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.056524 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316033 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.316033 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13351 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13351 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13351 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13351 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13351 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13351 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8618 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8618 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8618 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8618 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8618 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8618 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 90576000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 90576000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 90576000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 90576000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 90576000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 90576000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21969 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21969 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21969 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21969 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21969 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21969 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392280 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392280 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392280 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392280 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392280 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392280 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10510.095150 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10510.095150 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10510.095150 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10510.095150 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10510.095150 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10510.095150 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,90 +882,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2984 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2984 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8808 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8808 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8808 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8808 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8808 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8808 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 75594000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 75594000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 75594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 75594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 75594000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 75594000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398805 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398805 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398805 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8582.425068 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8582.425068 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8582.425068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2749 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2749 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8618 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8618 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8618 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8618 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8618 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8618 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 73340000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 73340000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 73340000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 73340000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 73340000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 73340000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392280 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392280 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392280 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8510.095150 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8510.095150 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8510.095150 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1620743 # number of replacements -system.cpu.dcache.tagsinuse 511.997667 # Cycle average of tags in use -system.cpu.dcache.total_refs 20031616 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621255 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.355623 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997667 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11991279 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11991279 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8038109 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8038109 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20029388 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20029388 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20029388 # number of overall hits -system.cpu.dcache.overall_hits::total 20029388 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1307954 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1307954 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315546 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315546 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1623500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1623500 # number of overall misses -system.cpu.dcache.overall_misses::total 1623500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18389416000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18389416000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8586143000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8586143000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26975559000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26975559000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26975559000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26975559000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13299233 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13299233 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8353655 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8353655 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21652888 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21652888 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21652888 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21652888 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098348 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098348 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037773 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037773 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074978 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074978 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074978 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074978 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14059.680998 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14059.680998 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27210.432076 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27210.432076 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16615.681552 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16615.681552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16615.681552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16615.681552 # average overall miss latency +system.cpu.dcache.replacements 1622441 # number of replacements +system.cpu.dcache.tagsinuse 511.992388 # Cycle average of tags in use +system.cpu.dcache.total_refs 20034872 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622953 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.344703 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48929000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.992388 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11992680 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11992680 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8039994 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8039994 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20032674 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20032674 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20032674 # number of overall hits +system.cpu.dcache.overall_hits::total 20032674 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308966 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308966 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316237 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316237 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1625203 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1625203 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1625203 # number of overall misses +system.cpu.dcache.overall_misses::total 1625203 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18848048000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18848048000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10644655000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10644655000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29492703000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29492703000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29492703000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29492703000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13301646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13301646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8356231 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8356231 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21657877 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21657877 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21657877 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21657877 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098406 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098406 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037844 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037844 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.075040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.188367 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.188367 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33660.371810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33660.371810 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18147.088702 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18147.088702 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18147.088702 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18147.088702 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -620,46 +974,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1538215 # number of writebacks -system.cpu.dcache.writebacks::total 1538215 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1307954 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1307954 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315546 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315546 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1623500 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1623500 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1623500 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1623500 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15773508000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15773508000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7955051000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7955051000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23728559000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23728559000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23728559000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23728559000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94200596500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94200596500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2522793500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2522793500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96723390000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96723390000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098348 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098348 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037773 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037773 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074978 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074978 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074978 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074978 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12059.680998 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12059.680998 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25210.432076 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25210.432076 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14615.681552 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14615.681552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14615.681552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14615.681552 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1539801 # number of writebacks +system.cpu.dcache.writebacks::total 1539801 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308966 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308966 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316237 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 316237 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1625203 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1625203 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1625203 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1625203 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16230116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16230116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10012181000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10012181000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26242297000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26242297000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26242297000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26242297000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94201595500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94201595500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2525692000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2525692000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96727287500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96727287500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098406 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098406 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075040 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.075040 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075040 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.075040 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12399.188367 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12399.188367 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31660.371810 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31660.371810 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16147.088702 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16147.088702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16147.088702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16147.088702 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -667,127 +1021,175 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 87004 # number of replacements -system.cpu.l2cache.tagsinuse 64771.472210 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3487444 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 151687 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.991054 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 49236259 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2696119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2695598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13727 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13727 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1543169 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 360759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314063 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1583833 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5979450 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 7815 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 17592 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7588690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50682240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 204056779 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 219328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 574336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 255532683 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 255511115 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 327616 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3834241500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 505500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1187884500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3023860000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 6582000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 12927000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.l2cache.replacements 86618 # number of replacements +system.cpu.l2cache.tagsinuse 64735.286295 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3491811 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 151264 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.084217 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50378.956222 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3347.055983 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11045.319419 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.768722 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 49971.529408 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.027392 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.141401 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3486.795305 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11276.792789 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.762505 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.051072 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.168538 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.988334 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6442 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2817 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 778194 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1278591 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2066044 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1541849 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1541849 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 308 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 308 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199895 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199895 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6442 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2817 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 778194 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1478486 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2265939 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6442 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2817 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 778194 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1478486 # number of overall hits -system.cpu.l2cache.overall_hits::total 2265939 # number of overall hits +system.cpu.l2cache.occ_percent::cpu.inst 0.053204 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.172070 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.987782 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6224 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2803 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779038 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1279905 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2067970 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1543169 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1543169 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 330 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 330 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 201356 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 201356 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6224 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2803 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 779038 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1481261 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2269326 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6224 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2803 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779038 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1481261 # number of overall hits +system.cpu.l2cache.overall_hits::total 2269326 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12884 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28512 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41401 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1385 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1385 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113419 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113419 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12872 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28269 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41147 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1336 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1336 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 112679 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 112679 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12884 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141931 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154820 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12872 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140948 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153826 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12884 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141931 # number of overall misses -system.cpu.l2cache.overall_misses::total 154820 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 788791000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1678791500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2467927500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15947000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 15947000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5604900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5604900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 788791000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7283691500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8072827500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 788791000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7283691500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8072827500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6442 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2822 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791078 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307103 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2107445 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1541849 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1541849 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1693 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1693 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313314 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313314 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6442 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2822 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791078 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1620417 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2420759 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6442 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2822 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791078 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1620417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2420759 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001772 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016287 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021813 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019645 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.818074 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818074 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361998 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.361998 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001772 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016287 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087589 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063955 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001772 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016287 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087589 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61222.524061 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58880.173260 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 59610.335499 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11514.079422 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11514.079422 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49417.646073 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49417.646073 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61222.524061 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51318.538586 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52143.311588 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61222.524061 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51318.538586 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52143.311588 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 12872 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 140948 # number of overall misses +system.cpu.l2cache.overall_misses::total 153826 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1010996500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2121306500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3132781000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15904000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 15904000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7647596500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7647596500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1010996500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9768903000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10780377500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1010996500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9768903000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10780377500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6225 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2808 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791910 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1308174 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2109117 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1543169 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1543169 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1666 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1666 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314035 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314035 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6225 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2808 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791910 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1622209 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2423152 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6225 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2808 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791910 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1622209 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2423152 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000161 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016254 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021610 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019509 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.801921 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.801921 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358810 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.358810 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000161 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016254 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.086886 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063482 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000161 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016254 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.086886 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063482 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77800 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78542.301119 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75040.026177 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76136.316135 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11904.191617 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11904.191617 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67870.645817 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67870.645817 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77800 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78542.301119 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69308.560604 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70081.634444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77800 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78542.301119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69308.560604 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70081.634444 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -796,78 +1198,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80215 # number of writebacks -system.cpu.l2cache.writebacks::total 80215 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 79984 # number of writebacks +system.cpu.l2cache.writebacks::total 79984 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12884 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28512 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41401 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1385 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1385 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113419 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 113419 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12872 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41147 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1336 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1336 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112679 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 112679 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12884 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141931 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154820 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12872 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140948 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 153826 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12884 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141931 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154820 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281255 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 628701625 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1324271586 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1953254466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14803865 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14803865 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4210880830 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4210880830 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 628701625 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5535152416 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6164135296 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 628701625 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5535152416 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6164135296 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86642612000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86642612000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2356974000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2356974000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88999586000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88999586000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001772 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016287 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021813 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019645 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818074 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818074 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361998 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361998 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001772 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016287 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063955 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001772 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016287 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48797.083592 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46446.113426 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47178.919978 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10688.711191 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10688.711191 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37126.767385 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37126.767385 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48797.083592 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38998.896760 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39814.851415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48797.083592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38998.896760 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39814.851415 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140948 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 153826 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 851715758 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1771468289 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2623586547 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14290818 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14290818 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6265697836 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6265697836 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851715758 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8037166125 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8889284383 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851715758 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8037166125 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8889284383 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86643520000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86643520000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2359628500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2359628500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89003148500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89003148500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021610 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019509 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.801921 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.801921 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358810 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358810 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063482 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063482 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66168.098042 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62664.695921 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63761.308163 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10696.720060 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10696.720060 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55606.615572 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55606.615572 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index ac7e3035a..cf36dbc01 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -1,188 +1,48 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.200409 # Number of seconds simulated -sim_ticks 200409293000 # Number of ticks simulated -final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 200409284500 # Number of ticks simulated +final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 11931696 # Simulator instruction rate (inst/s) -host_op_rate 11931689 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4547176905 # Simulator tick rate (ticks/s) -host_mem_usage 472520 # Number of bytes of host memory used -host_seconds 44.07 # Real time elapsed on the host -sim_insts 525869186 # Number of instructions simulated -sim_ops 525869186 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 27826180 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 51169128 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 160043872 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 81048564 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 81048564 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 16606324 # Number of bytes written to this memory +host_inst_rate 10833540 # Simulator instruction rate (inst/s) +host_op_rate 10833535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4145057481 # Simulator tick rate (ticks/s) +host_mem_usage 475668 # Number of bytes of host memory used +host_seconds 48.35 # Real time elapsed on the host +sim_insts 523790075 # Number of instructions simulated +sim_ops 523790075 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 81046720 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 27826276 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 166133492 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 81046720 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 81046720 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 16606680 # Number of bytes written to this memory testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 16607226 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 20262141 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 3842564 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 2132029 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 26236734 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 2258349 # Number of write requests responded to by this memory +testsys.physmem.bytes_written::total 16607582 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 20261680 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 3842559 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 26490075 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 2258392 # Number of write requests responded to by this memory testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 2258380 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 404415198 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 138846755 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 255323130 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 798585084 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 404415198 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 404415198 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 82862046 # Write bandwidth from this memory (bytes/s) +testsys.physmem.num_writes::total 2258423 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 404406014 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 138847240 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 285717781 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 828971035 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 404406014 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 404406014 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 82863826 # Write bandwidth from this memory (bytes/s) testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 82866547 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 404415198 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 221708801 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 255327631 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 881451630 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.readReqs 0 # Total number of read requests seen -testsys.physmem.writeReqs 0 # Total number of write requests seen -testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady -testsys.physmem.bytesRead 0 # Total number of bytes read from memory -testsys.physmem.bytesWritten 0 # Total number of bytes written to memory -testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() -testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -testsys.physmem.totGap 0 # Total gap between requests -testsys.physmem.readPktSize::0 0 # Categorize read packet sizes -testsys.physmem.readPktSize::1 0 # Categorize read packet sizes -testsys.physmem.readPktSize::2 0 # Categorize read packet sizes -testsys.physmem.readPktSize::3 0 # Categorize read packet sizes -testsys.physmem.readPktSize::4 0 # Categorize read packet sizes -testsys.physmem.readPktSize::5 0 # Categorize read packet sizes -testsys.physmem.readPktSize::6 0 # Categorize read packet sizes -testsys.physmem.writePktSize::0 0 # Categorize write packet sizes -testsys.physmem.writePktSize::1 0 # Categorize write packet sizes -testsys.physmem.writePktSize::2 0 # Categorize write packet sizes -testsys.physmem.writePktSize::3 0 # Categorize write packet sizes -testsys.physmem.writePktSize::4 0 # Categorize write packet sizes -testsys.physmem.writePktSize::5 0 # Categorize write packet sizes -testsys.physmem.writePktSize::6 0 # Categorize write packet sizes -testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -testsys.physmem.totQLat 0 # Total cycles spent in queuing delays -testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests -testsys.physmem.totBusLat 0 # Total cycles spent in databus access -testsys.physmem.totBankLat 0 # Total cycles spent in bank access -testsys.physmem.avgQLat nan # Average queueing delay per request -testsys.physmem.avgBankLat nan # Average bank access latency per request -testsys.physmem.avgBusLat nan # Average bus latency per request -testsys.physmem.avgMemAccLat nan # Average memory access latency -testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s -testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s -testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -testsys.physmem.busUtil 0.00 # Data bus utilization in percentage -testsys.physmem.avgRdQLen 0.00 # Average read queue length over time -testsys.physmem.avgWrQLen 0.00 # Average write queue length over time -testsys.physmem.readRowHits 0 # Number of row buffer hits during reads -testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes -testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads -testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes -testsys.physmem.avgGap nan # Average gap between requests +testsys.physmem.bw_write::total 82868326 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 404406014 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 221711065 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 285722281 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 911839361 # Total bandwidth to/from this memory (bytes/s) +testsys.membus.throughput 916540501 # Throughput (bytes/s) +testsys.membus.data_through_bus 183683226 # Total data (bytes) +testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes) testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -199,22 +59,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 3916928 # DTB read hits +testsys.cpu.dtb.read_hits 3916918 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.read_acv 80 # DTB read access violations testsys.cpu.dtb.read_accesses 225414 # DTB read accesses -testsys.cpu.dtb.write_hits 2316846 # DTB write hits +testsys.cpu.dtb.write_hits 2316885 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.dtb.write_acv 81 # DTB write access violations testsys.cpu.dtb.write_accesses 109988 # DTB write accesses -testsys.cpu.dtb.data_hits 6233774 # DTB hits +testsys.cpu.dtb.data_hits 6233803 # DTB hits testsys.cpu.dtb.data_misses 3815 # DTB misses testsys.cpu.dtb.data_acv 161 # DTB access violations testsys.cpu.dtb.data_accesses 335402 # DTB accesses -testsys.cpu.itb.fetch_hits 4052272 # ITB hits +testsys.cpu.itb.fetch_hits 4052211 # ITB hits testsys.cpu.itb.fetch_misses 1497 # ITB misses testsys.cpu.itb.fetch_acv 69 # ITB acv -testsys.cpu.itb.fetch_accesses 4053769 # ITB accesses +testsys.cpu.itb.fetch_accesses 4053708 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -227,51 +87,51 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 400815936 # number of cpu cycles simulated +testsys.cpu.numCycles 400804755 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 20258165 # Number of instructions committed -testsys.cpu.committedOps 20258165 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 18837392 # Number of integer alu accesses -testsys.cpu.num_fp_alu_accesses 17313 # Number of float alu accesses -testsys.cpu.num_func_calls 1221260 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 1442190 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 18837392 # number of integer instructions -testsys.cpu.num_fp_insts 17313 # number of float instructions -testsys.cpu.num_int_register_reads 24787608 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 14694255 # number of times the integer registers were written -testsys.cpu.num_fp_register_reads 11133 # number of times the floating registers were read -testsys.cpu.num_fp_register_writes 10789 # number of times the floating registers were written -testsys.cpu.num_mem_refs 6263009 # number of memory refs -testsys.cpu.num_load_insts 3944038 # Number of load instructions -testsys.cpu.num_store_insts 2318971 # Number of store instructions -testsys.cpu.num_idle_cycles 380552362.972989 # Number of idle cycles -testsys.cpu.num_busy_cycles 20263573.027011 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.050556 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.949444 # Percentage of idle cycles +testsys.cpu.committedInsts 20257704 # Number of instructions committed +testsys.cpu.committedOps 20257704 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 18837017 # Number of integer alu accesses +testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses +testsys.cpu.num_func_calls 1221180 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 1442148 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 18837017 # number of integer instructions +testsys.cpu.num_fp_insts 17380 # number of float instructions +testsys.cpu.num_int_register_reads 24787248 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 14693875 # number of times the integer registers were written +testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read +testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written +testsys.cpu.num_mem_refs 6263046 # number of memory refs +testsys.cpu.num_load_insts 3944033 # Number of load instructions +testsys.cpu.num_store_insts 2319013 # Number of store instructions +testsys.cpu.num_idle_cycles 380542207.362158 # Number of idle cycles +testsys.cpu.num_busy_cycles 20262547.637842 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.050555 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.949445 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 19598 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 153677 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 62790 42.68% 42.68% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 19620 13.34% 56.01% # number of times we switched to this ipl +testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed +testsys.cpu.kern.inst.hwrei 153667 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 64514 43.85% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 147129 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 62784 43.18% 43.18% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 19620 13.49% 56.67% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::22 205 0.14% 56.81% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 62791 43.19% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 145400 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 194352160500 96.98% 96.98% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 1588908500 0.79% 97.77% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_count::31 64509 43.85% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 147118 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 194346512500 96.98% 96.98% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 4458302500 2.22% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 200408186500 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 4458282500 2.22% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 200402596000 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.973293 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.988248 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::31 0.973275 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.988241 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed @@ -294,30 +154,30 @@ testsys.cpu.kern.syscall::104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.kern.syscall::total 83 # number of syscalls executed -testsys.cpu.kern.callpal::swpctx 437 0.34% 0.34% # number of callpals executed +testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed -testsys.cpu.kern.callpal::swpipl 106841 83.26% 83.62% # number of callpals executed +testsys.cpu.kern.callpal::swpipl 106830 83.26% 83.62% # number of callpals executed testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 128317 # number of callpals executed -testsys.cpu.kern.mode_switch::kernel 1281 # number of protection mode switches -testsys.cpu.kern.mode_switch::user 703 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 19627 # number of protection mode switches +testsys.cpu.kern.callpal::total 128307 # number of callpals executed +testsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches +testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches testsys.cpu.kern.mode_good::kernel 707 -testsys.cpu.kern.mode_good::user 703 -testsys.cpu.kern.mode_good::idle 4 -testsys.cpu.kern.mode_switch_good::kernel 0.551913 # fraction of useful protection mode switches +testsys.cpu.kern.mode_good::user 702 +testsys.cpu.kern.mode_good::idle 5 +testsys.cpu.kern.mode_switch_good::kernel 0.552344 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::idle 0.000204 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks::kernel 1002766500 60.53% 60.53% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::user 533073000 32.18% 92.70% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::idle 120928500 7.30% 100.00% # number of ticks spent at the given mode -testsys.cpu.kern.swap_context 437 # number of times the context was actually changed +testsys.cpu.kern.mode_ticks::kernel 994603000 60.01% 60.01% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::user 533068000 32.16% 92.17% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::idle 129740500 7.83% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted testsys.tsunami.ethernet.rxBytes 798 # Bytes Received testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted @@ -328,9 +188,9 @@ testsys.tsunami.ethernet.txTcpChecksums 2 # Nu testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -testsys.tsunami.ethernet.descDMAReads 2131994 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 2385801 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 51167856 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 57259224 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) testsys.tsunami.ethernet.totPackets 13 # Total Packets @@ -357,7 +217,7 @@ testsys.tsunami.ethernet.coalescedTxOk 0 # av testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 2131994 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 2385801 # total number of TxIdle written to ISR testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -365,180 +225,42 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 2132012 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.physmem.bytes_read::cpu.inst 76288612 # Number of bytes read from this memory -drivesys.physmem.bytes_read::cpu.data 26312880 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 51169134 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 153770626 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read::cpu.inst 76288612 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_inst_read::total 76288612 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written::cpu.data 14635456 # Number of bytes written to this memory +testsys.iobus.throughput 290423421 # Throughput (bytes/s) +testsys.iobus.data_through_bus 58203550 # Total data (bytes) +drivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory +drivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 57260526 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 159750390 # Number of bytes read from this memory +drivesys.physmem.bytes_inst_read::cpu.inst 76205572 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_inst_read::total 76205572 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_written::cpu.data 14619632 # Number of bytes written to this memory drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory -drivesys.physmem.bytes_written::total 14636520 # Number of bytes written to this memory -drivesys.physmem.num_reads::cpu.inst 19072153 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::cpu.data 3651006 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 2132030 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 24855189 # Number of read requests responded to by this memory -drivesys.physmem.num_writes::cpu.data 2026958 # Number of write requests responded to by this memory +drivesys.physmem.bytes_written::total 14620696 # Number of bytes written to this memory +drivesys.physmem.num_reads::cpu.inst 19051393 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::cpu.data 3647049 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 2385838 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 25084280 # Number of read requests responded to by this memory +drivesys.physmem.num_writes::cpu.data 2024776 # Number of write requests responded to by this memory drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory -drivesys.physmem.num_writes::total 2026995 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 380664044 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 131295708 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 255323160 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 767282912 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 380664044 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 380664044 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 73027831 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.num_writes::total 2024813 # Number of write requests responded to by this memory +drivesys.physmem.bw_read::cpu.inst 380249708 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 131153065 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 285717930 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 797120704 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 380249708 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 380249708 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 72948876 # Write bandwidth from this memory (bytes/s) drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 73033140 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 380664044 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 204323539 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 255328469 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 840316053 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.readReqs 0 # Total number of read requests seen -drivesys.physmem.writeReqs 0 # Total number of write requests seen -drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady -drivesys.physmem.bytesRead 0 # Total number of bytes read from memory -drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory -drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() -drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -drivesys.physmem.totGap 0 # Total gap between requests -drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes -drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes -drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays -drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests -drivesys.physmem.totBusLat 0 # Total cycles spent in databus access -drivesys.physmem.totBankLat 0 # Total cycles spent in bank access -drivesys.physmem.avgQLat nan # Average queueing delay per request -drivesys.physmem.avgBankLat nan # Average bank access latency per request -drivesys.physmem.avgBusLat nan # Average bus latency per request -drivesys.physmem.avgMemAccLat nan # Average memory access latency -drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s -drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s -drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage -drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time -drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time -drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads -drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes -drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads -drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes -drivesys.physmem.avgGap nan # Average gap between requests +drivesys.physmem.bw_write::total 72954185 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 380249708 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 204101941 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 285723240 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 870074889 # Total bandwidth to/from this memory (bytes/s) +drivesys.membus.throughput 874808223 # Throughput (bytes/s) +drivesys.membus.data_through_bus 175319690 # Total data (bytes) +drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes) drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -555,22 +277,22 @@ drivesys.cpu.dtb.fetch_hits 0 # IT drivesys.cpu.dtb.fetch_misses 0 # ITB misses drivesys.cpu.dtb.fetch_acv 0 # ITB acv drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses -drivesys.cpu.dtb.read_hits 3729326 # DTB read hits +drivesys.cpu.dtb.read_hits 3725273 # DTB read hits drivesys.cpu.dtb.read_misses 487 # DTB read misses drivesys.cpu.dtb.read_acv 30 # DTB read access violations drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses -drivesys.cpu.dtb.write_hits 2086333 # DTB write hits +drivesys.cpu.dtb.write_hits 2084079 # DTB write hits drivesys.cpu.dtb.write_misses 82 # DTB write misses drivesys.cpu.dtb.write_acv 10 # DTB write access violations drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses -drivesys.cpu.dtb.data_hits 5815659 # DTB hits +drivesys.cpu.dtb.data_hits 5809352 # DTB hits drivesys.cpu.dtb.data_misses 569 # DTB misses drivesys.cpu.dtb.data_acv 40 # DTB access violations drivesys.cpu.dtb.data_accesses 401230 # DTB accesses -drivesys.cpu.itb.fetch_hits 4201097 # ITB hits +drivesys.cpu.itb.fetch_hits 4197628 # ITB hits drivesys.cpu.itb.fetch_misses 194 # ITB misses drivesys.cpu.itb.fetch_acv 22 # ITB acv -drivesys.cpu.itb.fetch_accesses 4201291 # ITB accesses +drivesys.cpu.itb.fetch_accesses 4197822 # ITB accesses drivesys.cpu.itb.read_hits 0 # DTB read hits drivesys.cpu.itb.read_misses 0 # DTB read misses drivesys.cpu.itb.read_acv 0 # DTB read access violations @@ -583,51 +305,51 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 801619128 # number of cpu cycles simulated +drivesys.cpu.numCycles 801631448 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -drivesys.cpu.committedInsts 19071544 # Number of instructions committed -drivesys.cpu.committedOps 19071544 # Number of ops (including micro ops) committed -drivesys.cpu.num_int_alu_accesses 17759891 # Number of integer alu accesses +drivesys.cpu.committedInsts 19050784 # Number of instructions committed +drivesys.cpu.committedOps 19050784 # Number of ops (including micro ops) committed +drivesys.cpu.num_int_alu_accesses 17740632 # Number of integer alu accesses drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses -drivesys.cpu.num_func_calls 1266408 # number of times a function call or return occured -drivesys.cpu.num_conditional_control_insts 1266328 # number of instructions that are conditional controls -drivesys.cpu.num_int_insts 17759891 # number of integer instructions +drivesys.cpu.num_func_calls 1265024 # number of times a function call or return occured +drivesys.cpu.num_conditional_control_insts 1264985 # number of instructions that are conditional controls +drivesys.cpu.num_int_insts 17740632 # number of integer instructions drivesys.cpu.num_fp_insts 1412 # number of float instructions -drivesys.cpu.num_int_register_reads 23097438 # number of times the integer registers were read -drivesys.cpu.num_int_register_writes 13996340 # number of times the integer registers were written +drivesys.cpu.num_int_register_reads 23072330 # number of times the integer registers were read +drivesys.cpu.num_int_register_writes 13981107 # number of times the integer registers were written drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written -drivesys.cpu.num_mem_refs 5837119 # number of memory refs -drivesys.cpu.num_load_insts 3750273 # Number of load instructions -drivesys.cpu.num_store_insts 2086846 # Number of store instructions -drivesys.cpu.num_idle_cycles 782547188.298833 # Number of idle cycles -drivesys.cpu.num_busy_cycles 19071939.701167 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.023792 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.976208 # Percentage of idle cycles +drivesys.cpu.num_mem_refs 5830788 # number of memory refs +drivesys.cpu.num_load_insts 3746196 # Number of load instructions +drivesys.cpu.num_store_insts 2084592 # Number of store instructions +drivesys.cpu.num_idle_cycles 782579974.227931 # Number of idle cycles +drivesys.cpu.num_busy_cycles 19051473.772069 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.023766 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.976234 # Percentage of idle cycles drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed -drivesys.cpu.kern.inst.quiesce 19898 # number of quiesce instructions executed -drivesys.cpu.kern.inst.hwrei 143758 # number of hwrei instructions executed -drivesys.cpu.kern.ipl_count::0 60430 42.42% 42.42% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::21 19752 13.86% 56.28% # number of times we switched to this ipl +drivesys.cpu.kern.inst.quiesce 19876 # number of quiesce instructions executed +drivesys.cpu.kern.inst.hwrei 143591 # number of hwrei instructions executed +drivesys.cpu.kern.ipl_count::0 60359 42.42% 42.42% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::21 19727 13.86% 56.28% # number of times we switched to this ipl drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::31 62082 43.58% 100.00% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::total 142469 # number of times we switched to this ipl -drivesys.cpu.kern.ipl_good::0 60430 42.91% 42.91% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::21 19752 14.03% 56.94% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_count::31 62011 43.58% 100.00% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::total 142302 # number of times we switched to this ipl +drivesys.cpu.kern.ipl_good::0 60359 42.91% 42.91% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::21 19727 14.03% 56.94% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::31 60432 42.91% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::total 140819 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 197392680000 98.50% 98.50% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 799890500 0.40% 98.90% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_good::31 60360 42.91% 100.00% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::total 140651 # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_ticks::0 197399332500 98.50% 98.50% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 798910750 0.40% 98.90% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::31 2207804000 1.10% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 200404782000 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::31 2205211250 1.10% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 200407862000 # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::31 0.973422 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::total 0.988419 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::31 0.973376 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::total 0.988398 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed @@ -643,26 +365,26 @@ drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # nu drivesys.cpu.kern.syscall::total 22 # number of syscalls executed drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed -drivesys.cpu.kern.callpal::swpipl 102452 83.31% 83.37% # number of callpals executed +drivesys.cpu.kern.callpal::swpipl 102333 83.31% 83.37% # number of callpals executed drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed -drivesys.cpu.kern.callpal::rti 20062 16.31% 99.97% # number of callpals executed +drivesys.cpu.kern.callpal::rti 20038 16.31% 99.97% # number of callpals executed drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed -drivesys.cpu.kern.callpal::total 122978 # number of callpals executed +drivesys.cpu.kern.callpal::total 122835 # number of callpals executed drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches -drivesys.cpu.kern.mode_switch::user 139 # number of protection mode switches -drivesys.cpu.kern.mode_switch::idle 19920 # number of protection mode switches -drivesys.cpu.kern.mode_good::kernel 143 -drivesys.cpu.kern.mode_good::user 139 +drivesys.cpu.kern.mode_switch::user 140 # number of protection mode switches +drivesys.cpu.kern.mode_switch::idle 19896 # number of protection mode switches +drivesys.cpu.kern.mode_good::kernel 144 +drivesys.cpu.kern.mode_good::user 140 drivesys.cpu.kern.mode_good::idle 4 -drivesys.cpu.kern.mode_switch_good::kernel 0.668224 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::kernel 0.672897 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::total 0.014107 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_ticks::kernel 78132750 2.64% 2.64% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::user 319665750 10.79% 13.43% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::idle 2564974000 86.57% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_switch_good::total 0.014222 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_ticks::kernel 78134250 2.63% 2.63% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::user 319668250 10.78% 13.41% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::idle 2567942000 86.59% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received @@ -674,9 +396,9 @@ drivesys.tsunami.ethernet.txTcpChecksums 2 # Nu drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -drivesys.tsunami.ethernet.descDMAReads 2132001 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 2385809 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 51168024 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 57259416 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) drivesys.tsunami.ethernet.totPackets 13 # Total Packets @@ -701,9 +423,9 @@ drivesys.tsunami.ethernet.totalRxDesc 8 # to drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -drivesys.tsunami.ethernet.postedTxIdle 19750 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxIdle 19726 # number of TxIdle interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 2132001 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 2385809 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -711,192 +433,54 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 2132022 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 2385830 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +drivesys.iobus.throughput 290456573 # Throughput (bytes/s) +drivesys.iobus.data_through_bus 58210194 # Total data (bytes) ---------- End Simulation Statistics ---------- ---------- Begin Simulation Statistics ---------- sim_seconds 0.000407 # Number of seconds simulated -sim_ticks 407365500 # Number of ticks simulated -final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 407341500 # Number of ticks simulated +final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 6212406894 # Simulator instruction rate (inst/s) -host_op_rate 6210790807 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4809282801 # Simulator tick rate (ticks/s) -host_mem_usage 472520 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -sim_insts 525940622 # Number of instructions simulated -sim_ops 525940622 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 48760 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 103992 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 293888 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 141136 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 141136 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 27028 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 27028 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 35284 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 6744 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 4333 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 46361 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 3721 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 3721 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 346460365 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 119695949 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 255279350 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 721435664 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 346460365 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 346460365 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 66348279 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 66348279 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 346460365 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 186044228 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 255279350 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 787783943 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.readReqs 0 # Total number of read requests seen -testsys.physmem.writeReqs 0 # Total number of write requests seen -testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady -testsys.physmem.bytesRead 0 # Total number of bytes read from memory -testsys.physmem.bytesWritten 0 # Total number of bytes written to memory -testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() -testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -testsys.physmem.totGap 0 # Total gap between requests -testsys.physmem.readPktSize::0 0 # Categorize read packet sizes -testsys.physmem.readPktSize::1 0 # Categorize read packet sizes -testsys.physmem.readPktSize::2 0 # Categorize read packet sizes -testsys.physmem.readPktSize::3 0 # Categorize read packet sizes -testsys.physmem.readPktSize::4 0 # Categorize read packet sizes -testsys.physmem.readPktSize::5 0 # Categorize read packet sizes -testsys.physmem.readPktSize::6 0 # Categorize read packet sizes -testsys.physmem.writePktSize::0 0 # Categorize write packet sizes -testsys.physmem.writePktSize::1 0 # Categorize write packet sizes -testsys.physmem.writePktSize::2 0 # Categorize write packet sizes -testsys.physmem.writePktSize::3 0 # Categorize write packet sizes -testsys.physmem.writePktSize::4 0 # Categorize write packet sizes -testsys.physmem.writePktSize::5 0 # Categorize write packet sizes -testsys.physmem.writePktSize::6 0 # Categorize write packet sizes -testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -testsys.physmem.totQLat 0 # Total cycles spent in queuing delays -testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests -testsys.physmem.totBusLat 0 # Total cycles spent in databus access -testsys.physmem.totBankLat 0 # Total cycles spent in bank access -testsys.physmem.avgQLat nan # Average queueing delay per request -testsys.physmem.avgBankLat nan # Average bank access latency per request -testsys.physmem.avgBusLat nan # Average bus latency per request -testsys.physmem.avgMemAccLat nan # Average memory access latency -testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s -testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s -testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -testsys.physmem.busUtil 0.00 # Data bus utilization in percentage -testsys.physmem.avgRdQLen 0.00 # Average read queue length over time -testsys.physmem.avgWrQLen 0.00 # Average write queue length over time -testsys.physmem.readRowHits 0 # Number of row buffer hits during reads -testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes -testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads -testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes -testsys.physmem.avgGap nan # Average gap between requests +host_inst_rate 5619093232 # Simulator instruction rate (inst/s) +host_op_rate 5617709608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4367114686 # Simulator tick rate (ticks/s) +host_mem_usage 475668 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +sim_insts 523862353 # Number of instructions simulated +sim_ops 523862353 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 49936 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 116376 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 310816 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 144504 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 144504 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 27704 # Number of bytes written to this memory +testsys.physmem.bytes_written::total 27704 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 36126 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 6905 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 4849 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 47880 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 3814 # Number of write requests responded to by this memory +testsys.physmem.num_writes::total 3814 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 354749025 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 122590014 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 285696400 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 763035438 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 354749025 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 354749025 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 68011730 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::total 68011730 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 354749025 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s) +testsys.membus.throughput 835780297 # Throughput (bytes/s) +testsys.membus.data_through_bus 340448 # Total data (bytes) +testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes) testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -913,22 +497,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 6900 # DTB read hits +testsys.cpu.dtb.read_hits 7065 # DTB read hits testsys.cpu.dtb.read_misses 0 # DTB read misses testsys.cpu.dtb.read_acv 0 # DTB read access violations testsys.cpu.dtb.read_accesses 0 # DTB read accesses -testsys.cpu.dtb.write_hits 3839 # DTB write hits +testsys.cpu.dtb.write_hits 3935 # DTB write hits testsys.cpu.dtb.write_misses 0 # DTB write misses testsys.cpu.dtb.write_acv 0 # DTB write access violations testsys.cpu.dtb.write_accesses 0 # DTB write accesses -testsys.cpu.dtb.data_hits 10739 # DTB hits +testsys.cpu.dtb.data_hits 11000 # DTB hits testsys.cpu.dtb.data_misses 0 # DTB misses testsys.cpu.dtb.data_acv 0 # DTB access violations testsys.cpu.dtb.data_accesses 0 # DTB accesses -testsys.cpu.itb.fetch_hits 5847 # ITB hits +testsys.cpu.itb.fetch_hits 5992 # ITB hits testsys.cpu.itb.fetch_misses 0 # ITB misses testsys.cpu.itb.fetch_acv 0 # ITB acv -testsys.cpu.itb.fetch_accesses 5847 # ITB accesses +testsys.cpu.itb.fetch_accesses 5992 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -941,58 +525,58 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 799188 # number of cpu cycles simulated +testsys.cpu.numCycles 821016 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 35284 # Number of instructions committed -testsys.cpu.committedOps 35284 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 32710 # Number of integer alu accesses +testsys.cpu.committedInsts 36126 # Number of instructions committed +testsys.cpu.committedOps 36126 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 33492 # Number of integer alu accesses testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -testsys.cpu.num_func_calls 2330 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 2292 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 32710 # number of integer instructions +testsys.cpu.num_func_calls 2384 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 2346 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 33492 # number of integer instructions testsys.cpu.num_fp_insts 0 # number of float instructions -testsys.cpu.num_int_register_reads 42720 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 25860 # number of times the integer registers were written +testsys.cpu.num_int_register_reads 43747 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 26476 # number of times the integer registers were written testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written -testsys.cpu.num_mem_refs 10779 # number of memory refs -testsys.cpu.num_load_insts 6939 # Number of load instructions -testsys.cpu.num_store_insts 3840 # Number of store instructions -testsys.cpu.num_idle_cycles 764577.129267 # Number of idle cycles -testsys.cpu.num_busy_cycles 34610.870733 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.043308 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.956692 # Percentage of idle cycles +testsys.cpu.num_mem_refs 11041 # number of memory refs +testsys.cpu.num_load_insts 7105 # Number of load instructions +testsys.cpu.num_store_insts 3936 # Number of store instructions +testsys.cpu.num_idle_cycles 784609.171892 # Number of idle cycles +testsys.cpu.num_busy_cycles 36406.828108 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.044344 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.955656 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 288 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 120 41.81% 41.81% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 39 13.59% 55.40% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::22 1 0.35% 55.75% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 127 44.25% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 287 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 120 42.86% 42.86% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 39 13.93% 56.79% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::22 1 0.36% 57.14% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 120 42.86% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 280 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 387349500 96.94% 96.94% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 3159000 0.79% 97.73% # number of cycles we spent at this ipl +testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 397967000 96.95% 96.95% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.73% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 9042500 2.26% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 399594000 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 9258000 2.26% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 410508000 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.944882 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.975610 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.callpal::swpipl 207 83.47% 83.47% # number of callpals executed -testsys.cpu.kern.callpal::rdps 1 0.40% 83.87% # number of callpals executed -testsys.cpu.kern.callpal::rti 40 16.13% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 248 # number of callpals executed +testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed +testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed +testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed +testsys.cpu.kern.callpal::total 254 # number of callpals executed testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 40 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches testsys.cpu.kern.mode_good::kernel 0 testsys.cpu.kern.mode_good::user 0 testsys.cpu.kern.mode_good::idle 0 @@ -1004,9 +588,9 @@ testsys.cpu.kern.mode_ticks::kernel 0 # nu testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode testsys.cpu.kern.swap_context 0 # number of times the context was actually changed -testsys.tsunami.ethernet.descDMAReads 4333 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 103992 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 116376 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1023,9 +607,9 @@ testsys.tsunami.ethernet.totalRxDesc 0 # to testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 39 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 4333 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 4849 # total number of TxIdle written to ISR testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -1033,177 +617,39 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 4333 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +testsys.iobus.throughput 290429529 # Throughput (bytes/s) +testsys.iobus.data_through_bus 118304 # Total data (bytes) drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 104016 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 298576 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 116400 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 310960 # Number of bytes read from this memory drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 4334 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 47395 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 4850 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 47911 # Number of read requests responded to by this memory drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 354983424 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 122622068 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 255338265 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 732943757 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 354983424 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 354983424 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 67968446 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 67968446 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 354983424 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 190590514 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 255338265 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 800912203 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.readReqs 0 # Total number of read requests seen -drivesys.physmem.writeReqs 0 # Total number of write requests seen -drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady -drivesys.physmem.bytesRead 0 # Total number of bytes read from memory -drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory -drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() -drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis -drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -drivesys.physmem.totGap 0 # Total gap between requests -drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes -drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes -drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes -drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays -drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests -drivesys.physmem.totBusLat 0 # Total cycles spent in databus access -drivesys.physmem.totBankLat 0 # Total cycles spent in bank access -drivesys.physmem.avgQLat nan # Average queueing delay per request -drivesys.physmem.avgBankLat nan # Average bank access latency per request -drivesys.physmem.avgBusLat nan # Average bus latency per request -drivesys.physmem.avgMemAccLat nan # Average memory access latency -drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s -drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s -drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage -drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time -drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time -drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads -drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes -drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads -drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes -drivesys.physmem.avgGap nan # Average gap between requests +drivesys.physmem.bw_read::cpu.inst 355004339 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 122629293 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 285755318 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 763388950 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 355004339 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 355004339 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 67972451 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::total 67972451 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 355004339 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s) +drivesys.membus.throughput 836094530 # Throughput (bytes/s) +drivesys.membus.data_through_bus 340576 # Total data (bytes) +drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes) drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -1248,7 +694,7 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 1624320 # number of cpu cycles simulated +drivesys.cpu.numCycles 1626240 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed drivesys.cpu.committedInsts 36152 # Number of instructions committed @@ -1266,10 +712,10 @@ drivesys.cpu.num_fp_register_writes 0 # nu drivesys.cpu.num_mem_refs 11043 # number of memory refs drivesys.cpu.num_load_insts 7109 # Number of load instructions drivesys.cpu.num_store_insts 3934 # Number of store instructions -drivesys.cpu.num_idle_cycles 1588282.082886 # Number of idle cycles -drivesys.cpu.num_busy_cycles 36037.917114 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.022186 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.977814 # Percentage of idle cycles +drivesys.cpu.num_idle_cycles 1590157.359061 # Number of idle cycles +drivesys.cpu.num_busy_cycles 36082.640939 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.022188 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.977812 # Percentage of idle cycles drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed @@ -1283,11 +729,11 @@ drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # nu drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 399809000 98.46% 98.46% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.85% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::0 400289000 98.46% 98.46% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 406080000 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 406560000 # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1311,9 +757,9 @@ drivesys.cpu.kern.mode_ticks::kernel 0 # nu drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed -drivesys.tsunami.ethernet.descDMAReads 4334 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 104016 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 116400 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1332,7 +778,7 @@ drivesys.tsunami.ethernet.coalescedTxOk 0 # av drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 4334 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 4850 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -1340,7 +786,9 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 4334 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +drivesys.iobus.throughput 290488448 # Throughput (bytes/s) +drivesys.iobus.data_through_bus 118328 # Total data (bytes) ---------- End Simulation Statistics ---------- |