diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt | 374 |
1 files changed, 187 insertions, 187 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 35c6d79b2..9728f1e09 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24560000 # Number of ticks simulated -final_tick 24560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25046000 # Number of ticks simulated +final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1785 # Simulator instruction rate (inst/s) -host_op_rate 1785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6860090 # Simulator tick rate (ticks/s) -host_mem_usage 225432 # Number of bytes of host memory used -host_seconds 3.58 # Real time elapsed on the host +host_inst_rate 25238 # Simulator instruction rate (inst/s) +host_op_rate 25236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98905790 # Simulator tick rate (ticks/s) +host_mem_usage 225424 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 781758958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 437785016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1219543974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 781758958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 781758958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 781758958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 437785016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1219543974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 766589475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 429290106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1195879582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 766589475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 766589475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24545500 # Total gap between requests +system.physmem.totGap 25031500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # By system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation -system.physmem.totQLat 1607750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11529000 # Sum of mem lat for all requests +system.physmem.totQLat 1857500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11820000 # Sum of mem lat for all requests system.physmem.totBusLat 2345000 # Total cycles spent in databus access -system.physmem.totBankLat 7576250 # Total cycles spent in bank access -system.physmem.avgQLat 3428.04 # Average queueing delay per request -system.physmem.avgBankLat 16154.05 # Average bank access latency per request +system.physmem.totBankLat 7617500 # Total cycles spent in bank access +system.physmem.avgQLat 3960.55 # Average queueing delay per request +system.physmem.avgBankLat 16242.00 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24582.09 # Average memory access latency -system.physmem.avgRdBW 1219.54 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25202.56 # Average memory access latency +system.physmem.avgRdBW 1195.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1219.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1195.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.53 # Data bus utilization in percentage +system.physmem.busUtil 9.34 # Data bus utilization in percentage system.physmem.avgRdQLen 0.47 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 402 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 52335.82 # Average gap between requests -system.membus.throughput 1219543974 # Throughput (bytes/s) +system.physmem.avgGap 53372.07 # Average gap between requests +system.membus.throughput 1195879582 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -201,10 +201,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 563500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 4381500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4378000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.5 # Layer utilization (%) system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -247,7 +247,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 49121 # number of cpu cycles simulated +system.cpu.numCycles 50093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). @@ -269,12 +269,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11658 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11606 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 510 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41745 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 460 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42717 # Number of cycles cpu's stages were not processed system.cpu.runCycles 7376 # Number of cycles cpu stages are processed. -system.cpu.activity 15.015981 # Percentage of cycles cpu is active +system.cpu.activity 14.724612 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -286,36 +286,36 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 7.687167 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.839280 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.687167 # CPI: Total CPI of All Threads -system.cpu.ipc 0.130087 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.839280 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127563 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.130087 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 44197 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127563 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45169 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 10.024226 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45228 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.829717 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46200 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.925327 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44960 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.771545 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 45932 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.470919 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47787 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.306550 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48759 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.715743 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 44663 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.663047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.075548 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 140.779037 # Cycle average of tags in use -system.cpu.icache.total_refs 560 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 140.779037 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.068740 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.068740 # Average percentage of cache occupancy +system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -328,12 +328,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24103000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24103000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24103000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24103000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24103000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24103000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24600000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24600000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24600000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24600000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24600000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24600000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -346,17 +346,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67895.774648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67895.774648 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67895.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67895.774648 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69295.774648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69295.774648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69295.774648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69295.774648 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -372,26 +372,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20462500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20462500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20462500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20462500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20462500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20462500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20800250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20800250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20800250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20800250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20800250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20800250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67756.622517 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67756.622517 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68875 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68875 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1222149837 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1198434880 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -405,22 +405,22 @@ system.cpu.toL2Bus.tot_pkt_size 30016 # Cu system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 451500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 197.103662 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.828803 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.274859 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006015 # Average percentage of cache occupancy +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 512750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -438,17 +438,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20144000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6932500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27076500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4877500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4877500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11810000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31954000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20144000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11810000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31954000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20481750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6961500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27443250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4890250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4890250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20481750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11851750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32333500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20481750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11851750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32333500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -471,17 +471,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66923.588040 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72973.684211 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68375 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66815.068493 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66815.068493 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68132.196162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68132.196162 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68045.681063 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73278.947368 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69301.136364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66989.726027 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66989.726027 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68941.364606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68941.364606 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,17 +501,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16417750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5764000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22181750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16699250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5777500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22476750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16417750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9750750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26168500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16417750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9750750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26168500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16699250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9764250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26463500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16699250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9764250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26463500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -523,27 +523,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54544.019934 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60673.684211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56014.520202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55479.235880 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60815.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56759.469697 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.747723 # Cycle average of tags in use -system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.747723 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025085 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025085 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -560,14 +560,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7336500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7336500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21108000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21108000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28444500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28444500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28444500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28444500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7410000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7410000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21312750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21312750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28722750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28722750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28722750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28722750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -584,19 +584,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75634.020619 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75634.020619 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60308.571429 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60308.571429 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63634.228188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63634.228188 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76391.752577 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76391.752577 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60893.571429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60893.571429 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64256.711409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64256.711409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.533333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -616,14 +616,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7034000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7034000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4955000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4955000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11989000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11989000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11989000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11989000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7063000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7063000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4967750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4967750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12030750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12030750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -632,14 +632,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74042.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74042.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67876.712329 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67876.712329 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74347.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74347.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68051.369863 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68051.369863 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |