diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt | 934 |
1 files changed, 467 insertions, 467 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 39aafd883..b10a33b72 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,458 +1,42 @@ ---------- Begin Simulation Statistics ---------- +sim_seconds 0.000035 # Number of seconds simulated +sim_ticks 35015500 # Number of ticks simulated final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 59280 # Simulator instruction rate (inst/s) -host_mem_usage 248380 # Number of bytes of host memory used -host_op_rate 59280 # Simulator op (including micro ops) rate (op/s) -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 324332505 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 57020 # Simulator instruction rate (inst/s) +host_op_rate 57008 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 311836228 # Simulator tick rate (ticks/s) +host_mem_usage 240292 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated -sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 35015500 # Number of ticks simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 381 # Number of BTB hits -system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted -system.cpu.branchPred.lookups 1959 # Number of BP lookups -system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 6400 # Number of instructions committed -system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.cpi 10.942344 # CPI: cycles per instruction -system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 78029.411765 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78029.411765 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 76945.312500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76945.312500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7959000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7959000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7386750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7386750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70147.260274 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70147.260274 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8687500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8687500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5120750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5120750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73332.599119 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73332.599119 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 74008.875740 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74008.875740 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 16646500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16646500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12507500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12507500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73332.599119 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73332.599119 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 74008.875740 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74008.875740 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits -system.cpu.dcache.overall_hits::total 1968 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 16646500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16646500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses -system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12507500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12507500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 103.870916 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.025359 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025359 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 103.870916 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.discardedOps 1111 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dtb.data_accesses 2266 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2252 # DTB hits -system.cpu.dtb.data_misses 14 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1379 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1368 # DTB read hits -system.cpu.dtb.read_misses 11 # DTB read misses -system.cpu.dtb.write_accesses 887 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 884 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70238.356164 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70238.356164 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67805.479452 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67805.479452 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25637000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25637000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24749000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24749000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70238.356164 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70238.356164 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67805.479452 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67805.479452 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 25637000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25637000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24749000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24749000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70238.356164 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70238.356164 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67805.479452 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67805.479452 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits -system.cpu.icache.overall_hits::total 2265 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 25637000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25637000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses -system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24749000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24749000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 5625 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 175.902434 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085890 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085890 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 175.902434 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 57521 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.091388 # IPC: instructions per cycle -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 2647 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 2630 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69126.712329 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69126.712329 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56544.520548 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56544.520548 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5046250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5046250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4127750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4127750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68832.065217 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68832.065217 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56304.891304 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56304.891304 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31662750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31662750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 460 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25900250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25900250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68872.420263 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68872.420263 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56337.711069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56337.711069 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 36709000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36709000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30028000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30028000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68872.420263 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68872.420263 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56337.711069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56337.711069 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 36709000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36709000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses -system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30028000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30028000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.550813 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007127 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007127 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 233.550813 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 70031 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 12510 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 34112 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4977500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.2 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 974197141 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 460 # Transaction distribution -system.membus.trans_dist::ReadResp 460 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 65510.32 # Average gap between requests -system.physmem.avgMemAccLat 25799.25 # Average memory access latency per DRAM burst -system.physmem.avgQLat 7049.25 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 7.61 # Data bus utilization in percentage -system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory +system.physmem.bytes_read::total 34112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory +system.physmem.num_reads::total 533 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 369.617978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 234.259007 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.584548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22 24.72% 24.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 23 25.84% 50.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 11.24% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 8.99% 70.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.49% 75.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 6.74% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.25% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 4.49% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation +system.physmem.readReqs 533 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory -system.physmem.bytes_read::total 34112 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 15500 # Time in different power states -system.physmem.memoryStateTime::REF 1040000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 30385500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.perBankRdBursts::0 73 # Per bank write bursts system.physmem.perBankRdBursts::1 39 # Per bank write bursts system.physmem.perBankRdBursts::2 36 # Per bank write bursts @@ -485,8 +69,25 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 34917000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 533 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -517,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 533 # Read request sizes (log2) -system.physmem.readReqs 533 # Number of read requests accepted -system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads -system.physmem.readRowHits 436 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.totGap 34917000 # Total gap between requests -system.physmem.totMemAccLat 13751000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 3757250 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -597,17 +182,432 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 90 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 365.511111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 232.220198 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.209697 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22 24.44% 24.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 24 26.67% 51.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation +system.physmem.totQLat 3823500 # Total ticks spent queuing +system.physmem.totMemAccLat 13817250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7173.55 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25923.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 7.61 # Data bus utilization in percentage +system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 435 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 65510.32 # Average gap between requests +system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 15500 # Time in different power states +system.physmem.memoryStateTime::REF 1040000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 30385500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 974197141 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 460 # Transaction distribution +system.membus.trans_dist::ReadResp 460 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34112 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 1959 # Number of BP lookups +system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups +system.cpu.branchPred.BTBHits 381 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1368 # DTB read hits +system.cpu.dtb.read_misses 11 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1379 # DTB read accesses +system.cpu.dtb.write_hits 884 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 887 # DTB write accesses +system.cpu.dtb.data_hits 2252 # DTB hits +system.cpu.dtb.data_misses 14 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2266 # DTB accesses +system.cpu.itb.fetch_hits 2630 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2647 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 70031 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6400 # Number of instructions committed +system.cpu.committedOps 6400 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 10.942344 # CPI: cycles per instruction +system.cpu.ipc 0.091388 # IPC: instructions per cycle +system.cpu.tickCycles 12510 # Number of cycles that the object actually ticked +system.cpu.idleCycles 57521 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 176.143820 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 176.143820 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.086008 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.086008 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5625 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits +system.cpu.icache.overall_hits::total 2265 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses +system.cpu.icache.overall_misses::total 365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25932750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25932750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25932750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25932750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25932750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25932750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71048.630137 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71048.630137 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71048.630137 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71048.630137 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25045250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25045250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25045250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25045250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25045250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25045250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68617.123288 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68617.123288 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 233.878182 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.878182 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 460 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses +system.cpu.l2cache.overall_misses::total 533 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5056000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36782750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36782750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36782750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36782750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69260.273973 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69260.273973 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69010.787992 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69010.787992 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25965250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25965250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30103250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30103250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30103250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30103250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56446.195652 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56446.195652 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 104.053835 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 104.053835 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.025404 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025404 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits +system.cpu.dcache.overall_hits::total 1968 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses +system.cpu.dcache.overall_misses::total 227 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7727250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7727250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8696750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8696750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16424000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75757.352941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75757.352941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69574 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69574 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72352.422907 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7154500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5130500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12285000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74526.041667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74526.041667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70280.821918 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70280.821918 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |