diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt | 306 |
1 files changed, 153 insertions, 153 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index e5561895a..112157b30 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000041 # Nu sim_ticks 41083000 # Number of ticks simulated final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 217103 # Simulator instruction rate (inst/s) -host_op_rate 217013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1389706699 # Simulator tick rate (ticks/s) -host_mem_usage 253264 # Number of bytes of host memory used +host_inst_rate 202272 # Simulator instruction rate (inst/s) +host_op_rate 202193 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1294825774 # Simulator tick rate (ticks/s) +host_mem_usage 252636 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # By system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation -system.physmem.totQLat 6580250 # Total ticks spent queuing -system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6584250 # Total ticks spent queuing +system.physmem.totMemAccLat 16559250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12376.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31126.41 # Average memory access latency per DRAM burst system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s @@ -247,9 +247,9 @@ system.physmem_1.preEnergy 208725 # En system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 4023060 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 14292180 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ) @@ -262,19 +262,19 @@ system.physmem_1.memoryStateTime::PRE_PDN 464250 # T system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2003 # Number of BP lookups -system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups +system.cpu.branchPred.lookups 2002 # Number of BP lookups +system.cpu.branchPred.condPredicted 1237 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 378 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1602 # Number of BTB lookups system.cpu.branchPred.BTBHits 377 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 23.533084 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 322 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 333 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 319 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 114 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -292,10 +292,10 @@ system.cpu.dtb.data_hits 2249 # DT system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2263 # DTB accesses -system.cpu.itb.fetch_hits 2686 # ITB hits +system.cpu.itb.fetch_hits 2685 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2703 # ITB accesses +system.cpu.itb.fetch_accesses 2702 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -315,7 +315,7 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6413 # Number of instructions committed system.cpu.committedOps 6413 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1093 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 12.812412 # CPI: cycles per instruction system.cpu.ipc 0.078049 # IPC: instructions per cycle @@ -358,18 +358,18 @@ system.cpu.op_class_0::FloatMemWrite 7 0.11% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 6413 # Class of committed instruction -system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked -system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 12637 # Number of cycles that the object actually ticked +system.cpu.idleCycles 69529 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.987673 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.987673 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025388 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025388 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id @@ -395,12 +395,12 @@ system.cpu.dcache.overall_misses::cpu.data 221 # system.cpu.dcache.overall_misses::total 221 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10428500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10428500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18974000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18974000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18974000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18974000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -419,12 +419,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 83428 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85855.203620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85855.203620 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,12 +447,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 169 system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14538500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14538500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14538500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14538500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -463,65 +463,65 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83410.958904 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83410.958904 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.158440 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2321 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.376374 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.158440 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085527 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085527 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5736 # Number of data accesses +system.cpu.icache.tags.tag_accesses 5734 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5734 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits -system.cpu.icache.overall_hits::total 2322 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 2321 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2321 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2321 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2321 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2321 # number of overall hits +system.cpu.icache.overall_hits::total 2321 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30321500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30321500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30321500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30321500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30321500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30321500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2685 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2685 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2685 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2685 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2685 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2685 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135568 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.135568 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.135568 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.135568 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.135568 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.135568 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83300.824176 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 83300.824176 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 83300.824176 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 83300.824176 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,33 +534,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 364 system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29957500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29957500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135568 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.135568 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.135568 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82300.824176 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82300.824176 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 279.188916 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.158050 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 104.030866 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.008520 # Average percentage of cache occupancy @@ -589,18 +589,18 @@ system.cpu.l2cache.demand_misses::total 532 # nu system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 532 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5979500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5979500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29400000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 29400000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8304000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 8304000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 29400000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14283500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 43683500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 29400000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14283500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 43683500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) @@ -625,18 +625,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998124 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81910.958904 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81910.958904 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80991.735537 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80991.735537 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82111.842105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82111.842105 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,18 +655,18 @@ system.cpu.l2cache.demand_mshr_misses::total 532 system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5249500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5249500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25770000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25770000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25770000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12593500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 38363500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25770000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12593500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 38363500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses @@ -679,18 +679,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71910.958904 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71910.958904 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70991.735537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70991.735537 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -755,7 +755,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 532 # Request fanout histogram -system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 607000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) system.membus.respLayer1.occupancy 2825000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.9 # Layer utilization (%) |