diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory')
2 files changed, 106 insertions, 476 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats index bdfda8e2d..0b9ca4b9f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,26 +1,24 @@ -Real time: Mar/06/2013 20:38:34 +Real time: Jun/08/2013 14:12:32 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.68 -Virtual_time_in_minutes: 0.0113333 -Virtual_time_in_hours: 0.000188889 -Virtual_time_in_days: 7.87037e-06 +Virtual_time_in_seconds: 0.6 +Virtual_time_in_minutes: 0.01 +Virtual_time_in_hours: 0.000166667 +Virtual_time_in_days: 6.94444e-06 Ruby_current_time: 138616 Ruby_start_time: 0 Ruby_cycles: 138616 -mbytes_resident: 55.9375 -mbytes_total: 148.203 -resident_ratio: 0.377491 - -ruby_cycles_executed: [ 138617 ] +mbytes_resident: 56.3281 +mbytes_total: 144.332 +resident_ratio: 0.390322 Busy Controller Counts: L1Cache-0:0 @@ -61,7 +59,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -82,7 +79,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11604 +page_reclaims: 11627 page_faults: 0 swaps: 0 block_inputs: 0 @@ -160,458 +157,3 @@ links_utilized_percent_switch_3: 4.89085 outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [1183 ] 1183 -Ifetch [6400 ] 6400 -Store [865 ] 865 -Inv [1041 ] 1041 -L1_Replacement [1354 ] 1354 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_GET_INSTR [0 ] 0 -Data [0 ] 0 -Data_Exclusive [583 ] 583 -DataS_fromL1 [0 ] 0 -Data_all_Acks [907 ] 907 -Ack [0 ] 0 -Ack_all [0 ] 0 -WB_Ack [436 ] 436 -PF_Load [0 ] 0 -PF_Ifetch [0 ] 0 -PF_Store [0 ] 0 - - - Transitions - -NP Load [525 ] 525 -NP Ifetch [646 ] 646 -NP Store [191 ] 191 -NP Inv [356 ] 356 -NP L1_Replacement [0 ] 0 -NP PF_Load [0 ] 0 -NP PF_Ifetch [0 ] 0 -NP PF_Store [0 ] 0 - -I Load [58 ] 58 -I Ifetch [45 ] 45 -I Store [25 ] 25 -I Inv [0 ] 0 -I L1_Replacement [556 ] 556 -I PF_Load [0 ] 0 -I PF_Ifetch [0 ] 0 -I PF_Store [0 ] 0 - -S Load [0 ] 0 -S Ifetch [5709 ] 5709 -S Store [0 ] 0 -S Inv [325 ] 325 -S L1_Replacement [362 ] 362 -S PF_Load [0 ] 0 -S PF_Store [0 ] 0 - -E Load [452 ] 452 -E Ifetch [0 ] 0 -E Store [71 ] 71 -E Inv [219 ] 219 -E L1_Replacement [291 ] 291 -E Fwd_GETX [0 ] 0 -E Fwd_GETS [0 ] 0 -E Fwd_GET_INSTR [0 ] 0 -E PF_Load [0 ] 0 -E PF_Store [0 ] 0 - -M Load [148 ] 148 -M Ifetch [0 ] 0 -M Store [578 ] 578 -M Inv [141 ] 141 -M L1_Replacement [145 ] 145 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_GET_INSTR [0 ] 0 -M PF_Load [0 ] 0 -M PF_Store [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS Inv [0 ] 0 -IS L1_Replacement [0 ] 0 -IS Data_Exclusive [583 ] 583 -IS DataS_fromL1 [0 ] 0 -IS Data_all_Acks [691 ] 691 -IS PF_Load [0 ] 0 -IS PF_Store [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM Inv [0 ] 0 -IM L1_Replacement [0 ] 0 -IM Data [0 ] 0 -IM Data_all_Acks [216 ] 216 -IM Ack [0 ] 0 -IM PF_Load [0 ] 0 -IM PF_Store [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM Inv [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Ack [0 ] 0 -SM Ack_all [0 ] 0 -SM PF_Load [0 ] 0 -SM PF_Store [0 ] 0 - -IS_I Load [0 ] 0 -IS_I Ifetch [0 ] 0 -IS_I Store [0 ] 0 -IS_I Inv [0 ] 0 -IS_I L1_Replacement [0 ] 0 -IS_I Data_Exclusive [0 ] 0 -IS_I DataS_fromL1 [0 ] 0 -IS_I Data_all_Acks [0 ] 0 -IS_I PF_Load [0 ] 0 -IS_I PF_Store [0 ] 0 - -M_I Load [0 ] 0 -M_I Ifetch [0 ] 0 -M_I Store [0 ] 0 -M_I Inv [0 ] 0 -M_I L1_Replacement [0 ] 0 -M_I Fwd_GETX [0 ] 0 -M_I Fwd_GETS [0 ] 0 -M_I Fwd_GET_INSTR [0 ] 0 -M_I WB_Ack [436 ] 436 -M_I PF_Load [0 ] 0 -M_I PF_Store [0 ] 0 - -SINK_WB_ACK Load [0 ] 0 -SINK_WB_ACK Ifetch [0 ] 0 -SINK_WB_ACK Store [0 ] 0 -SINK_WB_ACK Inv [0 ] 0 -SINK_WB_ACK L1_Replacement [0 ] 0 -SINK_WB_ACK WB_Ack [0 ] 0 -SINK_WB_ACK PF_Load [0 ] 0 -SINK_WB_ACK PF_Store [0 ] 0 - -PF_IS Load [0 ] 0 -PF_IS Ifetch [0 ] 0 -PF_IS Store [0 ] 0 -PF_IS Inv [0 ] 0 -PF_IS L1_Replacement [0 ] 0 -PF_IS Data_Exclusive [0 ] 0 -PF_IS DataS_fromL1 [0 ] 0 -PF_IS Data_all_Acks [0 ] 0 -PF_IS PF_Load [0 ] 0 -PF_IS PF_Store [0 ] 0 - -PF_IM Load [0 ] 0 -PF_IM Ifetch [0 ] 0 -PF_IM Store [0 ] 0 -PF_IM Inv [0 ] 0 -PF_IM L1_Replacement [0 ] 0 -PF_IM Data [0 ] 0 -PF_IM Data_all_Acks [0 ] 0 -PF_IM Ack [0 ] 0 -PF_IM PF_Load [0 ] 0 -PF_IM PF_Store [0 ] 0 - -PF_SM Load [0 ] 0 -PF_SM Ifetch [0 ] 0 -PF_SM Store [0 ] 0 -PF_SM Inv [0 ] 0 -PF_SM L1_Replacement [0 ] 0 -PF_SM Ack [0 ] 0 -PF_SM Ack_all [0 ] 0 - -PF_IS_I Load [0 ] 0 -PF_IS_I Store [0 ] 0 -PF_IS_I Inv [0 ] 0 -PF_IS_I L1_Replacement [0 ] 0 -PF_IS_I Data_Exclusive [0 ] 0 -PF_IS_I DataS_fromL1 [0 ] 0 -PF_IS_I Data_all_Acks [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GET_INSTR [691 ] 691 -L1_GETS [583 ] 583 -L1_GETX [216 ] 216 -L1_UPGRADE [0 ] 0 -L1_PUTX [436 ] 436 -L1_PUTX_old [0 ] 0 -Fwd_L1_GETX [0 ] 0 -Fwd_L1_GETS [0 ] 0 -Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [142 ] 142 -L2_Replacement_clean [1310 ] 1310 -Mem_Data [1460 ] 1460 -Mem_Ack [1452 ] 1452 -WB_Data [141 ] 141 -WB_Data_clean [0 ] 0 -Ack [0 ] 0 -Ack_all [900 ] 900 -Unblock [0 ] 0 -Unblock_Cancel [0 ] 0 -Exclusive_Unblock [799 ] 799 -MEM_Inv [0 ] 0 - - - Transitions - -NP L1_GET_INSTR [686 ] 686 -NP L1_GETS [570 ] 570 -NP L1_GETX [204 ] 204 -NP L1_PUTX [0 ] 0 -NP L1_PUTX_old [0 ] 0 - -SS L1_GET_INSTR [5 ] 5 -SS L1_GETS [0 ] 0 -SS L1_GETX [0 ] 0 -SS L1_UPGRADE [0 ] 0 -SS L1_PUTX [0 ] 0 -SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L2_Replacement_clean [681 ] 681 -SS MEM_Inv [0 ] 0 - -M L1_GET_INSTR [0 ] 0 -M L1_GETS [13 ] 13 -M L1_GETX [12 ] 12 -M L1_PUTX [0 ] 0 -M L1_PUTX_old [0 ] 0 -M L2_Replacement [134 ] 134 -M L2_Replacement_clean [277 ] 277 -M MEM_Inv [0 ] 0 - -MT L1_GET_INSTR [0 ] 0 -MT L1_GETS [0 ] 0 -MT L1_GETX [0 ] 0 -MT L1_PUTX [436 ] 436 -MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [8 ] 8 -MT L2_Replacement_clean [352 ] 352 -MT MEM_Inv [0 ] 0 - -M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [0 ] 0 -M_I L1_GETX [0 ] 0 -M_I L1_UPGRADE [0 ] 0 -M_I L1_PUTX [0 ] 0 -M_I L1_PUTX_old [0 ] 0 -M_I Mem_Ack [1452 ] 1452 -M_I MEM_Inv [0 ] 0 - -MT_I L1_GET_INSTR [0 ] 0 -MT_I L1_GETS [0 ] 0 -MT_I L1_GETX [0 ] 0 -MT_I L1_UPGRADE [0 ] 0 -MT_I L1_PUTX [0 ] 0 -MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [6 ] 6 -MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [2 ] 2 -MT_I MEM_Inv [0 ] 0 - -MCT_I L1_GET_INSTR [0 ] 0 -MCT_I L1_GETS [0 ] 0 -MCT_I L1_GETX [0 ] 0 -MCT_I L1_UPGRADE [0 ] 0 -MCT_I L1_PUTX [0 ] 0 -MCT_I L1_PUTX_old [0 ] 0 -MCT_I WB_Data [135 ] 135 -MCT_I WB_Data_clean [0 ] 0 -MCT_I Ack_all [217 ] 217 - -I_I L1_GET_INSTR [0 ] 0 -I_I L1_GETS [0 ] 0 -I_I L1_GETX [0 ] 0 -I_I L1_UPGRADE [0 ] 0 -I_I L1_PUTX [0 ] 0 -I_I L1_PUTX_old [0 ] 0 -I_I Ack [0 ] 0 -I_I Ack_all [681 ] 681 - -S_I L1_GET_INSTR [0 ] 0 -S_I L1_GETS [0 ] 0 -S_I L1_GETX [0 ] 0 -S_I L1_UPGRADE [0 ] 0 -S_I L1_PUTX [0 ] 0 -S_I L1_PUTX_old [0 ] 0 -S_I Ack [0 ] 0 -S_I Ack_all [0 ] 0 -S_I MEM_Inv [0 ] 0 - -ISS L1_GET_INSTR [0 ] 0 -ISS L1_GETS [0 ] 0 -ISS L1_GETX [0 ] 0 -ISS L1_PUTX [0 ] 0 -ISS L1_PUTX_old [0 ] 0 -ISS L2_Replacement [0 ] 0 -ISS L2_Replacement_clean [0 ] 0 -ISS Mem_Data [570 ] 570 -ISS MEM_Inv [0 ] 0 - -IS L1_GET_INSTR [0 ] 0 -IS L1_GETS [0 ] 0 -IS L1_GETX [0 ] 0 -IS L1_PUTX [0 ] 0 -IS L1_PUTX_old [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L2_Replacement_clean [0 ] 0 -IS Mem_Data [686 ] 686 -IS MEM_Inv [0 ] 0 - -IM L1_GET_INSTR [0 ] 0 -IM L1_GETS [0 ] 0 -IM L1_GETX [0 ] 0 -IM L1_PUTX [0 ] 0 -IM L1_PUTX_old [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L2_Replacement_clean [0 ] 0 -IM Mem_Data [204 ] 204 -IM MEM_Inv [0 ] 0 - -SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [0 ] 0 -SS_MB L1_GETX [0 ] 0 -SS_MB L1_UPGRADE [0 ] 0 -SS_MB L1_PUTX [0 ] 0 -SS_MB L1_PUTX_old [0 ] 0 -SS_MB L2_Replacement [0 ] 0 -SS_MB L2_Replacement_clean [0 ] 0 -SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [0 ] 0 -SS_MB MEM_Inv [0 ] 0 - -MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [0 ] 0 -MT_MB L1_GETX [0 ] 0 -MT_MB L1_UPGRADE [0 ] 0 -MT_MB L1_PUTX [0 ] 0 -MT_MB L1_PUTX_old [0 ] 0 -MT_MB L2_Replacement [0 ] 0 -MT_MB L2_Replacement_clean [0 ] 0 -MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [799 ] 799 -MT_MB MEM_Inv [0 ] 0 - -MT_IIB L1_GET_INSTR [0 ] 0 -MT_IIB L1_GETS [0 ] 0 -MT_IIB L1_GETX [0 ] 0 -MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [0 ] 0 -MT_IIB L1_PUTX_old [0 ] 0 -MT_IIB L2_Replacement [0 ] 0 -MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [0 ] 0 -MT_IIB WB_Data_clean [0 ] 0 -MT_IIB Unblock [0 ] 0 -MT_IIB MEM_Inv [0 ] 0 - -MT_IB L1_GET_INSTR [0 ] 0 -MT_IB L1_GETS [0 ] 0 -MT_IB L1_GETX [0 ] 0 -MT_IB L1_UPGRADE [0 ] 0 -MT_IB L1_PUTX [0 ] 0 -MT_IB L1_PUTX_old [0 ] 0 -MT_IB L2_Replacement [0 ] 0 -MT_IB L2_Replacement_clean [0 ] 0 -MT_IB WB_Data [0 ] 0 -MT_IB WB_Data_clean [0 ] 0 -MT_IB Unblock_Cancel [0 ] 0 -MT_IB MEM_Inv [0 ] 0 - -MT_SB L1_GET_INSTR [0 ] 0 -MT_SB L1_GETS [0 ] 0 -MT_SB L1_GETX [0 ] 0 -MT_SB L1_UPGRADE [0 ] 0 -MT_SB L1_PUTX [0 ] 0 -MT_SB L1_PUTX_old [0 ] 0 -MT_SB L2_Replacement [0 ] 0 -MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [0 ] 0 -MT_SB MEM_Inv [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1737 - memory_reads: 1460 - memory_writes: 277 - memory_refreshes: 963 - memory_total_request_delays: 341 - memory_delays_per_request: 0.196315 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 341 - memory_stalls_for_bank_busy: 166 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 24 - memory_stalls_for_bus: 147 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 4 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61 - - --- Directory --- - - Event Counts - -Fetch [1460 ] 1460 -Data [277 ] 277 -Memory_Data [1460 ] 1460 -Memory_Ack [277 ] 277 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -CleanReplacement [1175 ] 1175 - - - Transitions - -I Fetch [1460 ] 1460 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -ID Fetch [0 ] 0 -ID Data [0 ] 0 -ID Memory_Data [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 - -ID_W Fetch [0 ] 0 -ID_W Data [0 ] 0 -ID_W Memory_Ack [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 - -M Data [277 ] 277 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 -M CleanReplacement [1175 ] 1175 - -IM Fetch [0 ] 0 -IM Data [0 ] 0 -IM Memory_Data [1460 ] 1460 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 - -MI Fetch [0 ] 0 -MI Data [0 ] 0 -MI Memory_Ack [277 ] 277 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -M_DRD Data [0 ] 0 -M_DRD DMA_READ [0 ] 0 -M_DRD DMA_WRITE [0 ] 0 - -M_DRDI Fetch [0 ] 0 -M_DRDI Data [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 -M_DRDI DMA_READ [0 ] 0 -M_DRDI DMA_WRITE [0 ] 0 - -M_DWR Data [0 ] 0 -M_DWR DMA_READ [0 ] 0 -M_DWR DMA_WRITE [0 ] 0 - -M_DWRI Fetch [0 ] 0 -M_DWRI Data [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 -M_DWRI DMA_READ [0 ] 0 -M_DWRI DMA_WRITE [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index ffef61c0e..53a8460e0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu sim_ticks 138616 # Number of ticks simulated final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 20262 # Simulator instruction rate (inst/s) -host_op_rate 20260 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 439475 # Simulator tick rate (ticks/s) -host_mem_usage 154624 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host +host_inst_rate 33803 # Simulator instruction rate (inst/s) +host_op_rate 33800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 733103 # Simulator tick rate (ticks/s) +host_mem_usage 147800 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits @@ -29,6 +29,20 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.dir_cntrl0.memBuffer.memReq 1737 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1460 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 277 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 963 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 341 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 341 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.196315 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 166 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 147 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 24 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 92 5.30% 5.30% | 21 1.21% 6.51% | 45 2.59% 9.10% | 54 3.11% 12.20% | 57 3.28% 15.49% | 174 10.02% 25.50% | 48 2.76% 28.27% | 18 1.04% 29.30% | 19 1.09% 30.40% | 22 1.27% 31.66% | 35 2.01% 33.68% | 37 2.13% 35.81% | 56 3.22% 39.03% | 59 3.40% 42.43% | 44 2.53% 44.96% | 36 2.07% 47.04% | 41 2.36% 49.40% | 24 1.38% 50.78% | 22 1.27% 52.04% | 28 1.61% 53.66% | 32 1.84% 55.50% | 48 2.76% 58.26% | 122 7.02% 65.28% | 36 2.07% 67.36% | 32 1.84% 69.20% | 25 1.44% 70.64% | 35 2.01% 72.65% | 96 5.53% 78.18% | 114 6.56% 84.74% | 185 10.65% 95.39% | 19 1.09% 96.49% | 61 3.51% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1737 # Number of accesses per bank + system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -84,5 +98,79 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 138616 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l2_cntrl0.L1_GET_INSTR 691 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS 583 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 216 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 436 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 142 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement_clean 1310 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Data 1460 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Ack 1452 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data 141 0.00% 0.00% +system.ruby.l2_cntrl0.Ack_all 900 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 799 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GET_INSTR 686 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 570 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 204 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GET_INSTR 5 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement_clean 681 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 13 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 12 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 134 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement_clean 277 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_PUTX 436 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement 8 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement_clean 352 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.Mem_Ack 1452 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.WB_Data 6 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data 135 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.Ack_all 217 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack_all 681 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.Mem_Data 570 0.00% 0.00% +system.ruby.l2_cntrl0.IS.Mem_Data 686 0.00% 0.00% +system.ruby.l2_cntrl0.IM.Mem_Data 204 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 799 0.00% 0.00% +system.ruby.l1_cntrl0.Load 1183 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00% +system.ruby.l1_cntrl0.Store 865 0.00% 0.00% +system.ruby.l1_cntrl0.Inv 1041 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 1354 0.00% 0.00% +system.ruby.l1_cntrl0.Data_Exclusive 583 0.00% 0.00% +system.ruby.l1_cntrl0.Data_all_Acks 907 0.00% 0.00% +system.ruby.l1_cntrl0.WB_Ack 436 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Load 525 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Ifetch 646 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Store 191 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Inv 356 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 58 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 45 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 25 0.00% 0.00% +system.ruby.l1_cntrl0.I.L1_Replacement 556 0.00% 0.00% +system.ruby.l1_cntrl0.S.Ifetch 5709 0.00% 0.00% +system.ruby.l1_cntrl0.S.Inv 325 0.00% 0.00% +system.ruby.l1_cntrl0.S.L1_Replacement 362 0.00% 0.00% +system.ruby.l1_cntrl0.E.Load 452 0.00% 0.00% +system.ruby.l1_cntrl0.E.Store 71 0.00% 0.00% +system.ruby.l1_cntrl0.E.Inv 219 0.00% 0.00% +system.ruby.l1_cntrl0.E.L1_Replacement 291 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 148 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 578 0.00% 0.00% +system.ruby.l1_cntrl0.M.Inv 141 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 145 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive 583 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_all_Acks 691 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data_all_Acks 216 0.00% 0.00% +system.ruby.l1_cntrl0.M_I.WB_Ack 436 0.00% 0.00% +system.ruby.dir_cntrl0.Fetch 1460 0.00% 0.00% +system.ruby.dir_cntrl0.Data 277 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 1460 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 277 0.00% 0.00% +system.ruby.dir_cntrl0.CleanReplacement 1175 0.00% 0.00% +system.ruby.dir_cntrl0.I.Fetch 1460 0.00% 0.00% +system.ruby.dir_cntrl0.M.Data 277 0.00% 0.00% +system.ruby.dir_cntrl0.M.CleanReplacement 1175 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 1460 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 277 0.00% 0.00% ---------- End Simulation Statistics ---------- |