diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini | 39 |
1 files changed, 35 insertions, 4 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini index 27b1ed20b..1a2ad4916 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini @@ -10,13 +10,14 @@ time_sync_spin_threshold=100000 [system] type=System -children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain +children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 init_param=0 kernel= +kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -37,7 +38,9 @@ system_port=system.sys_port_proxy.slave[0] [system.clk_domain] type=SrcClockDomain clock=1 +domain_id=-1 eventq_index=0 +init_perf_level=0 voltage_domain=system.voltage_domain [system.cpu] @@ -76,7 +79,9 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] [system.cpu.clk_domain] type=SrcClockDomain clock=1 +domain_id=-1 eventq_index=0 +init_perf_level=0 voltage_domain=system.voltage_domain [system.cpu.dtb] @@ -111,7 +116,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -122,6 +127,14 @@ simpoint=0 system=system uid=100 +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + [system.physmem] type=SimpleMemory bandwidth=0.000000 @@ -151,7 +164,9 @@ randomization=false [system.ruby.clk_domain] type=SrcClockDomain clock=1 +domain_id=-1 eventq_index=0 +init_perf_level=0 voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] @@ -171,6 +186,9 @@ ruby_system=system.ruby to_mem_ctrl_latency=1 transitions_per_cycle=4 version=0 +requestToDir=system.ruby.network.master[5] +responseFromDir=system.ruby.network.slave[6] +responseToDir=system.ruby.network.master[6] [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory @@ -210,7 +228,7 @@ children=L1Dcache L1Icache prefetcher sequencer L1Dcache=system.ruby.l1_cntrl0.L1Dcache L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 -clk_domain=system.ruby.clk_domain +clk_domain=system.cpu.clk_domain cluster_id=0 enable_prefetch=false eventq_index=0 @@ -227,6 +245,11 @@ sequencer=system.ruby.l1_cntrl0.sequencer to_l2_latency=1 transitions_per_cycle=4 version=0 +requestFromL1Cache=system.ruby.network.slave[0] +requestToL1Cache=system.ruby.network.master[0] +responseFromL1Cache=system.ruby.network.slave[1] +responseToL1Cache=system.ruby.network.master[1] +unblockFromL1Cache=system.ruby.network.slave[2] [system.ruby.l1_cntrl0.L1Dcache] type=RubyCache @@ -272,7 +295,7 @@ unit_filter=8 [system.ruby.l1_cntrl0.sequencer] type=RubySequencer access_phys_mem=false -clk_domain=system.ruby.clk_domain +clk_domain=system.cpu.clk_domain dcache=system.ruby.l1_cntrl0.L1Dcache deadlock_threshold=500000 eventq_index=0 @@ -304,6 +327,12 @@ ruby_system=system.ruby to_l1_latency=1 transitions_per_cycle=4 version=0 +DirRequestFromL2Cache=system.ruby.network.slave[3] +L1RequestFromL2Cache=system.ruby.network.slave[4] +L1RequestToL2Cache=system.ruby.network.master[3] +responseFromL2Cache=system.ruby.network.slave[5] +responseToL2Cache=system.ruby.network.master[4] +unblockToL2Cache=system.ruby.network.master[2] [system.ruby.l2_cntrl0.L2cache] type=RubyCache @@ -342,6 +371,8 @@ number_of_virtual_networks=10 routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar +master=system.ruby.l1_cntrl0.requestToL1Cache system.ruby.l1_cntrl0.responseToL1Cache system.ruby.l2_cntrl0.unblockToL2Cache system.ruby.l2_cntrl0.L1RequestToL2Cache system.ruby.l2_cntrl0.responseToL2Cache system.ruby.dir_cntrl0.requestToDir system.ruby.dir_cntrl0.responseToDir +slave=system.ruby.l1_cntrl0.requestFromL1Cache system.ruby.l1_cntrl0.responseFromL1Cache system.ruby.l1_cntrl0.unblockFromL1Cache system.ruby.l2_cntrl0.DirRequestFromL2Cache system.ruby.l2_cntrl0.L1RequestFromL2Cache system.ruby.l2_cntrl0.responseFromL2Cache system.ruby.dir_cntrl0.responseFromDir [system.ruby.network.ext_links0] type=SimpleExtLink |