diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats | 13 | ||||
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt | 19 |
2 files changed, 8 insertions, 24 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats index 0916fd5d5..b561f1129 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats @@ -133,19 +133,6 @@ links_utilized_percent_switch_2: 6.00613 outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.l1_cntrl0.cacheMemory - system.ruby.l1_cntrl0.cacheMemory_total_misses: 1730 - system.ruby.l1_cntrl0.cacheMemory_total_demand_misses: 1730 - system.ruby.l1_cntrl0.cacheMemory_total_prefetches: 0 - system.ruby.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 - system.ruby.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 - - system.ruby.l1_cntrl0.cacheMemory_request_type_LD: 42.0231% - system.ruby.l1_cntrl0.cacheMemory_request_type_ST: 15.7803% - system.ruby.l1_cntrl0.cacheMemory_request_type_IFETCH: 42.1965% - - system.ruby.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1730 100% - --- L1Cache --- - Event Counts - Load [1183 ] 1183 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index db16b5ceb..e942e8340 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,19 +4,16 @@ sim_seconds 0.000144 # Nu sim_ticks 143853 # Number of ticks simulated final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 25445 # Simulator instruction rate (inst/s) -host_op_rate 25443 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 572727 # Simulator tick rate (ticks/s) -host_mem_usage 150220 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 31570 # Simulator instruction rate (inst/s) +host_op_rate 31567 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 710572 # Simulator tick rate (ticks/s) +host_mem_usage 153096 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated -system.ruby.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads -system.ruby.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes -system.ruby.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.ruby.l1_cntrl0.cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.ruby.l1_cntrl0.cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.ruby.l1_cntrl0.cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv |