diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/linux')
41 files changed, 8739 insertions, 0 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini new file mode 100644 index 000000000..b17544f09 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -0,0 +1,240 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=InOrderCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +activity=0 +cachePorts=2 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +cpu_id=0 +dataMemPort=dcache_port +defer_registration=false +div16Latency=1 +div16RepeatRate=1 +div24Latency=1 +div24RepeatRate=1 +div32Latency=1 +div32RepeatRate=1 +div8Latency=1 +div8RepeatRate=1 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchBuffSize=4 +fetchMemPort=icache_port +functionTrace=false +functionTraceStart=0 +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +memBlockSize=64 +multLatency=1 +multRepeatRate=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +stageTracing=false +stageWidth=4 +system=system +threadModel=SMT +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout new file mode 100755 index 000000000..ba10334c5 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 04:58:59 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 21216000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt new file mode 100644 index 000000000..4ce82e64f --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -0,0 +1,309 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 21216000 # Number of ticks simulated +final_tick 21216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 36015 # Simulator instruction rate (inst/s) +host_tick_rate 119302866 # Simulator tick rate (ticks/s) +host_mem_usage 207132 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +sim_insts 6404 # Number of instructions simulated +system.physmem.bytes_read 30016 # Number of bytes read from this memory +system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 469 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 1414781297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 907993967 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1414781297 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1186 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1193 # DTB read accesses +system.cpu.dtb.write_hits 898 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 901 # DTB write accesses +system.cpu.dtb.data_hits 2084 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2094 # DTB accesses +system.cpu.itb.fetch_hits 929 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 946 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 42433 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 11397 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35050 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7383 # Number of cycles cpu stages are processed. +system.cpu.activity 17.399194 # Percentage of cycles cpu is active +system.cpu.comLoads 1185 # Number of Load instructions committed +system.cpu.comStores 865 # Number of Store instructions committed +system.cpu.comBranches 1051 # Number of Branches instructions committed +system.cpu.comNops 17 # Number of Nop instructions committed +system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed +system.cpu.comInts 3265 # Number of Integer instructions committed +system.cpu.comFloats 2 # Number of Floating Point instructions committed +system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) +system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) +system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi no_value # CPI: Total SMT-CPI +system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150920 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc no_value # IPC: Total SMT-IPC +system.cpu.ipc_total 0.150920 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1670 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1199 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1410 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 414 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 29.361702 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 565 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1105 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5165 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9745 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File +system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 3002 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2138 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 357 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 4447 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed +system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.stage0.idleCycles 37465 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4968 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.707869 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38516 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3917 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.231023 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.853180 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41093 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.157920 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 37964 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4469 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.531897 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 138.882502 # Cycle average of tags in use +system.cpu.icache.total_refs 581 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 138.882502 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.067814 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 581 # number of ReadReq hits +system.cpu.icache.demand_hits 581 # number of demand (read+write) hits +system.cpu.icache.overall_hits 581 # number of overall hits +system.cpu.icache.ReadReq_misses 348 # number of ReadReq misses +system.cpu.icache.demand_misses 348 # number of demand (read+write) misses +system.cpu.icache.overall_misses 348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 19241000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 19241000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 19241000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 929 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 929 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.374596 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.374596 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.374596 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55290.229885 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55290.229885 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55290.229885 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 46 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 46 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 302 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 302 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 302 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 16049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 16049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 16049000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.325081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.325081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.325081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.384106 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use +system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 102.671807 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.025066 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1088 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 615 # number of WriteReq hits +system.cpu.dcache.demand_hits 1703 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1703 # number of overall hits +system.cpu.dcache.ReadReq_misses 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 250 # number of WriteReq misses +system.cpu.dcache.demand_misses 347 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 347 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5508500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 13555500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 19064000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19064000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.081857 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.289017 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.169268 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.169268 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 56788.659794 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 54222 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54939.481268 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54939.481268 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 46000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 177 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 179 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 179 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 5114000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3910000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53831.578947 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53561.643836 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 195.209568 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005957 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses 396 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 469 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 469 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 20702000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3822000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 24524000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 24524000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997481 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.997872 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997872 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52277.777778 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.164384 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52289.978678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52289.978678 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 396 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 469 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 469 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15877000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2942500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18819500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18819500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.997872 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.997872 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40093.434343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40308.219178 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..db5baf5c5 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,535 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList6.opList + +[system.cpu.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout new file mode 100755 index 000000000..6e993ab1c --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 04:58:59 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 12004500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt new file mode 100644 index 000000000..3b3d572bb --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -0,0 +1,508 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12004500 # Number of ticks simulated +final_tick 12004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 38695 # Simulator instruction rate (inst/s) +host_tick_rate 72731813 # Simulator tick rate (ticks/s) +host_mem_usage 208040 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +sim_insts 6386 # Number of instructions simulated +system.physmem.bytes_read 31040 # Number of bytes read from this memory +system.physmem.bytes_inst_read 19904 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 485 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 2585697030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1658044900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2585697030 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1860 # DTB read hits +system.cpu.dtb.read_misses 44 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1904 # DTB read accesses +system.cpu.dtb.write_hits 1041 # DTB write hits +system.cpu.dtb.write_misses 28 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 1069 # DTB write accesses +system.cpu.dtb.data_hits 2901 # DTB hits +system.cpu.dtb.data_misses 72 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2973 # DTB accesses +system.cpu.itb.fetch_hits 2039 # ITB hits +system.cpu.itb.fetch_misses 29 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2068 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 24010 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 2507 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1457 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 459 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 718 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 373 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7150 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14456 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2507 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1091 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2619 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1556 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12592 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.148030 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.530696 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9973 79.20% 79.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.18% 81.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 224 1.78% 83.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.76% 84.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 234 1.86% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 178 1.41% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.04% 90.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 140 1.11% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1090 8.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 12592 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.104415 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.602082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7970 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2449 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 978 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 214 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13378 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 978 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8160 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2318 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12829 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9573 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16037 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16020 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 4990 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2391 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11558 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9757 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4883 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2853 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.774857 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.395692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8510 67.58% 67.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1462 11.61% 79.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1072 8.51% 87.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 685 5.44% 93.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 440 3.49% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 254 2.02% 98.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 128 1.02% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.24% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12592 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13 12.26% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 54 50.94% 63.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 36.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6575 67.39% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2074 21.26% 88.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1103 11.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 9757 # Type of FU issued +system.cpu.iq.rate 0.406372 # Inst issue rate +system.cpu.iq.fu_busy_cnt 106 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010864 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32238 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16474 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 9850 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 1206 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 406 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 978 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11665 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2391 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 447 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9313 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1914 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 80 # number of nop insts executed +system.cpu.iew.exec_refs 2985 # number of memory reference insts executed +system.cpu.iew.exec_branches 1504 # Number of branches executed +system.cpu.iew.exec_stores 1071 # Number of stores executed +system.cpu.iew.exec_rate 0.387880 # Inst execution rate +system.cpu.iew.wb_sent 9119 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8992 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4719 # num instructions producing a value +system.cpu.iew.wb_consumers 6404 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.374511 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736883 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 5259 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 381 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.551317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.413084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8938 76.96% 76.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1410 12.14% 89.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 462 3.98% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 240 2.07% 95.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 159 1.37% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 87 0.75% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.95% 98.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 46 0.40% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 162 1.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle +system.cpu.commit.count 6403 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 2050 # Number of memory references committed +system.cpu.commit.loads 1185 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 1051 # Number of branches committed +system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. +system.cpu.commit.int_insts 6321 # Number of committed integer instructions. +system.cpu.commit.function_calls 127 # Number of function calls committed. +system.cpu.commit.bw_lim_events 162 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 22763 # The number of ROB reads +system.cpu.rob.rob_writes 24313 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 6386 # Number of Instructions Simulated +system.cpu.committedInsts_total 6386 # Number of Instructions Simulated +system.cpu.cpi 3.759787 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.759787 # CPI: Total CPI of All Threads +system.cpu.ipc 0.265973 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.265973 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11830 # number of integer regfile reads +system.cpu.int_regfile_writes 6732 # number of integer regfile writes +system.cpu.fp_regfile_reads 8 # number of floating regfile reads +system.cpu.fp_regfile_writes 2 # number of floating regfile writes +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 160.112304 # Cycle average of tags in use +system.cpu.icache.total_refs 1606 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.147436 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 160.112304 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.078180 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1606 # number of ReadReq hits +system.cpu.icache.demand_hits 1606 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1606 # number of overall hits +system.cpu.icache.ReadReq_misses 433 # number of ReadReq misses +system.cpu.icache.demand_misses 433 # number of demand (read+write) misses +system.cpu.icache.overall_misses 433 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15431000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15431000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15431000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2039 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2039 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.212359 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.212359 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.212359 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35637.413395 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35637.413395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35637.413395 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 11021000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11021000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11021000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.153016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.153016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.153016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.717949 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35323.717949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35323.717949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 109.290272 # Cycle average of tags in use +system.cpu.dcache.total_refs 2154 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 109.290272 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits +system.cpu.dcache.demand_hits 2154 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2154 # number of overall hits +system.cpu.dcache.ReadReq_misses 154 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses +system.cpu.dcache.demand_misses 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5497500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 17965000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 17965000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1799 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 2664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2664 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.085603 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.191441 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.191441 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35698.051948 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35225.490196 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35225.490196 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 336 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6266000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6266000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056142 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.065315 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.065315 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36183.168317 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36011.494253 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36011.494253 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 221.643066 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 412 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 221.643066 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006764 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 485 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 14163000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16676500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16676500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 413 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997579 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.997942 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997942 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34376.213592 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34384.536082 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34384.536082 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12850000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15136000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15136000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997579 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.997942 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.997942 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.320388 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini new file mode 100644 index 000000000..df86e7077 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -0,0 +1,102 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout new file mode 100755 index 000000000..9f50fe960 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 04:58:59 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 3215000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..7ceb6a8be --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -0,0 +1,77 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 3215000 # Number of ticks simulated +final_tick 3215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 76916 # Simulator instruction rate (inst/s) +host_tick_rate 38606134 # Simulator tick rate (ticks/s) +host_mem_usage 198176 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +sim_insts 6404 # Number of instructions simulated +system.physmem.bytes_read 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written 6696 # Number of bytes written to this memory +system.physmem.num_reads 7599 # Number of read requests responded to by this memory +system.physmem.num_writes 865 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 10718506998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 7980093313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 2082737170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 12801244168 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6414 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6431 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 6431 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 6431 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini new file mode 100644 index 000000000..b9fd9c5f2 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -0,0 +1,327 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +mem_mode=timing +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=2 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +to_mem_ctrl_latency=1 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L1DcacheMemory L1IcacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory +buffer_size=0 +cntrl_id=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +cntrl_id=1 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=false +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l2_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers2 +latency=1 +link_id=2 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=3 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=4 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=5 +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats new file mode 100644 index 000000000..c2d3c97af --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -0,0 +1,641 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, unordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered +virtual_net_3: inactive +virtual_net_4: inactive +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/23/2012 04:21:55 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 2 +Elapsed_time_in_minutes: 0.0333333 +Elapsed_time_in_hours: 0.000555556 +Elapsed_time_in_days: 2.31481e-05 + +Virtual_time_in_seconds: 0.38 +Virtual_time_in_minutes: 0.00633333 +Virtual_time_in_hours: 0.000105556 +Virtual_time_in_days: 4.39815e-06 + +Ruby_current_time: 279353 +Ruby_start_time: 0 +Ruby_cycles: 279353 + +mbytes_resident: 45.5547 +mbytes_total: 214.371 +resident_ratio: 0.212504 + +ruby_cycles_executed: [ 279354 ] + +Busy Controller Counts: +L1Cache-0:0 +L2Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 295 count: 6414 average: 20.8227 | standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 297 count: 8464 average: 32.0048 | standard deviation: 63.6079 | 0 6974 0 0 0 0 0 0 0 29 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118 380 227 310 190 17 40 4 7 11 8 23 23 28 22 21 12 0 0 0 2 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 3 3 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_LD_NULL: [binsize: 2 max: 287 count: 1185 average: 83.8878 | standard deviation: 84.2176 | 0 602 0 0 0 0 0 0 0 12 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 155 70 110 81 8 29 3 2 5 2 9 4 12 7 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 297 count: 865 average: 43.8439 | standard deviation: 73.6087 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 35 63 19 18 8 4 0 0 1 1 3 15 1 3 16 4 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 2 max: 295 count: 6414 average: 20.8227 | standard deviation: 51.5606 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 190 94 181 91 1 7 1 5 5 5 11 4 15 12 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 20 count: 9645 average: 0.064282 | standard deviation: 0.540462 | 9495 0 1 0 147 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 6920 average: 0.000289017 | standard deviation: 0.0240441 | 6919 0 1 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 2725 average: 0.226789 | standard deviation: 0.997795 | 2576 0 0 0 147 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 5879 average: 0.000340194 | standard deviation: 0.0260865 | 5878 0 1 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 11862 +page_faults: 127 +swaps: 0 +block_inputs: 22816 +block_outputs: 96 + +Network Stats +------------- + +total_msg_count_Control: 8850 70800 +total_msg_count_Request_Control: 3123 24984 +total_msg_count_Response_Data: 9681 697032 +total_msg_count_Response_Control: 14286 114288 +total_msg_count_Writeback_Data: 864 62208 +total_msg_count_Writeback_Control: 867 6936 +total_msgs: 37671 total_bytes: 976248 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 1.87549 + links_utilized_percent_switch_0_link_0: 2.66455 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 1.08644 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 1699 13592 [ 0 900 799 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 3.64029 + links_utilized_percent_switch_1_link_0: 3.69819 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 3.58239 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1767 127224 [ 0 1767 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1611 12888 [ 0 1611 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 1.76479 + links_utilized_percent_switch_2_link_0: 0.917835 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 2.61175 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1452 11616 [ 0 1452 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 3 +switch_3_outlinks: 3 +links_utilized_percent_switch_3: 2.42686 + links_utilized_percent_switch_3_link_0: 2.66455 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 3.69819 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.917835 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 691 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 691 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% + + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 691 100% + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 799 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 799 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 72.9662% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 27.0338% + + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 799 100% + + --- L1Cache --- + - Event Counts - +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +Inv [1041 ] 1041 +L1_Replacement [1354 ] 1354 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_GET_INSTR [0 ] 0 +Data [0 ] 0 +Data_Exclusive [583 ] 583 +DataS_fromL1 [0 ] 0 +Data_all_Acks [907 ] 907 +Ack [0 ] 0 +Ack_all [0 ] 0 +WB_Ack [436 ] 436 + + - Transitions - +NP Load [525 ] 525 +NP Ifetch [646 ] 646 +NP Store [191 ] 191 +NP Inv [356 ] 356 +NP L1_Replacement [0 ] 0 + +I Load [58 ] 58 +I Ifetch [45 ] 45 +I Store [25 ] 25 +I Inv [0 ] 0 +I L1_Replacement [556 ] 556 + +S Load [0 ] 0 +S Ifetch [5723 ] 5723 +S Store [0 ] 0 +S Inv [325 ] 325 +S L1_Replacement [362 ] 362 + +E Load [454 ] 454 +E Ifetch [0 ] 0 +E Store [71 ] 71 +E Inv [219 ] 219 +E L1_Replacement [291 ] 291 +E Fwd_GETX [0 ] 0 +E Fwd_GETS [0 ] 0 +E Fwd_GET_INSTR [0 ] 0 + +M Load [148 ] 148 +M Ifetch [0 ] 0 +M Store [578 ] 578 +M Inv [141 ] 141 +M L1_Replacement [145 ] 145 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_GET_INSTR [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Inv [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Exclusive [583 ] 583 +IS DataS_fromL1 [0 ] 0 +IS Data_all_Acks [691 ] 691 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Inv [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data [0 ] 0 +IM Data_all_Acks [216 ] 216 +IM Ack [0 ] 0 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Inv [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Ack [0 ] 0 +SM Ack_all [0 ] 0 + +IS_I Load [0 ] 0 +IS_I Ifetch [0 ] 0 +IS_I Store [0 ] 0 +IS_I Inv [0 ] 0 +IS_I L1_Replacement [0 ] 0 +IS_I Data_Exclusive [0 ] 0 +IS_I DataS_fromL1 [0 ] 0 +IS_I Data_all_Acks [0 ] 0 + +M_I Load [0 ] 0 +M_I Ifetch [0 ] 0 +M_I Store [0 ] 0 +M_I Inv [0 ] 0 +M_I L1_Replacement [0 ] 0 +M_I Fwd_GETX [0 ] 0 +M_I Fwd_GETS [0 ] 0 +M_I Fwd_GET_INSTR [0 ] 0 +M_I WB_Ack [436 ] 436 + +E_I Load [0 ] 0 +E_I Ifetch [0 ] 0 +E_I Store [0 ] 0 +E_I L1_Replacement [0 ] 0 + +SINK_WB_ACK Load [0 ] 0 +SINK_WB_ACK Ifetch [0 ] 0 +SINK_WB_ACK Store [0 ] 0 +SINK_WB_ACK Inv [0 ] 0 +SINK_WB_ACK L1_Replacement [0 ] 0 +SINK_WB_ACK WB_Ack [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 1460 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1460 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 39.0411% + system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 46.9863% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 13.9726% + + system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 1460 100% + + --- L2Cache --- + - Event Counts - +L1_GET_INSTR [691 ] 691 +L1_GETS [586 ] 586 +L1_GETX [216 ] 216 +L1_UPGRADE [0 ] 0 +L1_PUTX [436 ] 436 +L1_PUTX_old [0 ] 0 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [142 ] 142 +L2_Replacement_clean [1310 ] 1310 +Mem_Data [1460 ] 1460 +Mem_Ack [1452 ] 1452 +WB_Data [141 ] 141 +WB_Data_clean [0 ] 0 +Ack [0 ] 0 +Ack_all [900 ] 900 +Unblock [0 ] 0 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [799 ] 799 +MEM_Inv [0 ] 0 + + - Transitions - +NP L1_GET_INSTR [686 ] 686 +NP L1_GETS [570 ] 570 +NP L1_GETX [204 ] 204 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [0 ] 0 + +SS L1_GET_INSTR [5 ] 5 +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_UPGRADE [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L2_Replacement_clean [681 ] 681 +SS MEM_Inv [0 ] 0 + +M L1_GET_INSTR [0 ] 0 +M L1_GETS [13 ] 13 +M L1_GETX [12 ] 12 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [134 ] 134 +M L2_Replacement_clean [277 ] 277 +M MEM_Inv [0 ] 0 + +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [0 ] 0 +MT L1_GETX [0 ] 0 +MT L1_PUTX [436 ] 436 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [8 ] 8 +MT L2_Replacement_clean [352 ] 352 +MT MEM_Inv [0 ] 0 + +M_I L1_GET_INSTR [0 ] 0 +M_I L1_GETS [3 ] 3 +M_I L1_GETX [0 ] 0 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [0 ] 0 +M_I Mem_Ack [1452 ] 1452 +M_I MEM_Inv [0 ] 0 + +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [6 ] 6 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [2 ] 2 +MT_I MEM_Inv [0 ] 0 + +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [0 ] 0 +MCT_I WB_Data [135 ] 135 +MCT_I WB_Data_clean [0 ] 0 +MCT_I Ack_all [217 ] 217 + +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [681 ] 681 + +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [0 ] 0 +S_I MEM_Inv [0 ] 0 + +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [0 ] 0 +ISS L1_GETX [0 ] 0 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [0 ] 0 +ISS Mem_Data [570 ] 570 +ISS MEM_Inv [0 ] 0 + +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [0 ] 0 +IS L1_GETX [0 ] 0 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [0 ] 0 +IS Mem_Data [686 ] 686 +IS MEM_Inv [0 ] 0 + +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [0 ] 0 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [0 ] 0 +IM Mem_Data [204 ] 204 +IM MEM_Inv [0 ] 0 + +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [0 ] 0 +SS_MB L1_GETX [0 ] 0 +SS_MB L1_UPGRADE [0 ] 0 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [0 ] 0 +SS_MB MEM_Inv [0 ] 0 + +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [0 ] 0 +MT_MB L1_GETX [0 ] 0 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [0 ] 0 +MT_MB L1_PUTX_old [0 ] 0 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [0 ] 0 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [799 ] 799 +MT_MB MEM_Inv [0 ] 0 + +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 + +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [0 ] 0 +MT_IIB L1_GETX [0 ] 0 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [0 ] 0 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 + +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 + +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [0 ] 0 +MT_SB L1_GETX [0 ] 0 +MT_SB L1_UPGRADE [0 ] 0 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [0 ] 0 +MT_SB MEM_Inv [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1737 + memory_reads: 1460 + memory_writes: 277 + memory_refreshes: 582 + memory_total_request_delays: 821 + memory_delays_per_request: 0.472654 + memory_delays_in_input_queue: 84 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 737 + memory_stalls_for_bank_busy: 197 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 40 + memory_stalls_for_bus: 242 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 258 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61 + + --- Directory --- + - Event Counts - +Fetch [1460 ] 1460 +Data [277 ] 277 +Memory_Data [1460 ] 1460 +Memory_Ack [277 ] 277 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [1175 ] 1175 + + - Transitions - +I Fetch [1460 ] 1460 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 + +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 + +M Data [277 ] 277 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [1175 ] 1175 + +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [1460 ] 1460 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 + +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [277 ] 277 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 + +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 + +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 + +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE [0 ] 0 + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout new file mode 100755 index 000000000..c93c8f8af --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 03:44:57 +gem5 started Jan 23 2012 04:21:53 +gem5 executing on zizzer +command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 279353 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt new file mode 100644 index 000000000..3bba58631 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -0,0 +1,77 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000279 # Number of seconds simulated +sim_ticks 279353 # Number of ticks simulated +final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 2836 # Simulator instruction rate (inst/s) +host_tick_rate 123728 # Simulator tick rate (ticks/s) +host_mem_usage 219520 # Number of bytes of host memory used +host_seconds 2.26 # Real time elapsed on the host +sim_insts 6404 # Number of instructions simulated +system.physmem.bytes_read 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written 6696 # Number of bytes written to this memory +system.physmem.num_reads 7599 # Number of read requests responded to by this memory +system.physmem.num_writes 865 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 123356470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 91840789 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 23969673 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 147326143 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6415 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6432 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 279353 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 279353 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini new file mode 100644 index 000000000..607ab419c --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -0,0 +1,323 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +mem_mode=timing +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=2 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L1DcacheMemory L1IcacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory +buffer_size=0 +cntrl_id=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +cntrl_id=1 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=false +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l2_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers2 +latency=1 +link_id=2 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=3 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=4 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=5 +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats new file mode 100644 index 000000000..03b0eda65 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -0,0 +1,1470 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, unordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered +virtual_net_3: inactive +virtual_net_4: inactive +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/23/2012 04:22:13 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 + +Virtual_time_in_seconds: 0.39 +Virtual_time_in_minutes: 0.0065 +Virtual_time_in_hours: 0.000108333 +Virtual_time_in_days: 4.51389e-06 + +Ruby_current_time: 223694 +Ruby_start_time: 0 +Ruby_cycles: 223694 + +mbytes_resident: 45.5586 +mbytes_total: 214.484 +resident_ratio: 0.21241 + +ruby_cycles_executed: [ 223695 ] + +Busy Controller Counts: +L2Cache-0:0 +L1Cache-0:0 + +Directory-0:0 + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4289 | standard deviation: 56.47 | 0 7102 0 0 0 0 0 0 0 164 89 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 243 195 220 185 167 17 4 19 5 3 3 5 21 6 1 2 1 0 0 0 0 1 0 0 0 0 0 3 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 259 count: 1185 average: 62.8405 | standard deviation: 79.0945 | 0 660 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95 54 83 83 64 4 1 2 2 1 3 3 5 6 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 233 count: 865 average: 29.4509 | standard deviation: 59.7812 | 0 674 0 0 0 0 0 0 0 0 61 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 41 10 37 6 1 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9746 | standard deviation: 47.4906 | 0 5768 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148 110 96 92 66 7 2 16 3 2 0 2 14 0 1 2 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 276 count: 8464 average: 25.4289 | standard deviation: 56.47 | 0 7102 0 0 0 0 0 0 0 164 89 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 243 195 220 185 167 17 4 19 5 3 3 5 21 6 1 2 1 0 0 0 0 1 0 0 0 0 0 3 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_LD_NULL: [binsize: 2 max: 259 count: 1185 average: 62.8405 | standard deviation: 79.0945 | 0 660 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95 54 83 83 64 4 1 2 2 1 3 3 5 6 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 233 count: 865 average: 29.4509 | standard deviation: 59.7812 | 0 674 0 0 0 0 0 0 0 0 61 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 41 10 37 6 1 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9746 | standard deviation: 47.4906 | 0 5768 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148 110 96 92 66 7 2 16 3 2 0 2 14 0 1 2 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 11886 +page_faults: 121 +swaps: 0 +block_inputs: 21600 +block_outputs: 88 + +Network Stats +------------- + +total_msg_count_Request_Control: 7413 59304 +total_msg_count_Response_Data: 6654 479088 +total_msg_count_ResponseL2hit_Data: 759 54648 +total_msg_count_Writeback_Data: 4644 334368 +total_msg_count_Writeback_Control: 17379 139032 +total_msg_count_Unblock_Control: 7413 59304 +total_msgs: 44262 total_bytes: 1125744 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 5.24221 + links_utilized_percent_switch_0_link_0: 6.11058 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 4.37383 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 2447 19576 [ 1354 1093 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 1109 8872 [ 0 1109 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 253 18216 [ 0 0 253 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 3346 26768 [ 1354 1093 899 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 1109 8872 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 3.33894 + links_utilized_percent_switch_1_link_0: 3.04255 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 3.63532 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 253 18216 [ 0 0 253 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 1.90327 + links_utilized_percent_switch_2_link_0: 1.33128 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 2.47526 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 1109 8872 [ 0 1109 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1992 15936 [ 0 1093 899 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Unblock_Control: 1109 8872 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 1093 8744 [ 0 1093 0 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 3 +switch_3_outlinks: 3 +links_utilized_percent_switch_3: 3.4948 + links_utilized_percent_switch_3_link_0: 6.11058 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 3.04255 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 1.33128 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 2447 19576 [ 1354 1093 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseL2hit_Data: 253 18216 [ 0 0 253 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 1109 8872 [ 0 1109 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 1992 15936 [ 0 1093 899 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Unblock_Control: 1109 8872 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + + --- L1Cache --- + - Event Counts - +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +L1_Replacement [1379 ] 1379 +Own_GETX [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Inv [0 ] 0 +Ack [0 ] 0 +Data [0 ] 0 +Exclusive_Data [1362 ] 1362 +Writeback_Ack [0 ] 0 +Writeback_Ack_Data [1354 ] 1354 +Writeback_Nack [0 ] 0 +All_acks [191 ] 191 +Use_Timeout [1361 ] 1361 + + - Transitions - +I Load [525 ] 525 +I Ifetch [646 ] 646 +I Store [191 ] 191 +I L1_Replacement [0 ] 0 +I Inv [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L1_Replacement [0 ] 0 +S Fwd_GETS [0 ] 0 +S Fwd_DMA [0 ] 0 +S Inv [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L1_Replacement [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 + +M Load [307 ] 307 +M Ifetch [3481 ] 3481 +M Store [51 ] 51 +M L1_Replacement [1086 ] 1086 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 + +M_W Load [112 ] 112 +M_W Ifetch [2287 ] 2287 +M_W Store [27 ] 27 +M_W L1_Replacement [17 ] 17 +M_W Own_GETX [0 ] 0 +M_W Fwd_GETX [0 ] 0 +M_W Fwd_GETS [0 ] 0 +M_W Fwd_DMA [0 ] 0 +M_W Inv [0 ] 0 +M_W Use_Timeout [1143 ] 1143 + +MM Load [234 ] 234 +MM Ifetch [0 ] 0 +MM Store [339 ] 339 +MM L1_Replacement [268 ] 268 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 + +MM_W Load [7 ] 7 +MM_W Ifetch [0 ] 0 +MM_W Store [257 ] 257 +MM_W L1_Replacement [8 ] 8 +MM_W Own_GETX [0 ] 0 +MM_W Fwd_GETX [0 ] 0 +MM_W Fwd_GETS [0 ] 0 +MM_W Fwd_DMA [0 ] 0 +MM_W Inv [0 ] 0 +MM_W Use_Timeout [218 ] 218 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Inv [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [191 ] 191 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Fwd_GETS [0 ] 0 +SM Fwd_DMA [0 ] 0 +SM Inv [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Own_GETX [0 ] 0 +OM Fwd_GETX [0 ] 0 +OM Fwd_GETS [0 ] 0 +OM Fwd_DMA [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [191 ] 191 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Inv [0 ] 0 +IS Data [0 ] 0 +IS Exclusive_Data [1171 ] 1171 + +SI Load [0 ] 0 +SI Ifetch [0 ] 0 +SI Store [0 ] 0 +SI L1_Replacement [0 ] 0 +SI Fwd_GETS [0 ] 0 +SI Fwd_DMA [0 ] 0 +SI Inv [0 ] 0 +SI Writeback_Ack [0 ] 0 +SI Writeback_Ack_Data [0 ] 0 +SI Writeback_Nack [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L1_Replacement [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Ack_Data [0 ] 0 +OI Writeback_Nack [0 ] 0 + +MI Load [0 ] 0 +MI Ifetch [0 ] 0 +MI Store [0 ] 0 +MI L1_Replacement [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI Writeback_Ack_Data [1354 ] 1354 +MI Writeback_Nack [0 ] 0 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L1_Replacement [0 ] 0 +II Inv [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Ack_Data [0 ] 0 +II Writeback_Nack [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- + - Event Counts - +L1_GETS [1171 ] 1171 +L1_GETX [191 ] 191 +L1_PUTO [0 ] 0 +L1_PUTX [1354 ] 1354 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [130 ] 130 +Data [130 ] 130 +Data_Exclusive [979 ] 979 +L1_WBCLEANDATA [1058 ] 1058 +L1_WBDIRTYDATA [296 ] 296 +Writeback_Ack [1093 ] 1093 +Writeback_Nack [0 ] 0 +Unblock [0 ] 0 +Exclusive_Unblock [1362 ] 1362 +DmaAck [0 ] 0 +L2_Replacement [1093 ] 1093 + + - Transitions - +NP L1_GETS [979 ] 979 +NP L1_GETX [130 ] 130 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 + +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 + +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 + +ILX L1_GETS [0 ] 0 +ILX L1_GETX [0 ] 0 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [1354 ] 1354 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 + +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 + +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 + +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 + +ILOSX L1_GETS [0 ] 0 +ILOSX L1_GETX [0 ] 0 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 + +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 + +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 + +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 + +M L1_GETS [192 ] 192 +M L1_GETX [61 ] 61 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [1093 ] 1093 + +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 + +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 + +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 + +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 + +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 + +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 + +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 + +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 + +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 + +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 + +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 + +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 + +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 + +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 + +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 + +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 + +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 + +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 + +ILXW L1_GETS [0 ] 0 +ILXW L1_GETX [0 ] 0 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [1058 ] 1058 +ILXW L1_WBDIRTYDATA [296 ] 296 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 + +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 + +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 + +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 + +IFLOXX L1_GETS [0 ] 0 +IFLOXX L1_GETX [0 ] 0 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [0 ] 0 +IFLOXX Exclusive_Unblock [0 ] 0 +IFLOXX L2_Replacement [0 ] 0 + +IFLOSX L1_GETS [0 ] 0 +IFLOSX L1_GETX [0 ] 0 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [0 ] 0 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 + +IFLXO L1_GETS [0 ] 0 +IFLXO L1_GETX [0 ] 0 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [0 ] 0 +IFLXO L2_Replacement [0 ] 0 + +IGS L1_GETS [0 ] 0 +IGS L1_GETX [0 ] 0 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [0 ] 0 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [979 ] 979 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [979 ] 979 +IGS L2_Replacement [0 ] 0 + +IGM L1_GETS [0 ] 0 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [130 ] 130 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 + +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 + +IGMO L1_GETS [0 ] 0 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [0 ] 0 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [130 ] 130 +IGMO Exclusive_Unblock [130 ] 130 +IGMO L2_Replacement [0 ] 0 + +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 + +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 + +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 + +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 + +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 + +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 + +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [0 ] 0 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [61 ] 61 +MM L2_Replacement [0 ] 0 + +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 + +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [192 ] 192 +OO L2_Replacement [0 ] 0 + +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 + +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 + +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 + +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 + +MI L1_GETS [0 ] 0 +MI L1_GETX [0 ] 0 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [1093 ] 1093 +MI L2_Replacement [0 ] 0 + +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 + +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 + +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 + +ILOSD L1_GETS [0 ] 0 +ILOSD L1_GETX [0 ] 0 +ILOSD L1_PUTO [0 ] 0 +ILOSD L1_PUTX [0 ] 0 +ILOSD L1_PUTS_only [0 ] 0 +ILOSD L1_PUTS [0 ] 0 +ILOSD Fwd_GETX [0 ] 0 +ILOSD Fwd_GETS [0 ] 0 +ILOSD Fwd_DMA [0 ] 0 +ILOSD Own_GETX [0 ] 0 +ILOSD Inv [0 ] 0 +ILOSD DmaAck [0 ] 0 +ILOSD L2_Replacement [0 ] 0 + +ILOSXD L1_GETS [0 ] 0 +ILOSXD L1_GETX [0 ] 0 +ILOSXD L1_PUTO [0 ] 0 +ILOSXD L1_PUTX [0 ] 0 +ILOSXD L1_PUTS_only [0 ] 0 +ILOSXD L1_PUTS [0 ] 0 +ILOSXD Fwd_GETX [0 ] 0 +ILOSXD Fwd_GETS [0 ] 0 +ILOSXD Fwd_DMA [0 ] 0 +ILOSXD Own_GETX [0 ] 0 +ILOSXD Inv [0 ] 0 +ILOSXD DmaAck [0 ] 0 +ILOSXD L2_Replacement [0 ] 0 + +ILOD L1_GETS [0 ] 0 +ILOD L1_GETX [0 ] 0 +ILOD L1_PUTO [0 ] 0 +ILOD L1_PUTX [0 ] 0 +ILOD L1_PUTS_only [0 ] 0 +ILOD L1_PUTS [0 ] 0 +ILOD Fwd_GETX [0 ] 0 +ILOD Fwd_GETS [0 ] 0 +ILOD Fwd_DMA [0 ] 0 +ILOD Own_GETX [0 ] 0 +ILOD Inv [0 ] 0 +ILOD DmaAck [0 ] 0 +ILOD L2_Replacement [0 ] 0 + +ILXD L1_GETS [0 ] 0 +ILXD L1_GETX [0 ] 0 +ILXD L1_PUTO [0 ] 0 +ILXD L1_PUTX [0 ] 0 +ILXD L1_PUTS_only [0 ] 0 +ILXD L1_PUTS [0 ] 0 +ILXD Fwd_GETX [0 ] 0 +ILXD Fwd_GETS [0 ] 0 +ILXD Fwd_DMA [0 ] 0 +ILXD Own_GETX [0 ] 0 +ILXD Inv [0 ] 0 +ILXD DmaAck [0 ] 0 +ILXD L2_Replacement [0 ] 0 + +ILOXD L1_GETS [0 ] 0 +ILOXD L1_GETX [0 ] 0 +ILOXD L1_PUTO [0 ] 0 +ILOXD L1_PUTX [0 ] 0 +ILOXD L1_PUTS_only [0 ] 0 +ILOXD L1_PUTS [0 ] 0 +ILOXD Fwd_GETX [0 ] 0 +ILOXD Fwd_GETS [0 ] 0 +ILOXD Fwd_DMA [0 ] 0 +ILOXD Own_GETX [0 ] 0 +ILOXD Inv [0 ] 0 +ILOXD DmaAck [0 ] 0 +ILOXD L2_Replacement [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1303 + memory_reads: 1109 + memory_writes: 194 + memory_refreshes: 466 + memory_total_request_delays: 279 + memory_delays_per_request: 0.214121 + memory_delays_in_input_queue: 12 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 267 + memory_stalls_for_bank_busy: 123 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 16 + memory_stalls_for_bus: 58 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 70 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 74 17 45 40 54 99 29 16 19 22 31 34 52 48 38 30 39 21 21 27 28 37 55 22 31 21 32 69 84 103 13 52 + + --- Directory --- + - Event Counts - +GETX [130 ] 130 +GETS [979 ] 979 +PUTX [1093 ] 1093 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [1109 ] 1109 +Clean_Writeback [899 ] 899 +Dirty_Writeback [194 ] 194 +Memory_Data [1109 ] 1109 +Memory_Ack [194 ] 194 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_ACK [0 ] 0 +Data [0 ] 0 + + - Transitions - +I GETX [130 ] 130 +I GETS [979 ] 979 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [190 ] 190 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [1093 ] 1093 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [979 ] 979 +IS Memory_Data [979 ] 979 +IS Memory_Ack [3 ] 3 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 + +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 + +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 + +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 + +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [130 ] 130 +MM Memory_Data [130 ] 130 +MM Memory_Ack [1 ] 1 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 + + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [899 ] 899 +MI Dirty_Writeback [194 ] 194 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 + +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 + +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 + +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 + +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 + +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 + +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data [0 ] 0 + +OD GETX [0 ] 0 +OD GETS [0 ] 0 +OD PUTX [0 ] 0 +OD PUTO [0 ] 0 +OD PUTO_SHARERS [0 ] 0 +OD DMA_READ [0 ] 0 +OD DMA_WRITE [0 ] 0 +OD DMA_ACK [0 ] 0 + +MD GETX [0 ] 0 +MD GETS [0 ] 0 +MD PUTX [0 ] 0 +MD PUTO [0 ] 0 +MD PUTO_SHARERS [0 ] 0 +MD DMA_READ [0 ] 0 +MD DMA_WRITE [0 ] 0 +MD DMA_ACK [0 ] 0 + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout new file mode 100755 index 000000000..ed47704f6 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 03:47:36 +gem5 started Jan 23 2012 04:22:12 +gem5 executing on zizzer +command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 223694 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt new file mode 100644 index 000000000..44a6426b2 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -0,0 +1,77 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000224 # Number of seconds simulated +sim_ticks 223694 # Number of ticks simulated +final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 19611 # Simulator instruction rate (inst/s) +host_tick_rate 684980 # Simulator tick rate (ticks/s) +host_mem_usage 219636 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host +sim_insts 6404 # Number of instructions simulated +system.physmem.bytes_read 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written 6696 # Number of bytes written to this memory +system.physmem.num_reads 7599 # Number of read requests responded to by this memory +system.physmem.num_writes 865 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 154049729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 114692392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 29933749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 183983477 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6415 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6432 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 223694 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 223694 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini new file mode 100644 index 000000000..e664ed4cf --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -0,0 +1,334 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +mem_mode=timing +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=2 +directory=system.dir_cntrl0.directory +directory_latency=5 +distributed_persistent=true +fixed_timeout_latency=100 +l2_select_num_bits=0 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L1DcacheMemory L1IcacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory +N_tokens=2 +buffer_size=0 +cntrl_id=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +N_tokens=2 +buffer_size=0 +cntrl_id=1 +filtering_enabled=true +l2_request_latency=5 +l2_response_latency=5 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=false +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l2_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers2 +latency=1 +link_id=2 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=3 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=4 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=5 +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats new file mode 100644 index 000000000..216172e7b --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -0,0 +1,1043 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, ordered +virtual_net_1: active, unordered +virtual_net_2: active, unordered +virtual_net_3: active, ordered +virtual_net_4: active, unordered +virtual_net_5: active, ordered +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/23/2012 04:22:26 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 + +Virtual_time_in_seconds: 0.31 +Virtual_time_in_minutes: 0.00516667 +Virtual_time_in_hours: 8.61111e-05 +Virtual_time_in_days: 3.58796e-06 + +Ruby_current_time: 231701 +Ruby_start_time: 0 +Ruby_cycles: 231701 + +mbytes_resident: 44.0234 +mbytes_total: 212.691 +resident_ratio: 0.206983 + +ruby_cycles_executed: [ 231702 ] + +Busy Controller Counts: +L1Cache-0:0 +L2Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 2 max: 326 count: 8464 average: 26.3749 | standard deviation: 59.7716 | 0 7082 0 0 0 0 0 0 0 0 21 3 180 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 7 156 141 316 165 138 16 4 6 35 30 41 24 40 3 1 2 4 3 0 2 2 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 3 0 0 0 0 0 0 0 1 0 0 1 20 0 3 2 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 326 count: 1185 average: 65.011 | standard deviation: 81.2899 | 0 660 0 0 0 0 0 0 0 0 3 2 95 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 55 33 124 68 56 0 2 3 11 11 7 12 19 3 1 1 3 2 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 321 count: 865 average: 39.3988 | standard deviation: 76.4664 | 0 654 0 0 0 0 0 0 0 0 17 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 17 11 29 14 36 1 0 1 1 6 23 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 18 0 2 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.4804 | standard deviation: 48.2606 | 0 5768 0 0 0 0 0 0 0 0 1 1 59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 84 97 163 83 46 15 2 2 23 13 11 12 20 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 7082 average: 2 | standard deviation: 0 | 0 0 7082 ] +miss_latency_L2Cache: [binsize: 1 max: 25 count: 204 average: 24.5441 | standard deviation: 1.24963 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 2 1 1 179 ] +miss_latency_Directory: [binsize: 2 max: 326 count: 1178 average: 173.231 | standard deviation: 22.9712 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 7 156 141 316 165 138 16 4 6 35 30 41 24 40 3 1 2 4 3 0 2 2 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 3 0 0 0 0 0 0 0 1 0 0 1 20 0 3 2 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 1177 +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 25 count: 100 average: 24.83 | standard deviation: 0.771984 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 1 0 95 ] +miss_latency_LD_Directory: [binsize: 2 max: 326 count: 425 average: 172.318 | standard deviation: 18.6969 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 55 33 124 68 56 0 2 3 11 11 7 12 19 3 1 1 3 2 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 654 average: 2 | standard deviation: 0 | 0 0 654 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 25 count: 43 average: 23.4186 | standard deviation: 1.98206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 26 ] +miss_latency_ST_Directory: [binsize: 2 max: 321 count: 168 average: 189.077 | standard deviation: 46.5714 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 17 11 29 14 36 1 0 1 1 6 23 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 18 0 2 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 25 count: 61 average: 24.8689 | standard deviation: 0.645497 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 58 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 276 count: 585 average: 169.344 | standard deviation: 10.0739 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 84 97 163 83 46 15 2 2 23 13 11 12 20 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 11434 +page_faults: 122 +swaps: 0 +block_inputs: 21928 +block_outputs: 104 + +Network Stats +------------- + +total_msg_count_Request_Control: 7731 61848 +total_msg_count_Response_Data: 3534 254448 +total_msg_count_ResponseL2hit_Data: 612 44064 +total_msg_count_Response_Control: 3 24 +total_msg_count_Writeback_Data: 4749 341928 +total_msg_count_Writeback_Control: 2901 23208 +total_msg_count_Persistent_Control: 240 1920 +total_msgs: 19770 total_bytes: 727440 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 2.81473 + links_utilized_percent_switch_0_link_0: 2.69291 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 2.93654 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 1178 84816 [ 0 0 0 0 1178 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 1382 11056 [ 0 1382 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 2.12213 + links_utilized_percent_switch_1_link_0: 2.93654 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 1.30772 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 1382 11056 [ 0 1382 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 1195 9560 [ 0 0 1195 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 229 16488 [ 0 0 0 0 229 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 967 7736 [ 0 0 0 0 967 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 1.6039 + links_utilized_percent_switch_2_link_0: 0.919936 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 2.28786 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 1195 9560 [ 0 0 1195 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 229 16488 [ 0 0 0 0 229 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 967 7736 [ 0 0 0 0 967 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 1178 84816 [ 0 0 0 0 1178 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 3 +switch_3_outlinks: 3 +links_utilized_percent_switch_3: 2.18025 + links_utilized_percent_switch_3_link_0: 2.68428 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 2.93654 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.919936 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 1178 84816 [ 0 0 0 0 1178 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 1382 11056 [ 0 1382 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 1195 9560 [ 0 0 1195 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 229 16488 [ 0 0 0 0 229 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 967 7736 [ 0 0 0 0 967 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Persistent_Control: 40 320 [ 0 0 0 40 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 646 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% + + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 646 100% + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 736 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 736 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 71.3315% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 28.6685% + + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 736 100% + + --- L1Cache --- + - Event Counts - +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +Atomic [0 ] 0 +L1_Replacement [1364 ] 1364 +Data_Shared [161 ] 161 +Data_Owner [0 ] 0 +Data_All_Tokens [1221 ] 1221 +Ack [1 ] 1 +Ack_All_Tokens [0 ] 0 +Transient_GETX [0 ] 0 +Transient_Local_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_Local_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +Transient_Local_GETS_Last_Token [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [40 ] 40 +Request_Timeout [20 ] 20 +Use_TimeoutStarverX [0 ] 0 +Use_TimeoutStarverS [0 ] 0 +Use_TimeoutNoStarvers [1220 ] 1220 +Use_TimeoutNoStarvers_NoMig [0 ] 0 + + - Transitions - +NP Load [525 ] 525 +NP Ifetch [646 ] 646 +NP Store [191 ] 191 +NP Atomic [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_Local_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Transient_Local_GETS [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [0 ] 0 + +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Atomic [0 ] 0 +I L1_Replacement [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_Local_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_Local_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I Transient_Local_GETS_Last_Token [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S Load [153 ] 153 +S Ifetch [331 ] 331 +S Store [20 ] 20 +S Atomic [0 ] 0 +S L1_Replacement [141 ] 141 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_Local_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_Local_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S Transient_Local_GETS_Last_Token [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O Atomic [0 ] 0 +O L1_Replacement [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_Local_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_Local_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O Transient_Local_GETS_Last_Token [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M Load [186 ] 186 +M Ifetch [3322 ] 3322 +M Store [33 ] 33 +M Atomic [0 ] 0 +M L1_Replacement [945 ] 945 +M Transient_GETX [0 ] 0 +M Transient_Local_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M Transient_Local_GETS [0 ] 0 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [3 ] 3 + +MM Load [220 ] 220 +MM Ifetch [0 ] 0 +MM Store [330 ] 330 +MM Atomic [0 ] 0 +MM L1_Replacement [268 ] 268 +MM Transient_GETX [0 ] 0 +MM Transient_Local_GETX [0 ] 0 +MM Transient_GETS [0 ] 0 +MM Transient_Local_GETS [0 ] 0 +MM Persistent_GETX [0 ] 0 +MM Persistent_GETS [0 ] 0 +MM Own_Lock_or_Unlock [17 ] 17 + +M_W Load [80 ] 80 +M_W Ifetch [2115 ] 2115 +M_W Store [25 ] 25 +M_W Atomic [0 ] 0 +M_W L1_Replacement [6 ] 6 +M_W Transient_GETX [0 ] 0 +M_W Transient_Local_GETX [0 ] 0 +M_W Transient_GETS [0 ] 0 +M_W Transient_Local_GETS [0 ] 0 +M_W Persistent_GETX [0 ] 0 +M_W Persistent_GETS [0 ] 0 +M_W Own_Lock_or_Unlock [0 ] 0 +M_W Use_TimeoutStarverX [0 ] 0 +M_W Use_TimeoutStarverS [0 ] 0 +M_W Use_TimeoutNoStarvers [984 ] 984 +M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 + +MM_W Load [21 ] 21 +MM_W Ifetch [0 ] 0 +MM_W Store [266 ] 266 +MM_W Atomic [0 ] 0 +MM_W L1_Replacement [4 ] 4 +MM_W Transient_GETX [0 ] 0 +MM_W Transient_Local_GETX [0 ] 0 +MM_W Transient_GETS [0 ] 0 +MM_W Transient_Local_GETS [0 ] 0 +MM_W Persistent_GETX [0 ] 0 +MM_W Persistent_GETS [0 ] 0 +MM_W Own_Lock_or_Unlock [0 ] 0 +MM_W Use_TimeoutStarverX [0 ] 0 +MM_W Use_TimeoutStarverS [0 ] 0 +MM_W Use_TimeoutNoStarvers [236 ] 236 +MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Atomic [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data_Shared [0 ] 0 +IM Data_Owner [0 ] 0 +IM Data_All_Tokens [191 ] 191 +IM Ack [1 ] 1 +IM Transient_GETX [0 ] 0 +IM Transient_Local_GETX [0 ] 0 +IM Transient_GETS [0 ] 0 +IM Transient_Local_GETS [0 ] 0 +IM Transient_GETS_Last_Token [0 ] 0 +IM Transient_Local_GETS_Last_Token [0 ] 0 +IM Persistent_GETX [0 ] 0 +IM Persistent_GETS [0 ] 0 +IM Persistent_GETS_Last_Token [0 ] 0 +IM Own_Lock_or_Unlock [17 ] 17 +IM Request_Timeout [17 ] 17 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Atomic [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Data_Shared [0 ] 0 +SM Data_Owner [0 ] 0 +SM Data_All_Tokens [20 ] 20 +SM Ack [0 ] 0 +SM Transient_GETX [0 ] 0 +SM Transient_Local_GETX [0 ] 0 +SM Transient_GETS [0 ] 0 +SM Transient_Local_GETS [0 ] 0 +SM Transient_GETS_Last_Token [0 ] 0 +SM Transient_Local_GETS_Last_Token [0 ] 0 +SM Persistent_GETX [0 ] 0 +SM Persistent_GETS [0 ] 0 +SM Persistent_GETS_Last_Token [0 ] 0 +SM Own_Lock_or_Unlock [0 ] 0 +SM Request_Timeout [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM Atomic [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Data_Shared [0 ] 0 +OM Data_All_Tokens [0 ] 0 +OM Ack [0 ] 0 +OM Ack_All_Tokens [0 ] 0 +OM Transient_GETX [0 ] 0 +OM Transient_Local_GETX [0 ] 0 +OM Transient_GETS [0 ] 0 +OM Transient_Local_GETS [0 ] 0 +OM Transient_GETS_Last_Token [0 ] 0 +OM Transient_Local_GETS_Last_Token [0 ] 0 +OM Persistent_GETX [0 ] 0 +OM Persistent_GETS [0 ] 0 +OM Persistent_GETS_Last_Token [0 ] 0 +OM Own_Lock_or_Unlock [0 ] 0 +OM Request_Timeout [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Atomic [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Shared [161 ] 161 +IS Data_Owner [0 ] 0 +IS Data_All_Tokens [1010 ] 1010 +IS Ack [0 ] 0 +IS Transient_GETX [0 ] 0 +IS Transient_Local_GETX [0 ] 0 +IS Transient_GETS [0 ] 0 +IS Transient_Local_GETS [0 ] 0 +IS Transient_GETS_Last_Token [0 ] 0 +IS Transient_Local_GETS_Last_Token [0 ] 0 +IS Persistent_GETX [0 ] 0 +IS Persistent_GETS [0 ] 0 +IS Persistent_GETS_Last_Token [0 ] 0 +IS Own_Lock_or_Unlock [3 ] 3 +IS Request_Timeout [3 ] 3 + +I_L Load [0 ] 0 +I_L Ifetch [0 ] 0 +I_L Store [0 ] 0 +I_L Atomic [0 ] 0 +I_L L1_Replacement [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_Local_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_Local_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L Transient_Local_GETS_Last_Token [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Persistent_GETS_Last_Token [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 + +S_L Load [0 ] 0 +S_L Ifetch [0 ] 0 +S_L Store [0 ] 0 +S_L Atomic [0 ] 0 +S_L L1_Replacement [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_Local_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_Local_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L Transient_Local_GETS_Last_Token [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +IM_L Load [0 ] 0 +IM_L Ifetch [0 ] 0 +IM_L Store [0 ] 0 +IM_L Atomic [0 ] 0 +IM_L L1_Replacement [0 ] 0 +IM_L Data_Shared [0 ] 0 +IM_L Data_Owner [0 ] 0 +IM_L Data_All_Tokens [0 ] 0 +IM_L Ack [0 ] 0 +IM_L Transient_GETX [0 ] 0 +IM_L Transient_Local_GETX [0 ] 0 +IM_L Transient_GETS [0 ] 0 +IM_L Transient_Local_GETS [0 ] 0 +IM_L Transient_GETS_Last_Token [0 ] 0 +IM_L Transient_Local_GETS_Last_Token [0 ] 0 +IM_L Persistent_GETX [0 ] 0 +IM_L Persistent_GETS [0 ] 0 +IM_L Own_Lock_or_Unlock [0 ] 0 +IM_L Request_Timeout [0 ] 0 + +SM_L Load [0 ] 0 +SM_L Ifetch [0 ] 0 +SM_L Store [0 ] 0 +SM_L Atomic [0 ] 0 +SM_L L1_Replacement [0 ] 0 +SM_L Data_Shared [0 ] 0 +SM_L Data_Owner [0 ] 0 +SM_L Data_All_Tokens [0 ] 0 +SM_L Ack [0 ] 0 +SM_L Transient_GETX [0 ] 0 +SM_L Transient_Local_GETX [0 ] 0 +SM_L Transient_GETS [0 ] 0 +SM_L Transient_Local_GETS [0 ] 0 +SM_L Transient_GETS_Last_Token [0 ] 0 +SM_L Transient_Local_GETS_Last_Token [0 ] 0 +SM_L Persistent_GETX [0 ] 0 +SM_L Persistent_GETS [0 ] 0 +SM_L Persistent_GETS_Last_Token [0 ] 0 +SM_L Own_Lock_or_Unlock [0 ] 0 +SM_L Request_Timeout [0 ] 0 + +IS_L Load [0 ] 0 +IS_L Ifetch [0 ] 0 +IS_L Store [0 ] 0 +IS_L Atomic [0 ] 0 +IS_L L1_Replacement [0 ] 0 +IS_L Data_Shared [0 ] 0 +IS_L Data_Owner [0 ] 0 +IS_L Data_All_Tokens [0 ] 0 +IS_L Ack [0 ] 0 +IS_L Transient_GETX [0 ] 0 +IS_L Transient_Local_GETX [0 ] 0 +IS_L Transient_GETS [0 ] 0 +IS_L Transient_Local_GETS [0 ] 0 +IS_L Transient_GETS_Last_Token [0 ] 0 +IS_L Transient_Local_GETS_Last_Token [0 ] 0 +IS_L Persistent_GETX [0 ] 0 +IS_L Persistent_GETS [0 ] 0 +IS_L Own_Lock_or_Unlock [0 ] 0 +IS_L Request_Timeout [0 ] 0 + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 1195 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1195 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 84.5188% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 15.4812% + + system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 1195 100% + + --- L2Cache --- + - Event Counts - +L1_GETS [1122 ] 1122 +L1_GETS_Last_Token [49 ] 49 +L1_GETX [211 ] 211 +L1_INV [0 ] 0 +Transient_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +L2_Replacement [1265 ] 1265 +Writeback_Tokens [0 ] 0 +Writeback_Shared_Data [84 ] 84 +Writeback_All_Tokens [1270 ] 1270 +Writeback_Owned [0 ] 0 +Data_Shared [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Persistent_GETX [17 ] 17 +Persistent_GETS [3 ] 3 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [20 ] 20 + + - Transitions - +NP L1_GETS [1010 ] 1010 +NP L1_GETX [166 ] 166 +NP L1_INV [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Writeback_Tokens [0 ] 0 +NP Writeback_Shared_Data [81 ] 81 +NP Writeback_All_Tokens [1192 ] 1192 +NP Writeback_Owned [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [20 ] 20 + +I L1_GETS [0 ] 0 +I L1_GETS_Last_Token [0 ] 0 +I L1_GETX [1 ] 1 +I L1_INV [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I L2_Replacement [69 ] 69 +I Writeback_Tokens [0 ] 0 +I Writeback_Shared_Data [3 ] 3 +I Writeback_All_Tokens [21 ] 21 +I Writeback_Owned [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 + +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [49 ] 49 +S L1_GETX [1 ] 1 +S L1_INV [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S L2_Replacement [34 ] 34 +S Writeback_Tokens [0 ] 0 +S Writeback_Shared_Data [0 ] 0 +S Writeback_All_Tokens [0 ] 0 +S Writeback_Owned [0 ] 0 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 + +O L1_GETS [0 ] 0 +O L1_GETS_Last_Token [0 ] 0 +O L1_GETX [17 ] 17 +O L1_INV [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O L2_Replacement [38 ] 38 +O Writeback_Tokens [0 ] 0 +O Writeback_Shared_Data [0 ] 0 +O Writeback_All_Tokens [57 ] 57 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 + +M L1_GETS [112 ] 112 +M L1_GETX [26 ] 26 +M L1_INV [0 ] 0 +M Transient_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M L2_Replacement [1124 ] 1124 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 + +I_L L1_GETS [0 ] 0 +I_L L1_GETX [0 ] 0 +I_L L1_INV [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L L2_Replacement [0 ] 0 +I_L Writeback_Tokens [0 ] 0 +I_L Writeback_Shared_Data [0 ] 0 +I_L Writeback_All_Tokens [0 ] 0 +I_L Writeback_Owned [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Persistent_GETX [17 ] 17 +I_L Persistent_GETS [3 ] 3 +I_L Own_Lock_or_Unlock [0 ] 0 + +S_L L1_GETS [0 ] 0 +S_L L1_GETS_Last_Token [0 ] 0 +S_L L1_GETX [0 ] 0 +S_L L1_INV [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L L2_Replacement [0 ] 0 +S_L Writeback_Tokens [0 ] 0 +S_L Writeback_Shared_Data [0 ] 0 +S_L Writeback_All_Tokens [0 ] 0 +S_L Writeback_Owned [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1407 + memory_reads: 1178 + memory_writes: 229 + memory_refreshes: 483 + memory_total_request_delays: 396 + memory_delays_per_request: 0.28145 + memory_delays_in_input_queue: 112 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 284 + memory_stalls_for_bank_busy: 58 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 16 + memory_stalls_for_bus: 208 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 2 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 75 17 45 41 54 102 33 16 20 22 32 34 53 50 40 31 40 21 21 21 28 38 89 22 31 23 32 72 95 141 15 53 + + --- Directory --- + - Event Counts - +GETX [488 ] 488 +GETS [1093 ] 1093 +Lockdown [20 ] 20 +Unlockdown [20 ] 20 +Own_Lock_or_Unlock [0 ] 0 +Own_Lock_or_Unlock_Tokens [0 ] 0 +Data_Owner [9 ] 9 +Data_All_Tokens [220 ] 220 +Ack_Owner [29 ] 29 +Ack_Owner_All_Tokens [904 ] 904 +Tokens [0 ] 0 +Ack_All_Tokens [34 ] 34 +Request_Timeout [0 ] 0 +Memory_Data [1178 ] 1178 +Memory_Ack [229 ] 229 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_WRITE_All_Tokens [0 ] 0 + + - Transitions - +O GETX [168 ] 168 +O GETS [1010 ] 1010 +O Lockdown [0 ] 0 +O Unlockdown [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 +O Own_Lock_or_Unlock_Tokens [0 ] 0 +O Data_Owner [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Tokens [0 ] 0 +O Ack_All_Tokens [34 ] 34 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O DMA_WRITE_All_Tokens [0 ] 0 + +NO GETX [17 ] 17 +NO GETS [0 ] 0 +NO Lockdown [6 ] 6 +NO Unlockdown [0 ] 0 +NO Own_Lock_or_Unlock [0 ] 0 +NO Own_Lock_or_Unlock_Tokens [0 ] 0 +NO Data_Owner [9 ] 9 +NO Data_All_Tokens [220 ] 220 +NO Ack_Owner [29 ] 29 +NO Ack_Owner_All_Tokens [904 ] 904 +NO Tokens [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 + +L GETX [0 ] 0 +L GETS [0 ] 0 +L Lockdown [0 ] 0 +L Unlockdown [20 ] 20 +L Own_Lock_or_Unlock [0 ] 0 +L Own_Lock_or_Unlock_Tokens [0 ] 0 +L Data_Owner [0 ] 0 +L Data_All_Tokens [0 ] 0 +L Ack_Owner [0 ] 0 +L Ack_Owner_All_Tokens [0 ] 0 +L Tokens [0 ] 0 +L DMA_READ [0 ] 0 +L DMA_WRITE [0 ] 0 +L DMA_WRITE_All_Tokens [0 ] 0 + +O_W GETX [303 ] 303 +O_W GETS [83 ] 83 +O_W Lockdown [0 ] 0 +O_W Unlockdown [0 ] 0 +O_W Own_Lock_or_Unlock [0 ] 0 +O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_W Data_Owner [0 ] 0 +O_W Data_All_Tokens [0 ] 0 +O_W Ack_Owner [0 ] 0 +O_W Tokens [0 ] 0 +O_W Ack_All_Tokens [0 ] 0 +O_W Memory_Data [0 ] 0 +O_W Memory_Ack [229 ] 229 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_O_W GETX [0 ] 0 +L_O_W GETS [0 ] 0 +L_O_W Lockdown [0 ] 0 +L_O_W Unlockdown [0 ] 0 +L_O_W Own_Lock_or_Unlock [0 ] 0 +L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_O_W Data_Owner [0 ] 0 +L_O_W Data_All_Tokens [0 ] 0 +L_O_W Ack_Owner [0 ] 0 +L_O_W Tokens [0 ] 0 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [0 ] 0 +L_O_W Memory_Ack [0 ] 0 +L_O_W DMA_READ [0 ] 0 +L_O_W DMA_WRITE [0 ] 0 +L_O_W DMA_WRITE_All_Tokens [0 ] 0 + +L_NO_W GETX [0 ] 0 +L_NO_W GETS [0 ] 0 +L_NO_W Lockdown [0 ] 0 +L_NO_W Unlockdown [0 ] 0 +L_NO_W Own_Lock_or_Unlock [0 ] 0 +L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_NO_W Data_Owner [0 ] 0 +L_NO_W Data_All_Tokens [0 ] 0 +L_NO_W Ack_Owner [0 ] 0 +L_NO_W Tokens [0 ] 0 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [14 ] 14 +L_NO_W DMA_READ [0 ] 0 +L_NO_W DMA_WRITE [0 ] 0 +L_NO_W DMA_WRITE_All_Tokens [0 ] 0 + +DR_L_W GETX [0 ] 0 +DR_L_W GETS [0 ] 0 +DR_L_W Lockdown [0 ] 0 +DR_L_W Unlockdown [0 ] 0 +DR_L_W Own_Lock_or_Unlock [0 ] 0 +DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L_W Data_Owner [0 ] 0 +DR_L_W Data_All_Tokens [0 ] 0 +DR_L_W Ack_Owner [0 ] 0 +DR_L_W Tokens [0 ] 0 +DR_L_W Ack_All_Tokens [0 ] 0 +DR_L_W Request_Timeout [0 ] 0 +DR_L_W Memory_Data [0 ] 0 +DR_L_W DMA_READ [0 ] 0 +DR_L_W DMA_WRITE [0 ] 0 +DR_L_W DMA_WRITE_All_Tokens [0 ] 0 + +DW_L_W GETX [0 ] 0 +DW_L_W GETS [0 ] 0 +DW_L_W Lockdown [0 ] 0 +DW_L_W Unlockdown [0 ] 0 +DW_L_W Own_Lock_or_Unlock [0 ] 0 +DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L_W Data_Owner [0 ] 0 +DW_L_W Data_All_Tokens [0 ] 0 +DW_L_W Ack_Owner [0 ] 0 +DW_L_W Tokens [0 ] 0 +DW_L_W Ack_All_Tokens [0 ] 0 +DW_L_W Request_Timeout [0 ] 0 +DW_L_W Memory_Ack [0 ] 0 +DW_L_W DMA_READ [0 ] 0 +DW_L_W DMA_WRITE [0 ] 0 +DW_L_W DMA_WRITE_All_Tokens [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W Lockdown [14 ] 14 +NO_W Unlockdown [0 ] 0 +NO_W Own_Lock_or_Unlock [0 ] 0 +NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_W Data_Owner [0 ] 0 +NO_W Data_All_Tokens [0 ] 0 +NO_W Ack_Owner [0 ] 0 +NO_W Tokens [0 ] 0 +NO_W Ack_All_Tokens [0 ] 0 +NO_W Memory_Data [1164 ] 1164 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW_W GETX [0 ] 0 +O_DW_W GETS [0 ] 0 +O_DW_W Lockdown [0 ] 0 +O_DW_W Unlockdown [0 ] 0 +O_DW_W Own_Lock_or_Unlock [0 ] 0 +O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW_W Data_Owner [0 ] 0 +O_DW_W Data_All_Tokens [0 ] 0 +O_DW_W Ack_Owner [0 ] 0 +O_DW_W Tokens [0 ] 0 +O_DW_W Ack_All_Tokens [0 ] 0 +O_DW_W Request_Timeout [0 ] 0 +O_DW_W Memory_Ack [0 ] 0 +O_DW_W DMA_READ [0 ] 0 +O_DW_W DMA_WRITE [0 ] 0 +O_DW_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DR_W GETX [0 ] 0 +O_DR_W GETS [0 ] 0 +O_DR_W Lockdown [0 ] 0 +O_DR_W Unlockdown [0 ] 0 +O_DR_W Own_Lock_or_Unlock [0 ] 0 +O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DR_W Data_Owner [0 ] 0 +O_DR_W Data_All_Tokens [0 ] 0 +O_DR_W Ack_Owner [0 ] 0 +O_DR_W Tokens [0 ] 0 +O_DR_W Ack_All_Tokens [0 ] 0 +O_DR_W Request_Timeout [0 ] 0 +O_DR_W Memory_Data [0 ] 0 +O_DR_W DMA_READ [0 ] 0 +O_DR_W DMA_WRITE [0 ] 0 +O_DR_W DMA_WRITE_All_Tokens [0 ] 0 + +O_DW GETX [0 ] 0 +O_DW GETS [0 ] 0 +O_DW Lockdown [0 ] 0 +O_DW Unlockdown [0 ] 0 +O_DW Own_Lock_or_Unlock [0 ] 0 +O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW Data_Owner [0 ] 0 +O_DW Data_All_Tokens [0 ] 0 +O_DW Ack_Owner [0 ] 0 +O_DW Ack_Owner_All_Tokens [0 ] 0 +O_DW Tokens [0 ] 0 +O_DW Ack_All_Tokens [0 ] 0 +O_DW Request_Timeout [0 ] 0 +O_DW DMA_READ [0 ] 0 +O_DW DMA_WRITE [0 ] 0 +O_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DW GETX [0 ] 0 +NO_DW GETS [0 ] 0 +NO_DW Lockdown [0 ] 0 +NO_DW Unlockdown [0 ] 0 +NO_DW Own_Lock_or_Unlock [0 ] 0 +NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DW Data_Owner [0 ] 0 +NO_DW Data_All_Tokens [0 ] 0 +NO_DW Tokens [0 ] 0 +NO_DW Request_Timeout [0 ] 0 +NO_DW DMA_READ [0 ] 0 +NO_DW DMA_WRITE [0 ] 0 +NO_DW DMA_WRITE_All_Tokens [0 ] 0 + +NO_DR GETX [0 ] 0 +NO_DR GETS [0 ] 0 +NO_DR Lockdown [0 ] 0 +NO_DR Unlockdown [0 ] 0 +NO_DR Own_Lock_or_Unlock [0 ] 0 +NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DR Data_Owner [0 ] 0 +NO_DR Data_All_Tokens [0 ] 0 +NO_DR Tokens [0 ] 0 +NO_DR Request_Timeout [0 ] 0 +NO_DR DMA_READ [0 ] 0 +NO_DR DMA_WRITE [0 ] 0 +NO_DR DMA_WRITE_All_Tokens [0 ] 0 + +DW_L GETX [0 ] 0 +DW_L GETS [0 ] 0 +DW_L Lockdown [0 ] 0 +DW_L Unlockdown [0 ] 0 +DW_L Own_Lock_or_Unlock [0 ] 0 +DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L Data_Owner [0 ] 0 +DW_L Data_All_Tokens [0 ] 0 +DW_L Ack_Owner [0 ] 0 +DW_L Ack_Owner_All_Tokens [0 ] 0 +DW_L Tokens [0 ] 0 +DW_L Request_Timeout [0 ] 0 +DW_L DMA_READ [0 ] 0 +DW_L DMA_WRITE [0 ] 0 +DW_L DMA_WRITE_All_Tokens [0 ] 0 + +DR_L GETX [0 ] 0 +DR_L GETS [0 ] 0 +DR_L Lockdown [0 ] 0 +DR_L Unlockdown [0 ] 0 +DR_L Own_Lock_or_Unlock [0 ] 0 +DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L Data_Owner [0 ] 0 +DR_L Data_All_Tokens [0 ] 0 +DR_L Ack_Owner [0 ] 0 +DR_L Ack_Owner_All_Tokens [0 ] 0 +DR_L Tokens [0 ] 0 +DR_L Request_Timeout [0 ] 0 +DR_L DMA_READ [0 ] 0 +DR_L DMA_WRITE [0 ] 0 +DR_L DMA_WRITE_All_Tokens [0 ] 0 + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout new file mode 100755 index 000000000..6ef144b06 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 03:50:16 +gem5 started Jan 23 2012 04:22:25 +gem5 executing on zizzer +command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 231701 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt new file mode 100644 index 000000000..4911f0b0e --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -0,0 +1,77 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000232 # Number of seconds simulated +sim_ticks 231701 # Number of ticks simulated +final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 23819 # Simulator instruction rate (inst/s) +host_tick_rate 861729 # Simulator tick rate (ticks/s) +host_mem_usage 217800 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host +sim_insts 6404 # Number of instructions simulated +system.physmem.bytes_read 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written 6696 # Number of bytes written to this memory +system.physmem.num_reads 7599 # Number of read requests responded to by this memory +system.physmem.num_writes 865 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 148726160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 110728914 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 28899314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 177625474 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6415 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6432 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 231701 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 231701 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini new file mode 100644 index 000000000..aa987ffa6 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -0,0 +1,302 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +mem_mode=timing +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer probeFilter +buffer_size=0 +cntrl_id=1 +directory=system.dir_cntrl0.directory +full_bit_dir_enabled=false +memBuffer=system.dir_cntrl0.memBuffer +memory_controller_latency=2 +number_of_TBEs=256 +probeFilter=system.dir_cntrl0.probeFilter +probe_filter_enabled=false +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.dir_cntrl0.probeFilter] +type=RubyCache +assoc=4 +is_icache=false +latency=1 +replacement_policy=PSEUDO_LRU +size=1024 +start_index_bit=6 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory +L2cacheMemory=system.l1_cntrl0.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +cntrl_id=0 +issue_latency=2 +l2_cache_hit_latency=10 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L1DcacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L1IcacheMemory] +type=RubyCache +assoc=2 +is_icache=true +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=false +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=2 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers2 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=3 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers2 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats new file mode 100644 index 000000000..15beb0d93 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -0,0 +1,973 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, ordered +virtual_net_1: active, ordered +virtual_net_2: active, unordered +virtual_net_3: active, unordered +virtual_net_4: active, unordered +virtual_net_5: active, unordered +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/23/2012 04:21:44 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 + +Virtual_time_in_seconds: 0.3 +Virtual_time_in_minutes: 0.005 +Virtual_time_in_hours: 8.33333e-05 +Virtual_time_in_days: 3.47222e-06 + +Ruby_current_time: 208400 +Ruby_start_time: 0 +Ruby_cycles: 208400 + +mbytes_resident: 43.3594 +mbytes_total: 212.09 +resident_ratio: 0.204439 + +ruby_cycles_executed: [ 208401 ] + +Busy Controller Counts: +L1Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ] +miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ] +miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +imcomplete_dir_Times: 1158 +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ] +miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ] +miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 11268 +page_faults: 126 +swaps: 0 +block_inputs: 22864 +block_outputs: 104 + +Network Stats +------------- + +total_msg_count_Request_Control: 3477 27816 +total_msg_count_Response_Data: 3477 250344 +total_msg_count_Writeback_Data: 660 47520 +total_msg_count_Writeback_Control: 9627 77016 +total_msg_count_Unblock_Control: 3477 27816 +total_msgs: 20718 total_bytes: 430512 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 2.15187 + links_utilized_percent_switch_0_link_0: 2.77687 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 1.52687 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 2.15187 + links_utilized_percent_switch_1_link_0: 1.52687 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 2.77687 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 2.15187 + links_utilized_percent_switch_2_link_0: 2.77687 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 1.52687 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 646 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% + + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 646 100% + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 716 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 716 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 73.324% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 26.676% + + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 716 100% + +Cache Stats: system.l1_cntrl0.L2cacheMemory + system.l1_cntrl0.L2cacheMemory_total_misses: 1362 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1362 + system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L2cacheMemory_request_type_LD: 38.5463% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 14.0235% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 47.4302% + + system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 1362 100% + + --- L1Cache --- + - Event Counts - +Load [1193 ] 1193 +Ifetch [6425 ] 6425 +Store [892 ] 892 +L2_Replacement [1143 ] 1143 +L1_to_L2 [1354 ] 1354 +Trigger_L2_to_L1D [138 ] 138 +Trigger_L2_to_L1I [65 ] 65 +Complete_L2_to_L1 [203 ] 203 +Other_GETX [0 ] 0 +Other_GETS [0 ] 0 +Merged_GETS [0 ] 0 +Other_GETS_No_Mig [0 ] 0 +NC_DMA_GETS [0 ] 0 +Invalidate [0 ] 0 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Data [0 ] 0 +Shared_Data [0 ] 0 +Exclusive_Data [1159 ] 1159 +Writeback_Ack [1143 ] 1143 +Writeback_Nack [0 ] 0 +All_acks [0 ] 0 +All_acks_no_sharers [1159 ] 1159 +Flush_line [0 ] 0 +Block_Ack [0 ] 0 + + - Transitions - +I Load [420 ] 420 +I Ifetch [581 ] 581 +I Store [158 ] 158 +I L2_Replacement [0 ] 0 +I L1_to_L2 [0 ] 0 +I Trigger_L2_to_L1D [0 ] 0 +I Trigger_L2_to_L1I [0 ] 0 +I Other_GETX [0 ] 0 +I Other_GETS [0 ] 0 +I Other_GETS_No_Mig [0 ] 0 +I NC_DMA_GETS [0 ] 0 +I Invalidate [0 ] 0 +I Flush_line [0 ] 0 + +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L2_Replacement [0 ] 0 +S L1_to_L2 [0 ] 0 +S Trigger_L2_to_L1D [0 ] 0 +S Trigger_L2_to_L1I [0 ] 0 +S Other_GETX [0 ] 0 +S Other_GETS [0 ] 0 +S Other_GETS_No_Mig [0 ] 0 +S NC_DMA_GETS [0 ] 0 +S Invalidate [0 ] 0 +S Flush_line [0 ] 0 + +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L2_Replacement [0 ] 0 +O L1_to_L2 [0 ] 0 +O Trigger_L2_to_L1D [0 ] 0 +O Trigger_L2_to_L1I [0 ] 0 +O Other_GETX [0 ] 0 +O Other_GETS [0 ] 0 +O Merged_GETS [0 ] 0 +O Other_GETS_No_Mig [0 ] 0 +O NC_DMA_GETS [0 ] 0 +O Invalidate [0 ] 0 +O Flush_line [0 ] 0 + +M Load [306 ] 306 +M Ifetch [5768 ] 5768 +M Store [60 ] 60 +M L2_Replacement [923 ] 923 +M L1_to_L2 [1061 ] 1061 +M Trigger_L2_to_L1D [68 ] 68 +M Trigger_L2_to_L1I [65 ] 65 +M Other_GETX [0 ] 0 +M Other_GETS [0 ] 0 +M Merged_GETS [0 ] 0 +M Other_GETS_No_Mig [0 ] 0 +M NC_DMA_GETS [0 ] 0 +M Invalidate [0 ] 0 +M Flush_line [0 ] 0 + +MM Load [354 ] 354 +MM Ifetch [0 ] 0 +MM Store [614 ] 614 +MM L2_Replacement [220 ] 220 +MM L1_to_L2 [293 ] 293 +MM Trigger_L2_to_L1D [70 ] 70 +MM Trigger_L2_to_L1I [0 ] 0 +MM Other_GETX [0 ] 0 +MM Other_GETS [0 ] 0 +MM Merged_GETS [0 ] 0 +MM Other_GETS_No_Mig [0 ] 0 +MM NC_DMA_GETS [0 ] 0 +MM Invalidate [0 ] 0 +MM Flush_line [0 ] 0 + +IR Load [0 ] 0 +IR Ifetch [0 ] 0 +IR Store [0 ] 0 +IR L1_to_L2 [0 ] 0 +IR Flush_line [0 ] 0 + +SR Load [0 ] 0 +SR Ifetch [0 ] 0 +SR Store [0 ] 0 +SR L1_to_L2 [0 ] 0 +SR Flush_line [0 ] 0 + +OR Load [0 ] 0 +OR Ifetch [0 ] 0 +OR Store [0 ] 0 +OR L1_to_L2 [0 ] 0 +OR Flush_line [0 ] 0 + +MR Load [62 ] 62 +MR Ifetch [65 ] 65 +MR Store [6 ] 6 +MR L1_to_L2 [0 ] 0 +MR Flush_line [0 ] 0 + +MMR Load [43 ] 43 +MMR Ifetch [0 ] 0 +MMR Store [27 ] 27 +MMR L1_to_L2 [0 ] 0 +MMR Flush_line [0 ] 0 + +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L1_to_L2 [0 ] 0 +IM Other_GETX [0 ] 0 +IM Other_GETS [0 ] 0 +IM Other_GETS_No_Mig [0 ] 0 +IM NC_DMA_GETS [0 ] 0 +IM Invalidate [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [158 ] 158 +IM Flush_line [0 ] 0 + +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L2_Replacement [0 ] 0 +SM L1_to_L2 [0 ] 0 +SM Other_GETX [0 ] 0 +SM Other_GETS [0 ] 0 +SM Other_GETS_No_Mig [0 ] 0 +SM NC_DMA_GETS [0 ] 0 +SM Invalidate [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 +SM Flush_line [0 ] 0 + +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L2_Replacement [0 ] 0 +OM L1_to_L2 [0 ] 0 +OM Other_GETX [0 ] 0 +OM Other_GETS [0 ] 0 +OM Merged_GETS [0 ] 0 +OM Other_GETS_No_Mig [0 ] 0 +OM NC_DMA_GETS [0 ] 0 +OM Invalidate [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [0 ] 0 +OM All_acks_no_sharers [0 ] 0 +OM Flush_line [0 ] 0 + +ISM Load [0 ] 0 +ISM Ifetch [0 ] 0 +ISM Store [0 ] 0 +ISM L2_Replacement [0 ] 0 +ISM L1_to_L2 [0 ] 0 +ISM Ack [0 ] 0 +ISM All_acks_no_sharers [0 ] 0 +ISM Flush_line [0 ] 0 + +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [0 ] 0 +M_W L2_Replacement [0 ] 0 +M_W L1_to_L2 [0 ] 0 +M_W Ack [0 ] 0 +M_W All_acks_no_sharers [1001 ] 1001 +M_W Flush_line [0 ] 0 + +MM_W Load [0 ] 0 +MM_W Ifetch [0 ] 0 +MM_W Store [0 ] 0 +MM_W L2_Replacement [0 ] 0 +MM_W L1_to_L2 [0 ] 0 +MM_W Ack [0 ] 0 +MM_W All_acks_no_sharers [158 ] 158 +MM_W Flush_line [0 ] 0 + +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L1_to_L2 [0 ] 0 +IS Other_GETX [0 ] 0 +IS Other_GETS [0 ] 0 +IS Other_GETS_No_Mig [0 ] 0 +IS NC_DMA_GETS [0 ] 0 +IS Invalidate [0 ] 0 +IS Ack [0 ] 0 +IS Shared_Ack [0 ] 0 +IS Data [0 ] 0 +IS Shared_Data [0 ] 0 +IS Exclusive_Data [1001 ] 1001 +IS Flush_line [0 ] 0 + +SS Load [0 ] 0 +SS Ifetch [0 ] 0 +SS Store [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L1_to_L2 [0 ] 0 +SS Ack [0 ] 0 +SS Shared_Ack [0 ] 0 +SS All_acks [0 ] 0 +SS All_acks_no_sharers [0 ] 0 +SS Flush_line [0 ] 0 + +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L2_Replacement [0 ] 0 +OI L1_to_L2 [0 ] 0 +OI Other_GETX [0 ] 0 +OI Other_GETS [0 ] 0 +OI Merged_GETS [0 ] 0 +OI Other_GETS_No_Mig [0 ] 0 +OI NC_DMA_GETS [0 ] 0 +OI Invalidate [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Flush_line [0 ] 0 + +MI Load [8 ] 8 +MI Ifetch [11 ] 11 +MI Store [27 ] 27 +MI L2_Replacement [0 ] 0 +MI L1_to_L2 [0 ] 0 +MI Other_GETX [0 ] 0 +MI Other_GETS [0 ] 0 +MI Merged_GETS [0 ] 0 +MI Other_GETS_No_Mig [0 ] 0 +MI NC_DMA_GETS [0 ] 0 +MI Invalidate [0 ] 0 +MI Writeback_Ack [1143 ] 1143 +MI Flush_line [0 ] 0 + +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L2_Replacement [0 ] 0 +II L1_to_L2 [0 ] 0 +II Other_GETX [0 ] 0 +II Other_GETS [0 ] 0 +II Other_GETS_No_Mig [0 ] 0 +II NC_DMA_GETS [0 ] 0 +II Invalidate [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Nack [0 ] 0 +II Flush_line [0 ] 0 + +IT Load [0 ] 0 +IT Ifetch [0 ] 0 +IT Store [0 ] 0 +IT L2_Replacement [0 ] 0 +IT L1_to_L2 [0 ] 0 +IT Complete_L2_to_L1 [0 ] 0 + +ST Load [0 ] 0 +ST Ifetch [0 ] 0 +ST Store [0 ] 0 +ST L2_Replacement [0 ] 0 +ST L1_to_L2 [0 ] 0 +ST Complete_L2_to_L1 [0 ] 0 + +OT Load [0 ] 0 +OT Ifetch [0 ] 0 +OT Store [0 ] 0 +OT L2_Replacement [0 ] 0 +OT L1_to_L2 [0 ] 0 +OT Complete_L2_to_L1 [0 ] 0 + +MT Load [0 ] 0 +MT Ifetch [0 ] 0 +MT Store [0 ] 0 +MT L2_Replacement [0 ] 0 +MT L1_to_L2 [0 ] 0 +MT Complete_L2_to_L1 [133 ] 133 + +MMT Load [0 ] 0 +MMT Ifetch [0 ] 0 +MMT Store [0 ] 0 +MMT L2_Replacement [0 ] 0 +MMT L1_to_L2 [0 ] 0 +MMT Complete_L2_to_L1 [70 ] 70 + +MI_F Load [0 ] 0 +MI_F Ifetch [0 ] 0 +MI_F Store [0 ] 0 +MI_F L1_to_L2 [0 ] 0 +MI_F Writeback_Ack [0 ] 0 +MI_F Flush_line [0 ] 0 + +MM_F Load [0 ] 0 +MM_F Ifetch [0 ] 0 +MM_F Store [0 ] 0 +MM_F L1_to_L2 [0 ] 0 +MM_F Other_GETX [0 ] 0 +MM_F Other_GETS [0 ] 0 +MM_F Merged_GETS [0 ] 0 +MM_F Other_GETS_No_Mig [0 ] 0 +MM_F NC_DMA_GETS [0 ] 0 +MM_F Invalidate [0 ] 0 +MM_F Ack [0 ] 0 +MM_F All_acks [0 ] 0 +MM_F All_acks_no_sharers [0 ] 0 +MM_F Flush_line [0 ] 0 +MM_F Block_Ack [0 ] 0 + +IM_F Load [0 ] 0 +IM_F Ifetch [0 ] 0 +IM_F Store [0 ] 0 +IM_F L2_Replacement [0 ] 0 +IM_F L1_to_L2 [0 ] 0 +IM_F Other_GETX [0 ] 0 +IM_F Other_GETS [0 ] 0 +IM_F Other_GETS_No_Mig [0 ] 0 +IM_F NC_DMA_GETS [0 ] 0 +IM_F Invalidate [0 ] 0 +IM_F Ack [0 ] 0 +IM_F Data [0 ] 0 +IM_F Exclusive_Data [0 ] 0 +IM_F Flush_line [0 ] 0 + +ISM_F Load [0 ] 0 +ISM_F Ifetch [0 ] 0 +ISM_F Store [0 ] 0 +ISM_F L2_Replacement [0 ] 0 +ISM_F L1_to_L2 [0 ] 0 +ISM_F Ack [0 ] 0 +ISM_F All_acks_no_sharers [0 ] 0 +ISM_F Flush_line [0 ] 0 + +SM_F Load [0 ] 0 +SM_F Ifetch [0 ] 0 +SM_F Store [0 ] 0 +SM_F L2_Replacement [0 ] 0 +SM_F L1_to_L2 [0 ] 0 +SM_F Other_GETX [0 ] 0 +SM_F Other_GETS [0 ] 0 +SM_F Other_GETS_No_Mig [0 ] 0 +SM_F NC_DMA_GETS [0 ] 0 +SM_F Invalidate [0 ] 0 +SM_F Ack [0 ] 0 +SM_F Data [0 ] 0 +SM_F Exclusive_Data [0 ] 0 +SM_F Flush_line [0 ] 0 + +OM_F Load [0 ] 0 +OM_F Ifetch [0 ] 0 +OM_F Store [0 ] 0 +OM_F L2_Replacement [0 ] 0 +OM_F L1_to_L2 [0 ] 0 +OM_F Other_GETX [0 ] 0 +OM_F Other_GETS [0 ] 0 +OM_F Merged_GETS [0 ] 0 +OM_F Other_GETS_No_Mig [0 ] 0 +OM_F NC_DMA_GETS [0 ] 0 +OM_F Invalidate [0 ] 0 +OM_F Ack [0 ] 0 +OM_F All_acks [0 ] 0 +OM_F All_acks_no_sharers [0 ] 0 +OM_F Flush_line [0 ] 0 + +MM_WF Load [0 ] 0 +MM_WF Ifetch [0 ] 0 +MM_WF Store [0 ] 0 +MM_WF L2_Replacement [0 ] 0 +MM_WF L1_to_L2 [0 ] 0 +MM_WF Ack [0 ] 0 +MM_WF All_acks_no_sharers [0 ] 0 +MM_WF Flush_line [0 ] 0 + +Cache Stats: system.dir_cntrl0.probeFilter + system.dir_cntrl0.probeFilter_total_misses: 0 + system.dir_cntrl0.probeFilter_total_demand_misses: 0 + system.dir_cntrl0.probeFilter_total_prefetches: 0 + system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 + system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 + + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1379 + memory_reads: 1159 + memory_writes: 220 + memory_refreshes: 435 + memory_total_request_delays: 495 + memory_delays_per_request: 0.358956 + memory_delays_in_input_queue: 3 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 492 + memory_stalls_for_bank_busy: 124 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 23 + memory_stalls_for_bus: 78 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 267 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52 + + --- Directory --- + - Event Counts - +GETX [189 ] 189 +GETS [1027 ] 1027 +PUT [1143 ] 1143 +Unblock [0 ] 0 +UnblockS [0 ] 0 +UnblockM [1159 ] 1159 +Writeback_Clean [0 ] 0 +Writeback_Dirty [0 ] 0 +Writeback_Exclusive_Clean [923 ] 923 +Writeback_Exclusive_Dirty [220 ] 220 +Pf_Replacement [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [1159 ] 1159 +Memory_Ack [220 ] 220 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Shared_Data [0 ] 0 +Data [0 ] 0 +Exclusive_Data [0 ] 0 +All_acks_and_shared_data [0 ] 0 +All_acks_and_owner_data [0 ] 0 +All_acks_and_data_no_sharers [0 ] 0 +All_Unblocks [0 ] 0 +GETF [0 ] 0 +PUTF [0 ] 0 + + - Transitions - +NX GETX [0 ] 0 +NX GETS [0 ] 0 +NX PUT [0 ] 0 +NX Pf_Replacement [0 ] 0 +NX DMA_READ [0 ] 0 +NX DMA_WRITE [0 ] 0 +NX GETF [0 ] 0 + +NO GETX [0 ] 0 +NO GETS [0 ] 0 +NO PUT [1143 ] 1143 +NO Pf_Replacement [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 +NO GETF [0 ] 0 + +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUT [0 ] 0 +S Pf_Replacement [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 +S GETF [0 ] 0 + +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUT [0 ] 0 +O Pf_Replacement [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O GETF [0 ] 0 + +E GETX [158 ] 158 +E GETS [1001 ] 1001 +E PUT [0 ] 0 +E DMA_READ [0 ] 0 +E DMA_WRITE [0 ] 0 +E GETF [0 ] 0 + +O_R GETX [0 ] 0 +O_R GETS [0 ] 0 +O_R PUT [0 ] 0 +O_R Pf_Replacement [0 ] 0 +O_R DMA_READ [0 ] 0 +O_R DMA_WRITE [0 ] 0 +O_R Ack [0 ] 0 +O_R All_acks_and_data_no_sharers [0 ] 0 +O_R GETF [0 ] 0 + +S_R GETX [0 ] 0 +S_R GETS [0 ] 0 +S_R PUT [0 ] 0 +S_R Pf_Replacement [0 ] 0 +S_R DMA_READ [0 ] 0 +S_R DMA_WRITE [0 ] 0 +S_R Ack [0 ] 0 +S_R Data [0 ] 0 +S_R All_acks_and_data_no_sharers [0 ] 0 +S_R GETF [0 ] 0 + +NO_R GETX [0 ] 0 +NO_R GETS [0 ] 0 +NO_R PUT [0 ] 0 +NO_R Pf_Replacement [0 ] 0 +NO_R DMA_READ [0 ] 0 +NO_R DMA_WRITE [0 ] 0 +NO_R Ack [0 ] 0 +NO_R Data [0 ] 0 +NO_R Exclusive_Data [0 ] 0 +NO_R All_acks_and_data_no_sharers [0 ] 0 +NO_R GETF [0 ] 0 + +NO_B GETX [0 ] 0 +NO_B GETS [0 ] 0 +NO_B PUT [0 ] 0 +NO_B UnblockS [0 ] 0 +NO_B UnblockM [1159 ] 1159 +NO_B Pf_Replacement [0 ] 0 +NO_B DMA_READ [0 ] 0 +NO_B DMA_WRITE [0 ] 0 +NO_B GETF [0 ] 0 + +NO_B_X GETX [0 ] 0 +NO_B_X GETS [0 ] 0 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [0 ] 0 +NO_B_X UnblockM [0 ] 0 +NO_B_X Pf_Replacement [0 ] 0 +NO_B_X DMA_READ [0 ] 0 +NO_B_X DMA_WRITE [0 ] 0 +NO_B_X GETF [0 ] 0 + +NO_B_S GETX [0 ] 0 +NO_B_S GETS [0 ] 0 +NO_B_S PUT [0 ] 0 +NO_B_S UnblockS [0 ] 0 +NO_B_S UnblockM [0 ] 0 +NO_B_S Pf_Replacement [0 ] 0 +NO_B_S DMA_READ [0 ] 0 +NO_B_S DMA_WRITE [0 ] 0 +NO_B_S GETF [0 ] 0 + +NO_B_S_W GETX [0 ] 0 +NO_B_S_W GETS [0 ] 0 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [0 ] 0 +NO_B_S_W Pf_Replacement [0 ] 0 +NO_B_S_W DMA_READ [0 ] 0 +NO_B_S_W DMA_WRITE [0 ] 0 +NO_B_S_W All_Unblocks [0 ] 0 +NO_B_S_W GETF [0 ] 0 + +O_B GETX [0 ] 0 +O_B GETS [0 ] 0 +O_B PUT [0 ] 0 +O_B UnblockS [0 ] 0 +O_B UnblockM [0 ] 0 +O_B Pf_Replacement [0 ] 0 +O_B DMA_READ [0 ] 0 +O_B DMA_WRITE [0 ] 0 +O_B GETF [0 ] 0 + +NO_B_W GETX [0 ] 0 +NO_B_W GETS [0 ] 0 +NO_B_W PUT [0 ] 0 +NO_B_W UnblockS [0 ] 0 +NO_B_W UnblockM [0 ] 0 +NO_B_W Pf_Replacement [0 ] 0 +NO_B_W DMA_READ [0 ] 0 +NO_B_W DMA_WRITE [0 ] 0 +NO_B_W Memory_Data [1159 ] 1159 +NO_B_W GETF [0 ] 0 + +O_B_W GETX [0 ] 0 +O_B_W GETS [0 ] 0 +O_B_W PUT [0 ] 0 +O_B_W UnblockS [0 ] 0 +O_B_W Pf_Replacement [0 ] 0 +O_B_W DMA_READ [0 ] 0 +O_B_W DMA_WRITE [0 ] 0 +O_B_W Memory_Data [0 ] 0 +O_B_W GETF [0 ] 0 + +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W PUT [0 ] 0 +NO_W Pf_Replacement [0 ] 0 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W Memory_Data [0 ] 0 +NO_W GETF [0 ] 0 + +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W PUT [0 ] 0 +O_W Pf_Replacement [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W Memory_Data [0 ] 0 +O_W GETF [0 ] 0 + +NO_DW_B_W GETX [0 ] 0 +NO_DW_B_W GETS [0 ] 0 +NO_DW_B_W PUT [0 ] 0 +NO_DW_B_W Pf_Replacement [0 ] 0 +NO_DW_B_W DMA_READ [0 ] 0 +NO_DW_B_W DMA_WRITE [0 ] 0 +NO_DW_B_W Ack [0 ] 0 +NO_DW_B_W Data [0 ] 0 +NO_DW_B_W Exclusive_Data [0 ] 0 +NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 +NO_DW_B_W GETF [0 ] 0 + +NO_DR_B_W GETX [0 ] 0 +NO_DR_B_W GETS [0 ] 0 +NO_DR_B_W PUT [0 ] 0 +NO_DR_B_W Pf_Replacement [0 ] 0 +NO_DR_B_W DMA_READ [0 ] 0 +NO_DR_B_W DMA_WRITE [0 ] 0 +NO_DR_B_W Memory_Data [0 ] 0 +NO_DR_B_W Ack [0 ] 0 +NO_DR_B_W Shared_Ack [0 ] 0 +NO_DR_B_W Shared_Data [0 ] 0 +NO_DR_B_W Data [0 ] 0 +NO_DR_B_W Exclusive_Data [0 ] 0 +NO_DR_B_W GETF [0 ] 0 + +NO_DR_B_D GETX [0 ] 0 +NO_DR_B_D GETS [0 ] 0 +NO_DR_B_D PUT [0 ] 0 +NO_DR_B_D Pf_Replacement [0 ] 0 +NO_DR_B_D DMA_READ [0 ] 0 +NO_DR_B_D DMA_WRITE [0 ] 0 +NO_DR_B_D Ack [0 ] 0 +NO_DR_B_D Shared_Ack [0 ] 0 +NO_DR_B_D Shared_Data [0 ] 0 +NO_DR_B_D Data [0 ] 0 +NO_DR_B_D Exclusive_Data [0 ] 0 +NO_DR_B_D All_acks_and_shared_data [0 ] 0 +NO_DR_B_D All_acks_and_owner_data [0 ] 0 +NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 +NO_DR_B_D GETF [0 ] 0 + +NO_DR_B GETX [0 ] 0 +NO_DR_B GETS [0 ] 0 +NO_DR_B PUT [0 ] 0 +NO_DR_B Pf_Replacement [0 ] 0 +NO_DR_B DMA_READ [0 ] 0 +NO_DR_B DMA_WRITE [0 ] 0 +NO_DR_B Ack [0 ] 0 +NO_DR_B Shared_Ack [0 ] 0 +NO_DR_B Shared_Data [0 ] 0 +NO_DR_B Data [0 ] 0 +NO_DR_B Exclusive_Data [0 ] 0 +NO_DR_B All_acks_and_shared_data [0 ] 0 +NO_DR_B All_acks_and_owner_data [0 ] 0 +NO_DR_B All_acks_and_data_no_sharers [0 ] 0 +NO_DR_B GETF [0 ] 0 + +NO_DW_W GETX [0 ] 0 +NO_DW_W GETS [0 ] 0 +NO_DW_W PUT [0 ] 0 +NO_DW_W Pf_Replacement [0 ] 0 +NO_DW_W DMA_READ [0 ] 0 +NO_DW_W DMA_WRITE [0 ] 0 +NO_DW_W Memory_Ack [0 ] 0 +NO_DW_W GETF [0 ] 0 + +O_DR_B_W GETX [0 ] 0 +O_DR_B_W GETS [0 ] 0 +O_DR_B_W PUT [0 ] 0 +O_DR_B_W Pf_Replacement [0 ] 0 +O_DR_B_W DMA_READ [0 ] 0 +O_DR_B_W DMA_WRITE [0 ] 0 +O_DR_B_W Memory_Data [0 ] 0 +O_DR_B_W Ack [0 ] 0 +O_DR_B_W Shared_Ack [0 ] 0 +O_DR_B_W GETF [0 ] 0 + +O_DR_B GETX [0 ] 0 +O_DR_B GETS [0 ] 0 +O_DR_B PUT [0 ] 0 +O_DR_B Pf_Replacement [0 ] 0 +O_DR_B DMA_READ [0 ] 0 +O_DR_B DMA_WRITE [0 ] 0 +O_DR_B Ack [0 ] 0 +O_DR_B Shared_Ack [0 ] 0 +O_DR_B All_acks_and_owner_data [0 ] 0 +O_DR_B All_acks_and_data_no_sharers [0 ] 0 +O_DR_B GETF [0 ] 0 + +WB GETX [27 ] 27 +WB GETS [19 ] 19 +WB PUT [0 ] 0 +WB Unblock [0 ] 0 +WB Writeback_Clean [0 ] 0 +WB Writeback_Dirty [0 ] 0 +WB Writeback_Exclusive_Clean [923 ] 923 +WB Writeback_Exclusive_Dirty [220 ] 220 +WB Pf_Replacement [0 ] 0 +WB DMA_READ [0 ] 0 +WB DMA_WRITE [0 ] 0 +WB GETF [0 ] 0 + +WB_O_W GETX [0 ] 0 +WB_O_W GETS [0 ] 0 +WB_O_W PUT [0 ] 0 +WB_O_W Pf_Replacement [0 ] 0 +WB_O_W DMA_READ [0 ] 0 +WB_O_W DMA_WRITE [0 ] 0 +WB_O_W Memory_Ack [0 ] 0 +WB_O_W GETF [0 ] 0 + +WB_E_W GETX [4 ] 4 +WB_E_W GETS [7 ] 7 +WB_E_W PUT [0 ] 0 +WB_E_W Pf_Replacement [0 ] 0 +WB_E_W DMA_READ [0 ] 0 +WB_E_W DMA_WRITE [0 ] 0 +WB_E_W Memory_Ack [220 ] 220 +WB_E_W GETF [0 ] 0 + +NO_F GETX [0 ] 0 +NO_F GETS [0 ] 0 +NO_F PUT [0 ] 0 +NO_F UnblockM [0 ] 0 +NO_F Pf_Replacement [0 ] 0 +NO_F GETF [0 ] 0 +NO_F PUTF [0 ] 0 + +NO_F_W GETX [0 ] 0 +NO_F_W GETS [0 ] 0 +NO_F_W PUT [0 ] 0 +NO_F_W Pf_Replacement [0 ] 0 +NO_F_W DMA_READ [0 ] 0 +NO_F_W DMA_WRITE [0 ] 0 +NO_F_W Memory_Data [0 ] 0 +NO_F_W GETF [0 ] 0 + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout new file mode 100755 index 000000000..fa89dfcd6 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 03:42:19 +gem5 started Jan 23 2012 04:21:43 +gem5 executing on zizzer +command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 208400 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt new file mode 100644 index 000000000..dfbcac63c --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -0,0 +1,77 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000208 # Number of seconds simulated +sim_ticks 208400 # Number of ticks simulated +final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 24253 # Simulator instruction rate (inst/s) +host_tick_rate 789193 # Simulator tick rate (ticks/s) +host_mem_usage 217184 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host +sim_insts 6404 # Number of instructions simulated +system.physmem.bytes_read 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written 6696 # Number of bytes written to this memory +system.physmem.num_reads 7599 # Number of read requests responded to by this memory +system.physmem.num_writes 865 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 165355086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 123109405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 32130518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 197485605 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6415 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6432 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 208400 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 208400 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini new file mode 100644 index 000000000..0772d2ee5 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -0,0 +1,268 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +mem_mode=timing +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=1 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl0.cacheMemory +cache_response_latency=12 +cntrl_id=0 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.cacheMemory +max_outstanding_requests=16 +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=false +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=2 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers2 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=3 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers2 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=1 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +physmem=system.physmem +ruby_system=system.ruby +using_network_tester=false +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[1] +port=system.system_port + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats new file mode 100644 index 000000000..c9b06e2ad --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats @@ -0,0 +1,311 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, ordered +virtual_net_1: active, ordered +virtual_net_2: active, ordered +virtual_net_3: active, ordered +virtual_net_4: active, ordered +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: Jan/23/2012 04:58:59 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 + +Virtual_time_in_seconds: 0.3 +Virtual_time_in_minutes: 0.005 +Virtual_time_in_hours: 8.33333e-05 +Virtual_time_in_days: 3.47222e-06 + +Ruby_current_time: 342698 +Ruby_start_time: 0 +Ruby_cycles: 342698 + +mbytes_resident: 44.5703 +mbytes_total: 213.352 +resident_ratio: 0.208905 + +ruby_cycles_executed: [ 342699 ] + +Busy Controller Counts: +L1Cache-0:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average: 3 | standard deviation: 0 | 0 0 0 6734 ] +miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 1729 +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average: 3 | standard deviation: 0 | 0 0 0 458 ] +miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average: 3 | standard deviation: 0 | 0 0 0 592 ] +miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average: 3 | standard deviation: 0 | 0 0 0 5684 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1730 average: 0 | standard deviation: 0 | 1730 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1726 average: 0 | standard deviation: 0 | 1726 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 0 +system_time: 0 +page_reclaims: 11770 +page_faults: 1 +swaps: 0 +block_inputs: 8 +block_outputs: 88 + +Network Stats +------------- + +total_msg_count_Control: 5190 41520 +total_msg_count_Data: 5178 372816 +total_msg_count_Response_Data: 5190 373680 +total_msg_count_Writeback_Control: 5178 41424 +total_msgs: 20736 total_bytes: 829440 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 2.52117 + links_utilized_percent_switch_0_link_0: 2.5235 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 2.51884 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 2.52117 + links_utilized_percent_switch_1_link_0: 2.51884 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 2.5235 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 2.52117 + links_utilized_percent_switch_2_link_0: 2.5235 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 2.51884 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.cacheMemory + system.l1_cntrl0.cacheMemory_total_misses: 1730 + system.l1_cntrl0.cacheMemory_total_demand_misses: 1730 + system.l1_cntrl0.cacheMemory_total_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.cacheMemory_request_type_LD: 42.0231% + system.l1_cntrl0.cacheMemory_request_type_ST: 15.7803% + system.l1_cntrl0.cacheMemory_request_type_IFETCH: 42.1965% + + system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1730 100% + + --- L1Cache --- + - Event Counts - +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +Data [1730 ] 1730 +Fwd_GETX [0 ] 0 +Inv [0 ] 0 +Replacement [1726 ] 1726 +Writeback_Ack [1726 ] 1726 +Writeback_Nack [0 ] 0 + + - Transitions - +I Load [727 ] 727 +I Ifetch [730 ] 730 +I Store [273 ] 273 +I Inv [0 ] 0 +I Replacement [0 ] 0 + +II Writeback_Nack [0 ] 0 + +M Load [458 ] 458 +M Ifetch [5684 ] 5684 +M Store [592 ] 592 +M Fwd_GETX [0 ] 0 +M Inv [0 ] 0 +M Replacement [1726 ] 1726 + +MI Fwd_GETX [0 ] 0 +MI Inv [0 ] 0 +MI Writeback_Ack [1726 ] 1726 +MI Writeback_Nack [0 ] 0 + +MII Fwd_GETX [0 ] 0 + +IS Data [1457 ] 1457 + +IM Data [273 ] 273 + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 3456 + memory_reads: 1730 + memory_writes: 1726 + memory_refreshes: 714 + memory_total_request_delays: 4411 + memory_delays_per_request: 1.27633 + memory_delays_in_input_queue: 1083 + memory_delays_behind_head_of_bank_queue: 8 + memory_delays_stalled_at_head_of_bank_queue: 3320 + memory_stalls_for_bank_busy: 1509 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 99 + memory_stalls_for_bus: 1677 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 35 + memory_stalls_for_read_read_turnaround: 0 + accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98 + + --- Directory --- + - Event Counts - +GETX [1730 ] 1730 +GETS [0 ] 0 +PUTX [1726 ] 1726 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [1730 ] 1730 +Memory_Ack [1726 ] 1726 + + - Transitions - +I GETX [1730 ] 1730 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [0 ] 0 +M PUTX [1726 ] 1726 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [0 ] 0 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [1730 ] 1730 + +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [1726 ] 1726 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack [0 ] 0 + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout new file mode 100755 index 000000000..9cf822901 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 04:58:59 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 342698 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..beb747c41 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -0,0 +1,77 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000343 # Number of seconds simulated +sim_ticks 342698 # Number of ticks simulated +final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 32385 # Simulator instruction rate (inst/s) +host_tick_rate 1732860 # Simulator tick rate (ticks/s) +host_mem_usage 218476 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +sim_insts 6404 # Number of instructions simulated +system.physmem.bytes_read 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written 6696 # Number of bytes written to this memory +system.physmem.num_reads 7599 # Number of read requests responded to by this memory +system.physmem.num_writes 865 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 100555008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 74864750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 19539069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 120094077 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6415 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6432 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 342698 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 342698 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini new file mode 100644 index 000000000..f51983ecf --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -0,0 +1,205 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=AlphaTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=AlphaTLB +size=48 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout new file mode 100755 index 000000000..d977e688b --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:48:33 +gem5 started Jan 23 2012 04:58:59 +gem5 executing on zizzer +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 33007000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt new file mode 100644 index 000000000..84a161e81 --- /dev/null +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -0,0 +1,260 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 33007000 # Number of ticks simulated +final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 110064 # Simulator instruction rate (inst/s) +host_tick_rate 566999999 # Simulator tick rate (ticks/s) +host_mem_usage 206896 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +sim_insts 6404 # Number of instructions simulated +system.physmem.bytes_read 28544 # Number of bytes read from this memory +system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 446 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 864786257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 539037174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 864786257 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1185 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1192 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2050 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6415 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6432 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 66014 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 66014 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use +system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.062443 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits +system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits +system.cpu.icache.overall_hits 6136 # number of overall hits +system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses +system.cpu.icache.demand_misses 279 # number of demand (read+write) misses +system.cpu.icache.overall_misses 279 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use +system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.025313 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits +system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1882 # number of overall hits +system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses +system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 168 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005626 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 446 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |