diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt | 384 |
1 files changed, 195 insertions, 189 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index ac371de2b..95775a988 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20329000 # Number of ticks simulated -final_tick 20329000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 20616000 # Number of ticks simulated +final_tick 20616000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113549 # Simulator instruction rate (inst/s) -host_op_rate 113428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 891182571 # Simulator tick rate (ticks/s) -host_mem_usage 248724 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 91304 # Simulator instruction rate (inst/s) +host_op_rate 91266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 727585147 # Simulator tick rate (ticks/s) +host_mem_usage 252076 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 19840 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 310 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 708347681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 267598013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 975945693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 708347681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 708347681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 708347681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 267598013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 975945693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 698486612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 263872720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 962359333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 698486612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 698486612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 698486612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 263872720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 962359333 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 310 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20241500 # Total gap between requests +system.physmem.totGap 20527500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -188,70 +188,70 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.421645 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.320856 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 424.585366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 277.937119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.553388 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 7.32% 56.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5 12.20% 51.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 4.88% 56.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 6 14.63% 70.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 1774250 # Total ticks spent queuing -system.physmem.totMemAccLat 7586750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1590750 # Total ticks spent queuing +system.physmem.totMemAccLat 7403250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5723.39 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5131.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24473.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 975.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23881.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 962.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 975.95 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 962.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.62 # Data bus utilization in percentage -system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.52 # Data bus utilization in percentage +system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 260 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65295.16 # Average gap between requests +system.physmem.avgGap 66217.74 # Average gap between requests system.physmem.pageHitRate 83.87 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 787800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10557540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 238500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12729495 # Total energy per rank (pJ) -system.physmem_0.averagePower 804.010422 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 825750 # Time in different power states +system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12758055 # Total energy per rank (pJ) +system.physmem_0.averagePower 805.814306 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 727750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14971750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1162200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10490850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13284945 # Total energy per rank (pJ) -system.physmem_1.averagePower 838.894625 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states +system.physmem_1.actBackEnergy 10417320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 361500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13250265 # Total energy per rank (pJ) +system.physmem_1.averagePower 836.902890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 560000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14872250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14766250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 794 # Number of BP lookups system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20329000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40658 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 20616000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 41232 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed system.cpu.discardedOps 573 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 15.728433 # CPI: cycles per instruction -system.cpu.ipc 0.063579 # IPC: instructions per cycle +system.cpu.cpi 15.950484 # CPI: cycles per instruction +system.cpu.ipc 0.062694 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction @@ -344,25 +344,25 @@ system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 2585 # Class of committed instruction -system.cpu.tickCycles 5421 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35237 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 5423 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35809 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.302993 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.342284 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.302993 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011793 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011793 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.342284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1673 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1673 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits @@ -379,14 +379,14 @@ system.cpu.dcache.demand_misses::cpu.data 102 # n system.cpu.dcache.demand_misses::total 102 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 102 # number of overall misses system.cpu.dcache.overall_misses::total 102 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4783500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4783500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3258000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3258000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8041500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8041500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8041500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8041500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4617500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4617500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3301000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3301000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7918500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7918500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7918500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7918500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 500 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 500 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -403,14 +403,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.128463 system.cpu.dcache.demand_miss_rate::total 0.128463 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.128463 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.128463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81076.271186 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 81076.271186 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75767.441860 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75767.441860 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 78838.235294 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78838.235294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 78838.235294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78838.235294 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78262.711864 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78262.711864 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76767.441860 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76767.441860 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77632.352941 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77632.352941 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,14 +433,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2017500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2017500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6671500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6671500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6671500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6671500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4487000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4487000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2044500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2044500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6531500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6531500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6531500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6531500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116000 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116000 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -449,31 +449,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107053 system.cpu.dcache.demand_mshr_miss_rate::total 0.107053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.107053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80241.379310 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80241.379310 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78488.235294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78488.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78488.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78488.235294 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77362.068966 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77362.068966 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 119.197826 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 119.307121 # Cycle average of tags in use system.cpu.icache.tags.total_refs 754 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.351111 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 119.197826 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.058202 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.058202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 119.307121 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.058255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.058255 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2183 # Number of tag accesses system.cpu.icache.tags.data_accesses 2183 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 754 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 754 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 754 # number of demand (read+write) hits @@ -486,12 +486,12 @@ system.cpu.icache.demand_misses::cpu.inst 225 # n system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.icache.overall_misses::total 225 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17116000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17116000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17116000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17116000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17116000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17116000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17383000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17383000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17383000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17383000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17383000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17383000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 979 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses @@ -504,12 +504,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229826 system.cpu.icache.demand_miss_rate::total 0.229826 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.229826 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.229826 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76071.111111 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76071.111111 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76071.111111 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76071.111111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76071.111111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76071.111111 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77257.777778 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77257.777778 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77257.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77257.777778 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,43 +522,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 225 system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16891000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16891000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16891000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16891000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16891000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16891000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17158000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17158000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17158000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229826 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.229826 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.229826 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75071.111111 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75071.111111 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75071.111111 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75071.111111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75071.111111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75071.111111 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76257.777778 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 147.090026 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 167.807293 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 283 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 310 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.314039 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.775987 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003641 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004489 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008636 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.421716 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.385576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003644 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001477 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009460 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses @@ -571,18 +571,18 @@ system.cpu.l2cache.demand_misses::total 310 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 310 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16553500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16553500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4566000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4566000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16553500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6543000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23096500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16553500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6543000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23096500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2004000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2004000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16820500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16820500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4399000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4399000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16820500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6403000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23223500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16820500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6403000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23223500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses) @@ -607,18 +607,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73571.111111 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73571.111111 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78724.137931 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78724.137931 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73571.111111 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76976.470588 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74504.838710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73571.111111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76976.470588 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74504.838710 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74222.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74222.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74757.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74757.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75844.827586 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75844.827586 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74914.516129 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74914.516129 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,18 +637,18 @@ system.cpu.l2cache.demand_mshr_misses::total 310 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14303500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14303500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3986000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3986000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14303500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5693000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19996500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14303500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5693000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19996500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1734000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1734000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14570500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14570500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3819000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3819000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14570500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5553000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20123500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14570500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5553000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20123500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -661,25 +661,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63571.111111 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63571.111111 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68724.137931 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68724.137931 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.111111 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66976.470588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64504.838710 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.111111 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66976.470588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64504.838710 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64222.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64222.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64757.777778 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64757.777778 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65844.827586 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65844.827586 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -707,10 +707,16 @@ system.cpu.toL2Bus.snoop_fanout::total 310 # Re system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 283 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution @@ -733,7 +739,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 310 # Request fanout histogram system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 8.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1648750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |