diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 976 |
1 files changed, 493 insertions, 483 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 493ed4968..ee80959b5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12774000 # Number of ticks simulated -final_tick 12774000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12591500 # Number of ticks simulated +final_tick 12591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38054 # Simulator instruction rate (inst/s) -host_op_rate 38045 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 203548685 # Simulator tick rate (ticks/s) -host_mem_usage 224448 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 74456 # Simulator instruction rate (inst/s) +host_op_rate 74426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 392441951 # Simulator tick rate (ticks/s) +host_mem_usage 293552 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 936903084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 425865038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1362768123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 936903084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 936903084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 936903084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 425865038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1362768123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 950482468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 432037486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1382519954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 950482468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 950482468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 950482468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 432037486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1382519954 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 12677500 # Total gap between requests +system.physmem.totGap 12495000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::5 0 # Wr system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,9 +187,9 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.222222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 237.741650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.174986 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation @@ -200,37 +200,37 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 1960500 # Total ticks spent queuing -system.physmem.totMemAccLat 7060500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1676750 # Total ticks spent queuing +system.physmem.totMemAccLat 6776750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7207.72 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6164.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25957.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1362.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24914.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1382.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1362.77 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1382.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.65 # Data bus utilization in percentage -system.physmem.busUtilRead 10.65 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.80 # Data bus utilization in percentage +system.physmem.busUtilRead 10.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46608.46 # Average gap between requests +system.physmem.avgGap 45937.50 # Average gap between requests system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 592800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) -system.physmem_0.averagePower 832.600901 # Core power per rank (mW) +system.physmem_0.totalEnergy 6707115 # Total energy per rank (pJ) +system.physmem_0.averagePower 833.570297 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -238,48 +238,48 @@ system.physmem_0.memoryStateTime::ACT 7777500 # Ti system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 6961470 # Total energy per rank (pJ) -system.physmem_1.averagePower 865.181917 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 428500 # Time in different power states +system.physmem_1.totalEnergy 6969270 # Total energy per rank (pJ) +system.physmem_1.averagePower 866.151313 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 708000 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1106 # Number of BP lookups -system.cpu.branchPred.condPredicted 562 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 228 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 735 # Number of BTB lookups -system.cpu.branchPred.BTBHits 214 # Number of BTB hits +system.cpu.branchPred.lookups 1086 # Number of BP lookups +system.cpu.branchPred.condPredicted 546 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 723 # Number of BTB lookups +system.cpu.branchPred.BTBHits 206 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.115646 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 201 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 28.492393 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 197 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 705 # DTB read hits -system.cpu.dtb.read_misses 25 # DTB read misses +system.cpu.dtb.read_hits 688 # DTB read hits +system.cpu.dtb.read_misses 18 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 730 # DTB read accesses -system.cpu.dtb.write_hits 367 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses +system.cpu.dtb.read_accesses 706 # DTB read accesses +system.cpu.dtb.write_hits 353 # DTB write hits +system.cpu.dtb.write_misses 17 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 386 # DTB write accesses -system.cpu.dtb.data_hits 1072 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses +system.cpu.dtb.write_accesses 370 # DTB write accesses +system.cpu.dtb.data_hits 1041 # DTB hits +system.cpu.dtb.data_misses 35 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1116 # DTB accesses -system.cpu.itb.fetch_hits 947 # ITB hits +system.cpu.dtb.data_accesses 1076 # DTB accesses +system.cpu.itb.fetch_hits 931 # ITB hits system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 973 # ITB accesses +system.cpu.itb.fetch_accesses 957 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,236 +293,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 25549 # number of cpu cycles simulated +system.cpu.numCycles 25184 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4412 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6683 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1106 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 415 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1538 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 4404 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6508 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1086 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 403 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1405 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1107 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1109 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 152 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.910863 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.331734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 931 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 153 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.904014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.325149 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6194 84.42% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 50 0.68% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 126 1.72% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 86 1.17% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 137 1.87% 89.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 59 0.80% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 69 0.94% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 62 0.85% 92.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 554 7.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6086 84.54% 84.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 49 0.68% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 124 1.72% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 82 1.14% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 134 1.86% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 58 0.81% 90.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 66 0.92% 91.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 57 0.79% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 543 7.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.043289 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.261576 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5200 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 911 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 995 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 54 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 177 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 159 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.043123 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.258418 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5197 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 794 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 972 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 178 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5779 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 271 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 177 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5279 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 611 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 960 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5531 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 5639 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 178 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5280 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 486 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 942 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5401 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3966 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6270 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.rename.RenamedOperands 3881 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6086 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2198 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2113 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4768 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 109 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4674 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3966 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2386 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1238 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3880 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2292 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1214 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7337 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.540548 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.288327 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.538964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.280196 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5813 79.23% 79.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 503 6.86% 86.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 359 4.89% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 255 3.48% 94.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 198 2.70% 97.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 113 1.54% 98.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 62 0.85% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 21 0.29% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5699 79.16% 79.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 500 6.95% 86.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 351 4.88% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 251 3.49% 94.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 194 2.69% 97.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 116 1.61% 98.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 57 0.79% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 21 0.29% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7337 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7199 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 18.97% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 37.93% 56.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 25 43.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2817 71.03% 71.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 757 19.09% 90.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 391 9.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2765 71.26% 71.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 738 19.02% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 376 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3966 # Type of FU issued -system.cpu.iq.rate 0.155231 # Inst issue rate -system.cpu.iq.fu_busy_cnt 58 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014624 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15337 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7157 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3670 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3880 # Type of FU issued +system.cpu.iq.rate 0.154066 # Inst issue rate +system.cpu.iq.fu_busy_cnt 51 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15012 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6969 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3584 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4017 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3924 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 480 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 177 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 538 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5114 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 178 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 422 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5018 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 21 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 167 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 188 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3845 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 731 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 121 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 168 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3751 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 707 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 129 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 340 # number of nop insts executed -system.cpu.iew.exec_refs 1117 # number of memory reference insts executed -system.cpu.iew.exec_branches 655 # Number of branches executed -system.cpu.iew.exec_stores 386 # Number of stores executed -system.cpu.iew.exec_rate 0.150495 # Inst execution rate -system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3676 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1745 # num instructions producing a value -system.cpu.iew.wb_consumers 2262 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1077 # number of memory reference insts executed +system.cpu.iew.exec_branches 639 # Number of branches executed +system.cpu.iew.exec_stores 370 # Number of stores executed +system.cpu.iew.exec_rate 0.148944 # Inst execution rate +system.cpu.iew.wb_sent 3648 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3590 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1708 # num instructions producing a value +system.cpu.iew.wb_consumers 2182 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.143880 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.771441 # average fanout of values written-back +system.cpu.iew.wb_rate 0.142551 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.782768 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2526 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2428 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 154 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6873 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.374800 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.238011 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 155 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.381743 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.245988 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6022 87.62% 87.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192 2.79% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 299 4.35% 94.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 111 1.62% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.05% 97.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 55 0.80% 98.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.48% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.29% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5894 87.34% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193 2.86% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 303 4.49% 94.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 109 1.62% 96.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.07% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 56 0.83% 98.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.49% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.30% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6748 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,101 +568,101 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 11659 # The number of ROB reads -system.cpu.rob.rob_writes 10686 # The number of ROB writes +system.cpu.commit.bw_lim_events 68 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 11437 # The number of ROB reads +system.cpu.rob.rob_writes 10476 # The number of ROB writes system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18212 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17985 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.703393 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.703393 # CPI: Total CPI of All Threads -system.cpu.ipc 0.093428 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.093428 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4655 # number of integer regfile reads -system.cpu.int_regfile_writes 2832 # number of integer regfile writes +system.cpu.cpi 10.550482 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.550482 # CPI: Total CPI of All Threads +system.cpu.ipc 0.094782 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.094782 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4532 # number of integer regfile reads +system.cpu.int_regfile_writes 2777 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.039302 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 45.864197 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 731 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.600000 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.039302 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011240 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011240 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.864197 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011197 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011197 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1969 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1969 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 525 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 525 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 218 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 218 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits -system.cpu.dcache.overall_hits::total 743 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses -system.cpu.dcache.overall_misses::total 199 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8172750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8172750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5678000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5678000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13850750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13850750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13850750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13850750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 648 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1937 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1937 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 518 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 518 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 731 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 731 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 731 # number of overall hits +system.cpu.dcache.overall_hits::total 731 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 195 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 195 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 195 # number of overall misses +system.cpu.dcache.overall_misses::total 195 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7589500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7589500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5666500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5666500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13256000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13256000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13256000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13256000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 632 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 632 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 942 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 942 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 942 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 942 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.189815 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.189815 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.258503 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.258503 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.211253 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.211253 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.211253 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.211253 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66445.121951 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66445.121951 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74710.526316 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74710.526316 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69601.758794 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69601.758794 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 926 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 926 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 926 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 926 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180380 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180380 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.210583 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.210583 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.210583 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.210583 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66574.561404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66574.561404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69956.790123 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69956.790123 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67979.487179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67979.487179 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 139 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 110 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 110 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 110 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -671,193 +671,198 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4793500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4793500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1841500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1841500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6635000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6635000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6635000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6635000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094136 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6660500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096519 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096519 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090234 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090234 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78581.967213 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78581.967213 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091793 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091793 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091793 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091793 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78844.262295 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78844.262295 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78358.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78358.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78358.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78358.823529 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.893913 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 694 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 91.507771 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 679 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.711230 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.631016 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.893913 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.507771 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044682 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044682 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2081 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2081 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 694 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 694 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 694 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 694 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 694 # number of overall hits -system.cpu.icache.overall_hits::total 694 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses -system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18914999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18914999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18914999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18914999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18914999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18914999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 947 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 947 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 947 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.267159 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.267159 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.267159 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.267159 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.267159 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.267159 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74762.841897 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74762.841897 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74762.841897 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74762.841897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74762.841897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74762.841897 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 2049 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2049 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 679 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 679 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 679 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 679 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 679 # number of overall hits +system.cpu.icache.overall_hits::total 679 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 252 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 252 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 252 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 252 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 252 # number of overall misses +system.cpu.icache.overall_misses::total 252 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18724999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18724999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18724999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18724999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18724999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18724999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 931 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 931 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 931 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 931 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.270677 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.270677 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.270677 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.270677 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.270677 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.270677 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74305.551587 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74305.551587 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74305.551587 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74305.551587 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74305.551587 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74305.551587 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14404999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14404999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14404999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14404999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14404999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14404999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.197466 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.197466 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.197466 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77032.080214 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77032.080214 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77032.080214 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77032.080214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77032.080214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77032.080214 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14173499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14173499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14173499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14173499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14173499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14173499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.200859 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.200859 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.200859 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.200859 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.200859 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.200859 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75794.112299 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75794.112299 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75794.112299 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75794.112299 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75794.112299 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75794.112299 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 121.236486 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 120.686426 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 92.076745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29.159741 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002810 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000890 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003700 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.663709 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29.022716 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002797 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000886 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003683 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 187 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 248 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 187 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 187 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 272 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14216750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4732500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18949250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1816000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1816000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14216750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6548500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20765250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14216750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6548500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20765250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1813500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1813500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13892000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13892000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4718000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4718000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13892000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20423500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13892000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6531500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20423500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 187 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 61 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 187 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 272 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 187 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76025.401070 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77581.967213 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76408.266129 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75666.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75666.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76025.401070 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77041.176471 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76342.830882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76025.401070 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77041.176471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76342.830882 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74288.770053 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74288.770053 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77344.262295 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77344.262295 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74288.770053 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76841.176471 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75086.397059 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74288.770053 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76841.176471 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75086.397059 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -866,55 +871,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 248 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 187 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 187 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11881250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3969500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15850750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11881250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5489500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17370750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11881250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5489500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17370750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12022000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12022000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12022000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5681500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17703500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12022000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5681500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17703500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63536.096257 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65073.770492 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63914.314516 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64288.770053 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64288.770053 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67344.262295 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67344.262295 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 187 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) @@ -935,14 +945,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 318750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 139500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 248 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 248 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) @@ -958,9 +968,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 341000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1440250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1441250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |