diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 842 |
1 files changed, 421 insertions, 421 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 729742f8d..572203942 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6934000 # Number of ticks simulated -final_tick 6934000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 7252000 # Number of ticks simulated +final_tick 7252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29510 # Simulator instruction rate (inst/s) -host_op_rate 29504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85688409 # Simulator tick rate (ticks/s) -host_mem_usage 217944 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 57662 # Simulator instruction rate (inst/s) +host_op_rate 57638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 175044086 # Simulator tick rate (ticks/s) +host_mem_usage 217908 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1735217768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 784539948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2519757716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1735217768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1735217768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1735217768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 784539948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2519757716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1659128516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 750137893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2409266409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1659128516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1659128516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1659128516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 750137893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2409266409 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 704 # DTB read hits -system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.read_hits 712 # DTB read hits +system.cpu.dtb.read_misses 13 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 740 # DTB read accesses -system.cpu.dtb.write_hits 367 # DTB write hits -system.cpu.dtb.write_misses 22 # DTB write misses +system.cpu.dtb.read_accesses 725 # DTB read accesses +system.cpu.dtb.write_hits 368 # DTB write hits +system.cpu.dtb.write_misses 15 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 389 # DTB write accesses -system.cpu.dtb.data_hits 1071 # DTB hits -system.cpu.dtb.data_misses 58 # DTB misses +system.cpu.dtb.write_accesses 383 # DTB write accesses +system.cpu.dtb.data_hits 1080 # DTB hits +system.cpu.dtb.data_misses 28 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1129 # DTB accesses -system.cpu.itb.fetch_hits 999 # ITB hits +system.cpu.dtb.data_accesses 1108 # DTB accesses +system.cpu.itb.fetch_hits 1014 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1029 # ITB accesses +system.cpu.itb.fetch_accesses 1044 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13869 # number of cpu cycles simulated +system.cpu.numCycles 14505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1119 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 563 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 252 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 783 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 216 # Number of BTB hits +system.cpu.BPredUnit.lookups 1131 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 573 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 253 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 782 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3820 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6858 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1119 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 426 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1175 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 850 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 242 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 211 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6900 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 429 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1183 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 857 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 264 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 783 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 170 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.037362 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.461313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 948 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1014 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 172 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.939926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.361375 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5436 82.23% 82.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 51 0.77% 83.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 129 1.95% 84.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 97 1.47% 86.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 136 2.06% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 62 0.94% 89.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 66 1.00% 90.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.97% 91.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 570 8.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6158 83.89% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 50 0.68% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 129 1.76% 86.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 101 1.38% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 139 1.89% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 62 0.84% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 66 0.90% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 61 0.83% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 575 7.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080684 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.494484 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4718 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 256 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1133 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 166 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6102 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 7341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077973 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.475698 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5395 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 291 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1141 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 501 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6151 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4814 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 67 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1046 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5849 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4252 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6619 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6607 # Number of integer rename lookups +system.cpu.rename.SquashCycles 501 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5491 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 66 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 174 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1058 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5908 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4280 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6676 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6664 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2484 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2512 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 137 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 945 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 145 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4975 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5051 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 4026 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2372 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1428 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2503 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6611 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608985 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.321430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.548427 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.241979 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4990 75.48% 75.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 583 8.82% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 382 5.78% 90.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 267 4.04% 94.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 192 2.90% 97.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 114 1.72% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 53 0.80% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18 0.27% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5680 77.37% 77.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 617 8.40% 85.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 387 5.27% 91.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 273 3.72% 94.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 198 2.70% 97.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 114 1.55% 99.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 56 0.76% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10 0.14% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 6 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7341 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 9.09% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 17 38.64% 47.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.88% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17 41.46% 46.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 53.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2853 70.86% 70.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 775 19.25% 90.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 397 9.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2876 71.44% 71.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 761 18.90% 90.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 388 9.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 4026 # Type of FU issued -system.cpu.iq.rate 0.290288 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010929 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14762 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7351 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3682 # Number of integer instruction queue wakeup accesses +system.cpu.iq.rate 0.277559 # Inst issue rate +system.cpu.iq.fu_busy_cnt 41 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010184 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15500 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3688 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4063 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4060 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 530 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 182 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5319 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 96 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 945 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 501 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5407 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 153 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 150 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 207 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3873 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 741 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3874 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 152 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1130 # number of memory reference insts executed -system.cpu.iew.exec_branches 650 # Number of branches executed -system.cpu.iew.exec_stores 389 # Number of stores executed -system.cpu.iew.exec_rate 0.279256 # Inst execution rate -system.cpu.iew.wb_sent 3778 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3688 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1732 # num instructions producing a value -system.cpu.iew.wb_consumers 2249 # num instructions consuming a value +system.cpu.iew.exec_nop 350 # number of nop insts executed +system.cpu.iew.exec_refs 1109 # number of memory reference insts executed +system.cpu.iew.exec_branches 649 # Number of branches executed +system.cpu.iew.exec_stores 383 # Number of stores executed +system.cpu.iew.exec_rate 0.267080 # Inst execution rate +system.cpu.iew.wb_sent 3756 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3694 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1740 # num instructions producing a value +system.cpu.iew.wb_consumers 2202 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.265917 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.770120 # average fanout of values written-back +system.cpu.iew.wb_rate 0.254671 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.790191 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2738 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2822 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 172 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6117 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.421121 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.275697 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.225423 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5226 85.43% 85.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 218 3.56% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 319 5.21% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 117 1.91% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 69 1.13% 97.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 56 0.92% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.52% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 19 0.31% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 61 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5956 87.08% 87.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 217 3.17% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 318 4.65% 94.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 115 1.68% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 67 0.98% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 47 0.69% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.47% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 21 0.31% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,69 +310,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11123 # The number of ROB reads -system.cpu.rob.rob_writes 11131 # The number of ROB writes -system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7258 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11924 # The number of ROB reads +system.cpu.rob.rob_writes 11305 # The number of ROB writes +system.cpu.timesIdled 172 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.810222 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.810222 # CPI: Total CPI of All Threads -system.cpu.ipc 0.172110 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.172110 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4695 # number of integer regfile reads -system.cpu.int_regfile_writes 2856 # number of integer regfile writes +system.cpu.cpi 6.076665 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.076665 # CPI: Total CPI of All Threads +system.cpu.ipc 0.164564 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.164564 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4677 # number of integer regfile reads +system.cpu.int_regfile_writes 2861 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 93.248355 # Cycle average of tags in use -system.cpu.icache.total_refs 752 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 94.201337 # Cycle average of tags in use +system.cpu.icache.total_refs 769 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.090426 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 93.248355 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045531 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045531 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 752 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 752 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 752 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 752 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 752 # number of overall hits -system.cpu.icache.overall_hits::total 752 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 247 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 247 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 247 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 247 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 247 # number of overall misses -system.cpu.icache.overall_misses::total 247 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8946000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8946000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8946000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8946000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8946000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8946000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 999 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 999 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 999 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 999 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.247247 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.247247 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.247247 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.247247 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.247247 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.247247 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36218.623482 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36218.623482 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36218.623482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36218.623482 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 94.201337 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045997 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045997 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 769 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 769 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 769 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 769 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 769 # number of overall hits +system.cpu.icache.overall_hits::total 769 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 245 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 245 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 245 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 245 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 245 # number of overall misses +system.cpu.icache.overall_misses::total 245 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 9112500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 9112500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 9112500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 9112500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 9112500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 9112500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1014 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1014 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1014 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1014 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241617 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.241617 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.241617 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.241617 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.241617 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.241617 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37193.877551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37193.877551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37193.877551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37193.877551 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,94 +381,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6660500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6660500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6660500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6660500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188188 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188188 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188188 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35428.191489 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35428.191489 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6932500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6932500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6932500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6932500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6932500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6932500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185404 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.185404 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.185404 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36875 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36875 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.780075 # Cycle average of tags in use -system.cpu.dcache.total_refs 785 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.851495 # Cycle average of tags in use +system.cpu.dcache.total_refs 774 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.235294 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.105882 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.780075 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011177 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011177 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 563 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 563 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 785 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 785 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 785 # number of overall hits -system.cpu.dcache.overall_hits::total 785 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 110 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 110 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses -system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3679000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3679000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2813500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2813500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 673 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 45.851495 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011194 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011194 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 561 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits +system.cpu.dcache.overall_hits::total 774 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses +system.cpu.dcache.overall_misses::total 199 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4328500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4328500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3561500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3561500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7890000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7890000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7890000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7890000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 679 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 967 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 967 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 967 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 967 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.163447 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.163447 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.188211 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.188211 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.188211 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.188211 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33445.454545 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33445.454545 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39076.388889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39076.388889 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35673.076923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35673.076923 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 973 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 973 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 973 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 973 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173785 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.173785 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.204522 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.204522 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.204522 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.204522 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36682.203390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36682.203390 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43969.135802 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43969.135802 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39648.241206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39648.241206 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,14 +477,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -493,42 +493,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2166000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2166000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 871000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 871000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3037000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3037000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3037000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3037000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090639 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 981000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3492500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3492500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3492500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3492500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089838 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089838 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087901 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087901 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35508.196721 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35508.196721 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36291.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36291.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087359 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087359 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41172.131148 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41172.131148 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40875 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 122.119430 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 123.109780 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.334885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.784545 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002848 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000878 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003727 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 94.284624 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.825156 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002877 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000880 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003757 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -540,17 +540,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6449000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2098500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8547500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 830000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 830000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6449000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2928500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9377500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6449000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2928500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9377500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6740500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2447000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9187500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 950000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 950000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6740500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3397000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10137500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6740500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3397000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10137500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -573,17 +573,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34303.191489 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34401.639344 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34327.309237 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34583.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34583.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34349.816850 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34349.816850 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35853.723404 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40114.754098 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36897.590361 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39583.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39583.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37133.699634 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37133.699634 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,17 +603,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5849000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1904500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7753500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 755000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 755000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5849000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2659500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8508500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5849000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2659500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8508500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6136500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2258000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8394500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 876000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 876000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6136500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3134000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9270500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6136500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3134000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9270500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -625,17 +625,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31111.702128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31221.311475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31138.554217 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31458.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31458.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.957447 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37016.393443 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33712.851406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |