diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/o3-timing')
4 files changed, 0 insertions, 1861 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index ff6825b17..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index 4e7b90c23..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 35f169b23..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:49 -gem5 executing on e108600-lin, pid 28097 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 13358500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index ed65513bb..000000000 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,1016 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13358500 # Number of ticks simulated -final_tick 13358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102485 # Simulator instruction rate (inst/s) -host_op_rate 102439 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 573050673 # Simulator tick rate (ticks/s) -host_mem_usage 252720 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 2387 # Number of instructions simulated -sim_ops 2387 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory -system.physmem.bytes_read::total 17408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory -system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 895908972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 407231351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1303140323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 895908972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 895908972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 895908972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 407231351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1303140323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 272 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 17408 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 17408 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 0 # Per bank write bursts -system.physmem.perBankRdBursts::1 1 # Per bank write bursts -system.physmem.perBankRdBursts::2 2 # Per bank write bursts -system.physmem.perBankRdBursts::3 24 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 24 # Per bank write bursts -system.physmem.perBankRdBursts::7 37 # Per bank write bursts -system.physmem.perBankRdBursts::8 60 # Per bank write bursts -system.physmem.perBankRdBursts::9 2 # Per bank write bursts -system.physmem.perBankRdBursts::10 15 # Per bank write bursts -system.physmem.perBankRdBursts::11 9 # Per bank write bursts -system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 50 # Per bank write bursts -system.physmem.perBankRdBursts::14 12 # Per bank write bursts -system.physmem.perBankRdBursts::15 1 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 13255000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 272 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 235.532687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.140835 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4 11.11% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 11.11% 55.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 16.67% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 5.56% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 2.78% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 2.78% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 3364250 # Total ticks spent queuing -system.physmem.totMemAccLat 8464250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12368.57 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31118.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1303.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1303.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.18 # Data bus utilization in percentage -system.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 224 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48731.62 # Average gap between requests -system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 99960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 37950 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1355460 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 21600 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 4583370 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 107040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 7576860 # Total energy per rank (pJ) -system.physmem_0.averagePower 567.183307 # Core power per rank (mW) -system.physmem_0.totalIdleTime 10278500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 28500 # Time in different power states -system.physmem_0.memoryStateTime::REF 260000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 279000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2735250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 10055750 # Time in different power states -system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 98670 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1185240 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1822290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 183840 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 4050420 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 8198340 # Total energy per rank (pJ) -system.physmem_1.averagePower 613.705624 # Core power per rank (mW) -system.physmem_1.totalIdleTime 8246250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 450500 # Time in different power states -system.physmem_1.memoryStateTime::REF 260000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3767500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 8879250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 994 # Number of BP lookups -system.cpu.branchPred.condPredicted 488 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 684 # Number of BTB lookups -system.cpu.branchPred.BTBHits 175 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.584795 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 99 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 97 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 705 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 715 # DTB read accesses -system.cpu.dtb.write_hits 349 # DTB write hits -system.cpu.dtb.write_misses 16 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 365 # DTB write accesses -system.cpu.dtb.data_hits 1054 # DTB hits -system.cpu.dtb.data_misses 26 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1080 # DTB accesses -system.cpu.itb.fetch_hits 872 # ITB hits -system.cpu.itb.fetch_misses 32 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 904 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 13358500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 26718 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4379 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6026 # Number of instructions fetch has processed -system.cpu.fetch.Branches 994 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 395 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1172 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 872 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 147 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.260497 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5993 85.39% 85.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 27 0.38% 85.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 97 1.38% 87.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 87 1.24% 88.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 140 1.99% 90.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 81 1.15% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 45 0.64% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 75 1.07% 93.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 473 6.74% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037203 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.225541 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5261 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 642 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 913 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 39 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5228 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 263 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5336 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 333 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 302 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 873 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5015 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3598 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5603 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1830 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 838 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 424 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4336 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3724 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1954 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 987 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.530636 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.266302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5580 79.51% 79.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 466 6.64% 86.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 341 4.86% 91.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 254 3.62% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 190 2.71% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 104 1.48% 98.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 55 0.78% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 20 0.28% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7018 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 30 49.18% 59.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 24 39.34% 98.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1 1.64% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2606 69.98% 69.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 745 20.01% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 366 9.83% 99.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 6 0.16% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3724 # Type of FU issued -system.cpu.iq.rate 0.139382 # Inst issue rate -system.cpu.iq.fu_busy_cnt 61 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016380 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14533 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6293 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3394 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3778 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 423 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 130 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 42 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 304 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 4648 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 838 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 424 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 132 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 165 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3600 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 717 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 124 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 306 # number of nop insts executed -system.cpu.iew.exec_refs 1082 # number of memory reference insts executed -system.cpu.iew.exec_branches 595 # Number of branches executed -system.cpu.iew.exec_stores 365 # Number of stores executed -system.cpu.iew.exec_rate 0.134741 # Inst execution rate -system.cpu.iew.wb_sent 3453 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3400 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1619 # num instructions producing a value -system.cpu.iew.wb_consumers 2076 # num instructions consuming a value -system.cpu.iew.wb_rate 0.127255 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.779865 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2070 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.389713 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.245121 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5740 86.84% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 197 2.98% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 319 4.83% 94.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 117 1.77% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 63 0.95% 97.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.80% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 36 0.54% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23 0.35% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 62 0.94% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6610 # Number of insts commited each cycle -system.cpu.commit.committedInsts 2576 # Number of instructions committed -system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 709 # Number of memory references committed -system.cpu.commit.loads 415 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 396 # Number of branches committed -system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. -system.cpu.commit.int_insts 2367 # Number of committed integer instructions. -system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 189 7.34% 7.34% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1677 65.10% 72.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 1 0.04% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 288 11.18% 99.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 6 0.23% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 62 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 10947 # The number of ROB reads -system.cpu.rob.rob_writes 9704 # The number of ROB writes -system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19700 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 2387 # Number of Instructions Simulated -system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 11.193129 # CPI: Cycles Per Instruction -system.cpu.cpi_total 11.193129 # CPI: Total CPI of All Threads -system.cpu.ipc 0.089341 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.089341 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4344 # number of integer regfile reads -system.cpu.int_regfile_writes 2618 # number of integer regfile writes -system.cpu.fp_regfile_reads 6 # number of floating regfile reads -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.378002 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.378002 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011079 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011079 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1935 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1935 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 530 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits -system.cpu.dcache.overall_hits::total 743 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses -system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7124500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7124500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6134000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6134000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13258500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13258500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13258500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13258500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 631 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 631 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 925 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 925 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 925 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 925 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.160063 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.160063 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.196757 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.196757 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.196757 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.196757 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70539.603960 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70539.603960 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75728.395062 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75728.395062 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72848.901099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72848.901099 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5157500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5157500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2004000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2004000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7161500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7161500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7161500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7161500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096672 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096672 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091892 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091892 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091892 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091892 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84549.180328 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84549.180328 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84252.941176 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84252.941176 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84252.941176 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84252.941176 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 89.996713 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 618 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.304813 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 89.996713 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.043944 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.043944 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1931 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1931 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 618 # number of overall hits -system.cpu.icache.overall_hits::total 618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 254 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 254 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 254 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 254 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 254 # number of overall misses -system.cpu.icache.overall_misses::total 254 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20808999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20808999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20808999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20808999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20808999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20808999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 872 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 872 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 872 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 872 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.291284 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.291284 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.291284 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.291284 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.291284 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.291284 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81925.192913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 81925.192913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 81925.192913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 81925.192913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 81925.192913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 81925.192913 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15635499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15635499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15635499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15635499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15635499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15635499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.214450 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.214450 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.214450 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83612.294118 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83612.294118 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83612.294118 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83612.294118 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83612.294118 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83612.294118 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 135.588512 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 272 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.143699 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.444813 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002751 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004138 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 272 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008301 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 187 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 187 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 272 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses -system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1966500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1966500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15354000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 15354000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5066000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5066000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15354000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7032500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22386500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15354000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7032500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22386500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 187 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 61 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 187 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 272 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 187 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81937.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81937.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82106.951872 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82106.951872 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83049.180328 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83049.180328 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82303.308824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82303.308824 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 187 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 187 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1726500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1726500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13484000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13484000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4456000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4456000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13484000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6182500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19666500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13484000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6182500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19666500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71937.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71937.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72106.951872 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72106.951872 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73049.180328 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73049.180328 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 187 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 248 # Transaction distribution -system.membus.trans_dist::ReadExReq 24 # Transaction distribution -system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 248 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 272 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 337500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1437500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 10.8 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |