diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level')
-rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini | 20 | ||||
-rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt | 12 |
2 files changed, 24 insertions, 8 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini index 8168c285c..96554f51d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000 [system] type=System -children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain +children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:268435455 memories=system.physmem @@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -108,7 +110,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -131,6 +133,16 @@ latency_var=0 null=true range=0:134217727 +[system.piobus] +type=NoncoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=false +width=8 +master=system.ruby.l1_cntrl0.sequencer.pio_slave_port +slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port + [system.ruby] type=RubySystem children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network @@ -282,6 +294,9 @@ system=system using_network_tester=false using_ruby_tester=false version=0 +mem_master_port=system.piobus.slave[1] +pio_master_port=system.piobus.slave[0] +pio_slave_port=system.piobus.master[0] slave=system.cpu.icache_port system.cpu.dcache_port [system.ruby.l2_cntrl0] @@ -436,7 +451,6 @@ ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.system_port diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 32cd33943..24dc22b08 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,15 +4,17 @@ sim_seconds 0.000053 # Nu sim_ticks 52548 # Number of ticks simulated final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18733 # Simulator instruction rate (inst/s) -host_op_rate 18730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 381878 # Simulator tick rate (ticks/s) -host_mem_usage 173280 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 15623 # Simulator instruction rate (inst/s) +host_op_rate 15622 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 318507 # Simulator tick rate (ticks/s) +host_mem_usage 173288 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.piobus.throughput 0 # Throughput (bytes/s) +system.piobus.data_through_bus 0 # Total data (bytes) system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message |