diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt | 48 |
1 files changed, 43 insertions, 5 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 98abd69d6..408d1d326 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,16 +4,30 @@ sim_seconds 0.000052 # Nu sim_ticks 52498 # Number of ticks simulated final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 9649 # Simulator instruction rate (inst/s) -host_op_rate 9649 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 196549 # Simulator tick rate (ticks/s) -host_mem_usage 151788 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 30872 # Simulator instruction rate (inst/s) +host_op_rate 30864 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 628609 # Simulator tick rate (ticks/s) +host_mem_usage 144188 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 1248 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 626 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 622 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 915 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 915 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.733173 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 352 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 497 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 26 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 40 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 55 4.41% 4.41% | 40 3.21% 7.61% | 0 0.00% 7.61% | 100 8.01% 15.62% | 42 3.37% 18.99% | 42 3.37% 22.36% | 88 7.05% 29.41% | 45 3.61% 33.01% | 14 1.12% 34.13% | 10 0.80% 34.94% | 14 1.12% 36.06% | 10 0.80% 36.86% | 46 3.69% 40.54% | 82 6.57% 47.12% | 38 3.04% 50.16% | 6 0.48% 50.64% | 22 1.76% 52.40% | 14 1.12% 53.53% | 14 1.12% 54.65% | 48 3.85% 58.49% | 20 1.60% 60.10% | 52 4.17% 64.26% | 26 2.08% 66.35% | 92 7.37% 73.72% | 34 2.72% 76.44% | 10 0.80% 77.24% | 12 0.96% 78.21% | 24 1.92% 80.13% | 28 2.24% 82.37% | 44 3.53% 85.90% | 38 3.04% 88.94% | 138 11.06% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1248 # Number of accesses per bank + system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -69,5 +83,29 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 52498 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l1_cntrl0.Load 415 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00% +system.ruby.l1_cntrl0.Store 294 0.00% 0.00% +system.ruby.l1_cntrl0.Data 626 0.00% 0.00% +system.ruby.l1_cntrl0.Replacement 622 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 622 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 245 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 297 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 84 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 170 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 2288 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 210 0.00% 0.00% +system.ruby.l1_cntrl0.M.Replacement 622 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 622 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data 542 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data 84 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 626 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 622 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 626 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 622 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 626 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 622 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 626 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 622 0.00% 0.00% ---------- End Simulation Statistics ---------- |