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Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini')
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini15
1 files changed, 6 insertions, 9 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index ea66af4ee..d8f1b0ca1 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -87,7 +87,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=false
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -98,7 +98,6 @@ size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -119,7 +118,7 @@ eventq_index=0
size=64
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -128,7 +127,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
-is_top_level=true
+is_read_only=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
@@ -139,7 +138,6 @@ size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
-two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -169,7 +167,7 @@ eventq_index=0
size=48
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -178,7 +176,7 @@ demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
-is_top_level=false
+is_read_only=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
@@ -189,7 +187,6 @@ size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
-two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]