diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64')
16 files changed, 804 insertions, 720 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini index 8e21534df..654daf7a1 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -120,11 +122,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -135,7 +144,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -560,7 +568,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -611,7 +618,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -646,6 +652,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -711,6 +718,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index eadf1b794..8e060c84e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20075000 # Number of ticks simulated -final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20320000 # Number of ticks simulated +final_tick 20320000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 31344 # Simulator instruction rate (inst/s) host_op_rate 31334 # Simulator op (including micro ops) rate (op/s) @@ -13,30 +13,30 @@ sim_insts 2585 # Nu sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 14272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory -system.physmem.bytes_read::total 19712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 19840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory -system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 710933998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 270983811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 981917808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 710933998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 710933998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 710933998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 270983811 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 981917808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 308 # Number of read requests accepted +system.physmem.num_reads::total 310 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 708661417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 267716535 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 976377953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 708661417 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 708661417 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 708661417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 267716535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 976377953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 310 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 19712 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 19840 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 19712 # Total read bytes from the system interface side +system.physmem.bytesReadSys 19840 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -52,7 +52,7 @@ system.physmem.perBankRdBursts::7 47 # Pe system.physmem.perBankRdBursts::8 68 # Per bank write bursts system.physmem.perBankRdBursts::9 2 # Per bank write bursts system.physmem.perBankRdBursts::10 15 # Per bank write bursts -system.physmem.perBankRdBursts::11 14 # Per bank write bursts +system.physmem.perBankRdBursts::11 16 # Per bank write bursts system.physmem.perBankRdBursts::12 18 # Per bank write bursts system.physmem.perBankRdBursts::13 52 # Per bank write bursts system.physmem.perBankRdBursts::14 15 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19987000 # Total gap between requests +system.physmem.totGap 20232000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 308 # Read request sizes (log2) +system.physmem.readPktSize::6 310 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -187,41 +187,41 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 430.829268 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 282.802413 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.088769 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 282.076610 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.225077 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 14.63% 68.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 9.76% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 17.07% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 7.32% 78.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 3 7.32% 85.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 1568250 # Total ticks spent queuing -system.physmem.totMemAccLat 7343250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5091.72 # Average queueing delay per DRAM burst +system.physmem.totQLat 1648500 # Total ticks spent queuing +system.physmem.totMemAccLat 7461000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5317.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23841.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 981.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24067.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 976.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 981.92 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 976.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.67 # Data bus utilization in percentage -system.physmem.busUtilRead 7.67 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.63 # Data bus utilization in percentage +system.physmem.busUtilRead 7.63 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 258 # Number of row buffer hits during reads +system.physmem.readRowHits 259 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 64892.86 # Average gap between requests -system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined +system.physmem.avgGap 65264.52 # Average gap between requests +system.physmem.pageHitRate 83.55 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ) @@ -231,55 +231,59 @@ system.physmem_0.actBackEnergy 10605420 # En system.physmem_0.preBackEnergy 196500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 12727575 # Total energy per rank (pJ) system.physmem_0.averagePower 803.889152 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 534250 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 681250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15041250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1201200 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1193400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 10488285 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13297980 # Total energy per rank (pJ) -system.physmem_1.averagePower 839.916627 # Core power per rank (mW) +system.physmem_1.totalEnergy 13290180 # Total energy per rank (pJ) +system.physmem_1.averagePower 839.423970 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14869250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 787 # Number of BP lookups -system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 164 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 560 # Number of BTB lookups -system.cpu.branchPred.BTBHits 60 # Number of BTB hits +system.cpu.branchPred.lookups 794 # Number of BP lookups +system.cpu.branchPred.condPredicted 395 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups +system.cpu.branchPred.BTBHits 54 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.714286 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 138 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 9.608541 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 144 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 83 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 83 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 32 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 506 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_hits 510 # DTB read hits +system.cpu.dtb.read_misses 8 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 513 # DTB read accesses +system.cpu.dtb.read_accesses 518 # DTB read accesses system.cpu.dtb.write_hits 307 # DTB write hits system.cpu.dtb.write_misses 6 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 313 # DTB write accesses -system.cpu.dtb.data_hits 813 # DTB hits -system.cpu.dtb.data_misses 13 # DTB misses +system.cpu.dtb.data_hits 817 # DTB hits +system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 826 # DTB accesses -system.cpu.itb.fetch_hits 965 # ITB hits +system.cpu.dtb.data_accesses 831 # DTB accesses +system.cpu.itb.fetch_hits 975 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 978 # ITB accesses +system.cpu.itb.fetch_accesses 988 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,40 +297,75 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 40150 # number of cpu cycles simulated +system.cpu.numCycles 40640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 581 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 603 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 15.531915 # CPI: cycles per instruction -system.cpu.ipc 0.064384 # IPC: instructions per cycle -system.cpu.tickCycles 5369 # Number of cycles that the object actually ticked -system.cpu.idleCycles 34781 # Total number of cycles that the object has spent stopped +system.cpu.cpi 15.721470 # CPI: cycles per instruction +system.cpu.ipc 0.063607 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction +system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction +system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 72.26% # Class of committed instruction +system.cpu.op_class_0::MemRead 419 16.21% 88.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 2585 # Class of committed instruction +system.cpu.tickCycles 5416 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35224 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.313800 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 689 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 48.513757 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 693 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.105882 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.152941 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.313800 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011795 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011795 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.513757 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011844 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011844 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1671 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1671 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 438 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 438 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1679 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1679 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 442 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 442 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 689 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 689 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 689 # number of overall hits -system.cpu.dcache.overall_hits::total 689 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 693 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 693 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 693 # number of overall hits +system.cpu.dcache.overall_hits::total 693 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses @@ -335,38 +374,38 @@ system.cpu.dcache.demand_misses::cpu.data 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4723000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4723000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4723500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4723500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3258500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3258500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7981500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7981500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7981500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7981500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 7982000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7982000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7982000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7982000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 503 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 793 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 793 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 793 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 793 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.122244 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.122244 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 797 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 797 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 797 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 797 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.121272 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.121272 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.146259 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.131148 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.131148 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.131148 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.131148 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77426.229508 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77426.229508 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.130489 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.130489 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.130489 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.130489 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77434.426230 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77434.426230 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 75779.069767 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76745.192308 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76745.192308 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76745.192308 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76745.192308 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76750 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76750 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76750 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76750 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,82 +430,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4442000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4442000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4442500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2017500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2017500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6459500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6459500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6459500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6459500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6460000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6460000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6460000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6460000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107188 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.107188 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107188 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.107188 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76586.206897 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76586.206897 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106650 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.106650 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106650 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.106650 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76594.827586 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76594.827586 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75994.117647 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75994.117647 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.873256 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 742 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.327354 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 119.123012 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 750 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.333333 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.873256 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057555 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057555 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2153 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2153 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 742 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 742 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 742 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 742 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 742 # number of overall hits -system.cpu.icache.overall_hits::total 742 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses -system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16979500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16979500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16979500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16979500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16979500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16979500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 965 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 965 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.231088 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.231088 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.231088 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.231088 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.231088 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.231088 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76141.255605 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76141.255605 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76141.255605 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76141.255605 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76141.255605 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76141.255605 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 119.123012 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.058166 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.058166 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 2175 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2175 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 750 # number of overall hits +system.cpu.icache.overall_hits::total 750 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 225 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 225 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses +system.cpu.icache.overall_misses::total 225 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17203000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17203000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17203000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17203000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17203000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17203000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 975 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 975 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 975 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 975 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 975 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 975 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230769 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.230769 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.230769 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.230769 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.230769 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.230769 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76457.777778 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76457.777778 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76457.777778 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76457.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76457.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76457.777778 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,84 +514,84 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 223 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16756500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16756500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16756500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16756500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16756500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16756500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231088 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.231088 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.231088 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75141.255605 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75141.255605 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75141.255605 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75141.255605 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75141.255605 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75141.255605 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 225 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16978000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16978000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16978000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16978000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16978000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16978000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.230769 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.230769 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.230769 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.230769 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.230769 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.230769 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75457.777778 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75457.777778 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75457.777778 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75457.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 145.780629 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 147.162900 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 283 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 117.989893 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.790736 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003601 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004449 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.239277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.923624 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003639 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004491 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 283 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008636 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 223 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 223 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 58 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 58 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 223 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses +system.cpu.l2cache.demand_misses::total 310 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses -system.cpu.l2cache.overall_misses::total 308 # number of overall misses +system.cpu.l2cache.overall_misses::total 310 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16422000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16422000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4354000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4354000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16422000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6331000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16422000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6331000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16640500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16640500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4354500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4354500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16640500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6331500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22972000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16640500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6331500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22972000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 223 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 223 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 225 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 58 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 58 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 225 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 308 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 223 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 310 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 225 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 308 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 310 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses @@ -567,16 +606,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73641.255605 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73641.255605 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75068.965517 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75068.965517 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73873.376623 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73873.376623 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73957.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73957.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75077.586207 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75077.586207 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73957.777778 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74488.235294 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74103.225806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73957.777778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74488.235294 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74103.225806 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,28 +626,28 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 223 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 223 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 58 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 58 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 310 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14192000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14192000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3774000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3774000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14192000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5481000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19673000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14192000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5481000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19673000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14390500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14390500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3774500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3774500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14390500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5481500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19872000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14390500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5481500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19872000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -623,74 +662,74 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63641.255605 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63641.255605 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65068.965517 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63957.777778 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63957.777778 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65077.586207 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65077.586207 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63957.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64488.235294 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64103.225806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63957.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64488.235294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64103.225806 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 308 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 223 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 225 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 450 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 620 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14400 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 19840 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 310 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 310 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 310 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 334500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadResp 281 # Transaction distribution +system.membus.trans_dist::ReadResp 283 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 281 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 283 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 620 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 620 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19840 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 308 # Request fanout histogram +system.membus.snoop_fanout::samples 310 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 310 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 308 # Request fanout histogram -system.membus.reqLayer0.occupancy 359500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 310 # Request fanout histogram +system.membus.reqLayer0.occupancy 363500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1638750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 8.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1649000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 7d0044f86..4281491aa 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -145,11 +147,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -160,7 +169,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -509,7 +517,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -560,7 +567,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -595,6 +601,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -660,6 +667,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index c35fecd4e..619c657d2 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12363500 # Number of ticks simulated -final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12409500 # Number of ticks simulated +final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 12168 # Simulator instruction rate (inst/s) host_op_rate 12166 # Simulator op (including micro ops) rate (op/s) @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 968010677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 440004853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1408015530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 968010677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 968010677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 968010677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 440004853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1408015530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 964422418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 438373827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1402796245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 964422418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 964422418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 964422418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 438373827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1402796245 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 12267000 # Total gap between requests +system.physmem.totGap 12313000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -200,27 +200,27 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 1685750 # Total ticks spent queuing -system.physmem.totMemAccLat 6785750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1652750 # Total ticks spent queuing +system.physmem.totMemAccLat 6752750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6197.61 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6076.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24947.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1408.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24826.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1402.80 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1408.02 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1402.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.00 # Data bus utilization in percentage -system.physmem.busUtilRead 11.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.96 # Data bus utilization in percentage +system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45099.26 # Average gap between requests +system.physmem.avgGap 45268.38 # Average gap between requests system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) @@ -250,36 +250,40 @@ system.physmem_1.memoryStateTime::REF 260000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 890 # Number of BP lookups -system.cpu.branchPred.condPredicted 443 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 195 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 616 # Number of BTB lookups -system.cpu.branchPred.BTBHits 164 # Number of BTB hits +system.cpu.branchPred.lookups 1003 # Number of BP lookups +system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 688 # Number of BTB lookups +system.cpu.branchPred.BTBHits 176 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 26.623377 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 186 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 25.581395 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 101 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 98 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 719 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses +system.cpu.dtb.read_hits 712 # DTB read hits +system.cpu.dtb.read_misses 13 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 729 # DTB read accesses -system.cpu.dtb.write_hits 347 # DTB write hits -system.cpu.dtb.write_misses 16 # DTB write misses +system.cpu.dtb.read_accesses 725 # DTB read accesses +system.cpu.dtb.write_hits 349 # DTB write hits +system.cpu.dtb.write_misses 17 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 363 # DTB write accesses -system.cpu.dtb.data_hits 1066 # DTB hits -system.cpu.dtb.data_misses 26 # DTB misses +system.cpu.dtb.write_accesses 366 # DTB write accesses +system.cpu.dtb.data_hits 1061 # DTB hits +system.cpu.dtb.data_misses 30 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1092 # DTB accesses -system.cpu.itb.fetch_hits 802 # ITB hits -system.cpu.itb.fetch_misses 35 # ITB misses +system.cpu.dtb.data_accesses 1091 # DTB accesses +system.cpu.itb.fetch_hits 878 # ITB hits +system.cpu.itb.fetch_misses 32 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 837 # ITB accesses +system.cpu.itb.fetch_accesses 910 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,233 +297,234 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 24728 # number of cpu cycles simulated +system.cpu.numCycles 24820 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4265 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 5512 # Number of instructions fetch has processed -system.cpu.fetch.Branches 890 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 350 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1015 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 436 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 4371 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6065 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1003 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 400 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1173 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1206 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1146 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 802 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 146 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6733 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.818654 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.224131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 878 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6955 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.872035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.274710 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5799 86.13% 86.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30 0.45% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 91 1.35% 87.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 76 1.13% 89.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 118 1.75% 90.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 72 1.07% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40 0.59% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 56 0.83% 93.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 451 6.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5922 85.15% 85.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 27 0.39% 85.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 100 1.44% 86.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 87 1.25% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 141 2.03% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 81 1.16% 91.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 46 0.66% 92.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 76 1.09% 93.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 475 6.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6733 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.035992 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.222905 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5190 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 505 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 865 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 28 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 145 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 132 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 6955 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.040411 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.244359 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5210 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 623 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 919 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 4839 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 5274 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 268 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 145 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5257 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5285 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 327 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 824 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 4680 # Number of instructions processed by rename +system.cpu.rename.RunCycles 881 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5069 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenamedOperands 3347 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5270 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.RenamedOperands 3638 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5669 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5662 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1579 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 1870 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 52 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 418 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.rename.skidInsts 62 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 846 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4078 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4387 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3608 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 32 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1696 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 859 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3758 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 28 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2005 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1025 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6733 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.535868 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.279819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 6955 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.540331 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.279888 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5352 79.49% 79.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 449 6.67% 86.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 318 4.72% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 240 3.56% 94.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 185 2.75% 97.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 110 1.63% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 49 0.73% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 21 0.31% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5508 79.19% 79.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 469 6.74% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 342 4.92% 90.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 254 3.65% 94.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 193 2.77% 97.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 103 1.48% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 56 0.81% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 20 0.29% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6955 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 8.70% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 39 56.52% 65.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 24 34.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 31 50.82% 60.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 24 39.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2482 68.79% 68.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 757 20.98% 89.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 368 10.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2627 69.90% 69.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 757 20.14% 90.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 373 9.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3608 # Type of FU issued -system.cpu.iq.rate 0.145907 # Inst issue rate -system.cpu.iq.fu_busy_cnt 69 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019124 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 5777 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3273 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3758 # Type of FU issued +system.cpu.iq.rate 0.151410 # Inst issue rate +system.cpu.iq.fu_busy_cnt 61 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14547 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6395 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3419 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3670 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3812 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 380 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 431 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 124 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 91 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 145 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 4365 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 29 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 418 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 297 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 4700 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 846 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 20 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 120 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 140 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3509 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 730 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 99 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 132 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 165 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3634 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 727 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 124 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 281 # number of nop insts executed +system.cpu.iew.exec_nop 307 # number of nop insts executed system.cpu.iew.exec_refs 1093 # number of memory reference insts executed -system.cpu.iew.exec_branches 570 # Number of branches executed -system.cpu.iew.exec_stores 363 # Number of stores executed -system.cpu.iew.exec_rate 0.141904 # Inst execution rate -system.cpu.iew.wb_sent 3329 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3279 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1560 # num instructions producing a value -system.cpu.iew.wb_consumers 1998 # num instructions consuming a value -system.cpu.iew.wb_rate 0.132603 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.780781 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 1787 # The number of squashed insts skipped by commit +system.cpu.iew.exec_branches 599 # Number of branches executed +system.cpu.iew.exec_stores 366 # Number of stores executed +system.cpu.iew.exec_rate 0.146414 # Inst execution rate +system.cpu.iew.wb_sent 3483 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3425 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1633 # num instructions producing a value +system.cpu.iew.wb_consumers 2097 # num instructions consuming a value +system.cpu.iew.wb_rate 0.137994 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.778732 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 2122 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 122 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6402 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.402374 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273029 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.393884 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.249766 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5545 86.61% 86.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194 3.03% 89.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 304 4.75% 94.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 116 1.81% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 62 0.97% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 60 0.94% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 35 0.55% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.31% 98.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 66 1.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5669 86.68% 86.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 198 3.03% 89.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 318 4.86% 94.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 118 1.80% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 63 0.96% 97.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.81% 98.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 37 0.57% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23 0.35% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6540 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -565,101 +570,101 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 66 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 10452 # The number of ROB reads -system.cpu.rob.rob_writes 9060 # The number of ROB writes -system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17995 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 10930 # The number of ROB reads +system.cpu.rob.rob_writes 9815 # The number of ROB writes +system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17865 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.359447 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.359447 # CPI: Total CPI of All Threads -system.cpu.ipc 0.096530 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.096530 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4249 # number of integer regfile reads -system.cpu.int_regfile_writes 2511 # number of integer regfile writes +system.cpu.cpi 10.397989 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.397989 # CPI: Total CPI of All Threads +system.cpu.ipc 0.096172 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.096172 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4383 # number of integer regfile reads +system.cpu.int_regfile_writes 2640 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.334739 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 716 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 45.439304 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 735 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.423529 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.647059 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.334739 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011068 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011068 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.439304 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011094 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1873 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1873 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 503 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 503 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1919 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1919 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 522 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 522 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 716 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 716 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 716 # number of overall hits -system.cpu.dcache.overall_hits::total 716 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 735 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 735 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 735 # number of overall hits +system.cpu.dcache.overall_hits::total 735 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 178 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 178 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 178 # number of overall misses -system.cpu.dcache.overall_misses::total 178 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6583000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6583000 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses +system.cpu.dcache.overall_misses::total 182 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6673500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6673500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5672000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5672000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12255000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12255000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12255000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12255000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 600 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 12345500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12345500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12345500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12345500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 623 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 623 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 894 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 894 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 894 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 894 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.161667 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.161667 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 917 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 917 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 917 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 917 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.162119 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.162119 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.199105 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.199105 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.199105 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.199105 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67865.979381 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67865.979381 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.198473 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.198473 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.198473 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.198473 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66074.257426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66074.257426 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70024.691358 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 70024.691358 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68848.314607 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68848.314607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68848.314607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68848.314607 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 292 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67832.417582 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67832.417582 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67832.417582 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67832.417582 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 256 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.444444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 97 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -668,82 +673,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4810000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4810000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4797000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4797000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6661000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6661000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6661000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6661000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.101667 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.101667 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6648000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6648000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6648000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6648000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.097913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.097913 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.095078 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.095078 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.095078 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.095078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78852.459016 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78852.459016 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.092694 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.092694 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78639.344262 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78639.344262 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78364.705882 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78364.705882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78364.705882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78364.705882 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 90.143737 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 552 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 90.399218 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 625 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2.951872 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.342246 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 90.143737 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044015 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 90.399218 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044140 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044140 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1791 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1791 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 552 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 552 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 552 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 552 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 552 # number of overall hits -system.cpu.icache.overall_hits::total 552 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses -system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18739499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18739499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18739499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18739499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18739499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18739499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 802 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 802 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.311721 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.311721 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.311721 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.311721 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.311721 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.311721 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74957.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74957.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74957.996000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74957.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74957.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74957.996000 # average overall miss latency +system.cpu.icache.tags.tag_accesses 1943 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1943 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 625 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 625 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 625 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 625 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 625 # number of overall hits +system.cpu.icache.overall_hits::total 625 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses +system.cpu.icache.overall_misses::total 253 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18863999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18863999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18863999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18863999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18863999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18863999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 878 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 878 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 878 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 878 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.288155 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.288155 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.288155 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.288155 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.288155 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.288155 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74561.260870 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74561.260870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74561.260870 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74561.260870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74561.260870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74561.260870 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -752,48 +757,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14179499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14179499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14179499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14179499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14179499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14179499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.233167 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.233167 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.233167 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.233167 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.233167 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.233167 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75826.197861 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75826.197861 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75826.197861 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75826.197861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75826.197861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75826.197861 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14160499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14160499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14160499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14160499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14160499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14160499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.212984 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.212984 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.212984 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75724.593583 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75724.593583 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 118.927175 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 119.261302 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.302552 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.624623 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002756 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003629 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.557444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.703859 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002764 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000876 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003640 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -814,16 +819,16 @@ system.cpu.l2cache.overall_misses::cpu.data 85 # system.cpu.l2cache.overall_misses::total 272 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1813500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1813500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13898000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13898000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4718500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4718500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13898000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6532000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20430000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13898000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6532000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20430000 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13879000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13879000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4705500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4705500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13879000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6519000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20398000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13879000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6519000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20398000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) @@ -850,16 +855,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74320.855615 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74320.855615 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77352.459016 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77352.459016 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74320.855615 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76847.058824 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75110.294118 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74320.855615 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76847.058824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75110.294118 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74219.251337 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74219.251337 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77139.344262 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77139.344262 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74219.251337 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76694.117647 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74992.647059 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74219.251337 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76694.117647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74992.647059 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -882,16 +887,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 85 system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12028000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12028000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12028000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5682000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17710000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12028000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5682000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17710000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12009000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12009000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4095500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4095500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12009000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5669000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17678000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12009000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5669000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17678000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -906,16 +911,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64320.855615 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64320.855615 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67352.459016 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67352.459016 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64320.855615 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64219.251337 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64219.251337 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67139.344262 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67139.344262 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -971,9 +976,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 335500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1441000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1440000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 2db41bef8..164e856da 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -151,6 +153,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini index 8e85722f1..214f11946 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr index f6a02f021..1c18978fa 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr @@ -4,6 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 95074a37b..2ad2eb8ea 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr index f6a02f021..1c18978fa 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr @@ -4,6 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 7ee7deae6..c78531ccf 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr index f6a02f021..1c18978fa 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr @@ -4,6 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 8190e6bb4..18d7c2ab4 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr index f6a02f021..1c18978fa 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr @@ -4,6 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 4edb3028e..538bb6cd3 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr index f6a02f021..1c18978fa 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr @@ -4,6 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 16a0ec4c3..ea2d2a5a5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -181,7 +181,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -216,6 +215,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -281,6 +281,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 |