diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha/tru64')
26 files changed, 3165 insertions, 1725 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini index ccd9350bc..220cfeeae 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout index 115f46689..fff19a530 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:24 -gem5 executing on e108600-lin, pid 39579 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28071 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 20329000 because target called exit() +Exiting @ tick 22083000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 95775a988..a6e87b576 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20616000 # Number of ticks simulated -final_tick 20616000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 22083000 # Number of ticks simulated +final_tick 22083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91304 # Simulator instruction rate (inst/s) -host_op_rate 91266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 727585147 # Simulator tick rate (ticks/s) -host_mem_usage 252076 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 143746 # Simulator instruction rate (inst/s) +host_op_rate 143654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1226490189 # Simulator tick rate (ticks/s) +host_mem_usage 251004 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 19840 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 310 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 698486612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 263872720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 962359333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 698486612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 698486612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 698486612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 263872720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 962359333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 652085314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 246343341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 898428656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 652085314 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 652085314 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 652085314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 246343341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 898428656 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 310 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20527500 # Total gap between requests +system.physmem.totGap 21988500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -188,77 +188,87 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 424.585366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 277.937119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.553388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 281.212133 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.776868 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5 12.20% 51.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 4.88% 56.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 14.63% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 14.63% 53.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 4.88% 58.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 7.32% 65.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 4.88% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 17.07% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 4.88% 92.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 1590750 # Total ticks spent queuing -system.physmem.totMemAccLat 7403250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3615250 # Total ticks spent queuing +system.physmem.totMemAccLat 9427750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5131.45 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11662.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23881.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 962.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30412.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 898.43 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 962.36 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 898.43 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.52 # Data bus utilization in percentage -system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.02 # Data bus utilization in percentage +system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 260 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 66217.74 # Average gap between requests +system.physmem.avgGap 70930.65 # Average gap between requests system.physmem.pageHitRate 83.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 787800 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 114240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 45540 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 885360 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12758055 # Total energy per rank (pJ) -system.physmem_0.averagePower 805.814306 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 727750 # Time in different power states +system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1636470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 7529700 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 729120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12201870 # Total energy per rank (pJ) +system.physmem_0.averagePower 552.527084 # Core power per rank (mW) +system.physmem_0.totalIdleTime 18356500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 27500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1162200 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1898500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3124750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 16512250 # Time in different power states +system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 110055 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1328040 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10417320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 361500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13250265 # Total energy per rank (pJ) -system.physmem_1.averagePower 836.902890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 560000 # Time in different power states +system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2565570 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 217440 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 7221900 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12935685 # Total energy per rank (pJ) +system.physmem_1.averagePower 585.755816 # Core power per rank (mW) +system.physmem_1.totalIdleTime 15168500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 498000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14766250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 794 # Number of BP lookups -system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 53000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5182750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 15829250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 793 # Number of BP lookups +system.cpu.branchPred.condPredicted 395 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 561 # Number of BTB lookups system.cpu.branchPred.BTBHits 54 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 9.608541 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 9.625668 # BTB Hit Percentage system.cpu.branchPred.usedRAS 144 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 83 # Number of indirect predictor lookups. @@ -282,10 +292,10 @@ system.cpu.dtb.data_hits 813 # DT system.cpu.dtb.data_misses 12 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 825 # DTB accesses -system.cpu.itb.fetch_hits 979 # ITB hits +system.cpu.itb.fetch_hits 980 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 992 # ITB accesses +system.cpu.itb.fetch_accesses 993 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20616000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 41232 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22083000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44166 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed system.cpu.discardedOps 573 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 15.950484 # CPI: cycles per instruction -system.cpu.ipc 0.062694 # IPC: instructions per cycle +system.cpu.cpi 17.085493 # CPI: cycles per instruction +system.cpu.ipc 0.058529 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction @@ -344,25 +354,25 @@ system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 2585 # Class of committed instruction -system.cpu.tickCycles 5423 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35809 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 5429 # Number of cycles that the object actually ticked +system.cpu.idleCycles 38737 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.342284 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.291787 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.342284 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.291787 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011790 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011790 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1673 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1673 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits @@ -379,14 +389,14 @@ system.cpu.dcache.demand_misses::cpu.data 102 # n system.cpu.dcache.demand_misses::total 102 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 102 # number of overall misses system.cpu.dcache.overall_misses::total 102 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4617500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4617500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3301000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3301000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7918500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7918500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7918500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7918500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5143500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5143500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3553000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3553000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8696500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8696500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8696500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8696500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 500 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 500 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -403,14 +413,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.128463 system.cpu.dcache.demand_miss_rate::total 0.128463 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.128463 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.128463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78262.711864 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78262.711864 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76767.441860 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76767.441860 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77632.352941 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77632.352941 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87177.966102 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87177.966102 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82627.906977 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82627.906977 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85259.803922 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85259.803922 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85259.803922 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85259.803922 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,14 +443,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4487000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4487000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2044500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2044500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6531500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6531500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6531500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6531500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5007000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5007000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2203500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2203500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7210500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7210500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116000 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116000 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -449,67 +459,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107053 system.cpu.dcache.demand_mshr_miss_rate::total 0.107053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.107053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77362.068966 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77362.068966 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86327.586207 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86327.586207 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81611.111111 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81611.111111 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84829.411765 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84829.411765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84829.411765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84829.411765 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 119.307121 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 754 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 118.973491 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 755 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.351111 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.355556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 119.307121 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.058255 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.058255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 118.973491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.058093 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.058093 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2183 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2183 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 754 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 754 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 754 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 754 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 754 # number of overall hits -system.cpu.icache.overall_hits::total 754 # number of overall hits +system.cpu.icache.tags.tag_accesses 2185 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2185 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 755 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 755 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 755 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 755 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 755 # number of overall hits +system.cpu.icache.overall_hits::total 755 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 225 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 225 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.icache.overall_misses::total 225 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17383000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17383000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17383000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17383000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17383000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17383000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 979 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 979 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 979 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 979 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229826 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229826 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229826 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229826 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229826 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229826 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77257.777778 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77257.777778 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77257.777778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77257.777778 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18729500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18729500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18729500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18729500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18729500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18729500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229592 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229592 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229592 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229592 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229592 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229592 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83242.222222 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 83242.222222 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 83242.222222 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 83242.222222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 83242.222222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 83242.222222 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,43 +532,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 225 system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17158000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17158000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17158000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229826 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.229826 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.229826 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76257.777778 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18504500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18504500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18504500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18504500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18504500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18504500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229592 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.229592 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.229592 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82242.222222 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82242.222222 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82242.222222 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82242.222222 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82242.222222 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82242.222222 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 167.807293 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 167.412677 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 310 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.421716 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.385576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003644 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001477 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.080474 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.332203 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003634 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001475 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005109 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009460 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses @@ -571,18 +581,18 @@ system.cpu.l2cache.demand_misses::total 310 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 310 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2004000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2004000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16820500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16820500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4399000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4399000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16820500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6403000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23223500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16820500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6403000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23223500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2163000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2163000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18167000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 18167000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4919000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4919000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18167000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7082000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25249000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18167000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7082000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25249000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses) @@ -607,18 +617,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74757.777778 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74757.777778 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75844.827586 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75844.827586 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74914.516129 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74914.516129 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80111.111111 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80111.111111 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80742.222222 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80742.222222 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84810.344828 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84810.344828 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80742.222222 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83317.647059 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81448.387097 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80742.222222 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83317.647059 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81448.387097 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,18 +647,18 @@ system.cpu.l2cache.demand_mshr_misses::total 310 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1734000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1734000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14570500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14570500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3819000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3819000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14570500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5553000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20123500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14570500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5553000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20123500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 15917000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 15917000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4339000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4339000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15917000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6232000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22149000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15917000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6232000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22149000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -661,25 +671,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64757.777778 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64757.777778 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65844.827586 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65844.827586 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70111.111111 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70111.111111 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70742.222222 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70742.222222 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74810.344828 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74810.344828 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70742.222222 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73317.647059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71448.387097 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70742.222222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73317.647059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71448.387097 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -705,9 +715,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 310 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.membus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. @@ -716,7 +726,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 283 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution @@ -737,9 +747,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 310 # Request fanout histogram -system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 362500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.respLayer1.occupancy 1648750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 8.0 # Layer utilization (%) +system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 39c72e110..ff6825b17 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 5515360ee..35f169b23 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:24 -gem5 executing on e108600-lin, pid 39577 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:49 +gem5 executing on e108600-lin, pid 28097 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12409500 because target called exit() +Exiting @ tick 13358500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index cdae5e837..cecea8f6e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12542500 # Number of ticks simulated -final_tick 12542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13358500 # Number of ticks simulated +final_tick 13358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60996 # Simulator instruction rate (inst/s) -host_op_rate 60977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 320317516 # Simulator tick rate (ticks/s) -host_mem_usage 253100 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 53089 # Simulator instruction rate (inst/s) +host_op_rate 53060 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 296795260 # Simulator tick rate (ticks/s) +host_mem_usage 251260 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 17408 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 954195735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 433725334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1387921068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 954195735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 954195735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 954195735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 433725334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1387921068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 895908972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 407231351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1303140323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 895908972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 895908972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 895908972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 407231351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1303140323 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 12445000 # Total gap between requests +system.physmem.totGap 13255000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 155 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -188,81 +188,91 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 235.532687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 344.140835 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 8.33% 63.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 8.33% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 5.56% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4 11.11% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 11.11% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 16.67% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 5.56% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 2.78% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 2.78% 83.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 1866000 # Total ticks spent queuing -system.physmem.totMemAccLat 6966000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3364250 # Total ticks spent queuing +system.physmem.totMemAccLat 8464250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6860.29 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12368.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25610.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1387.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31118.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1303.14 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1387.92 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1303.14 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.84 # Data bus utilization in percentage -system.physmem.busUtilRead 10.84 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.18 # Data bus utilization in percentage +system.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 226 # Number of row buffer hits during reads +system.physmem.readRowHits 224 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45753.68 # Average gap between requests -system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 48731.62 # Average gap between requests +system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 99960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 37950 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) -system.physmem_0.averagePower 832.600901 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states +system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1355460 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 21600 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 4583370 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 107040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 7576860 # Total energy per rank (pJ) +system.physmem_0.averagePower 567.183307 # Core power per rank (mW) +system.physmem_0.totalIdleTime 10278500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 28500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7777500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 279000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2735250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 10055750 # Time in different power states +system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 98670 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1185240 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5198400 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 267750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 6961155 # Total energy per rank (pJ) -system.physmem_1.averagePower 865.142768 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 432500 # Time in different power states +system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1822290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 183840 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 4050420 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 8198340 # Total energy per rank (pJ) +system.physmem_1.averagePower 613.705624 # Core power per rank (mW) +system.physmem_1.totalIdleTime 8246250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 450500 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7367500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1001 # Number of BP lookups -system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3767500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 8879250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 994 # Number of BP lookups +system.cpu.branchPred.condPredicted 488 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 687 # Number of BTB lookups -system.cpu.branchPred.BTBHits 176 # Number of BTB hits +system.cpu.branchPred.BTBLookups 684 # Number of BTB lookups +system.cpu.branchPred.BTBHits 175 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.618632 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 25.584795 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 100 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 99 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 97 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -270,22 +280,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 712 # DTB read hits -system.cpu.dtb.read_misses 13 # DTB read misses +system.cpu.dtb.read_hits 705 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 725 # DTB read accesses +system.cpu.dtb.read_accesses 715 # DTB read accesses system.cpu.dtb.write_hits 349 # DTB write hits -system.cpu.dtb.write_misses 17 # DTB write misses +system.cpu.dtb.write_misses 16 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 366 # DTB write accesses -system.cpu.dtb.data_hits 1061 # DTB hits -system.cpu.dtb.data_misses 30 # DTB misses +system.cpu.dtb.write_accesses 365 # DTB write accesses +system.cpu.dtb.data_hits 1054 # DTB hits +system.cpu.dtb.data_misses 26 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1091 # DTB accesses -system.cpu.itb.fetch_hits 877 # ITB hits +system.cpu.dtb.data_accesses 1080 # DTB accesses +system.cpu.itb.fetch_hits 872 # ITB hits system.cpu.itb.fetch_misses 32 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 909 # ITB accesses +system.cpu.itb.fetch_accesses 904 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,193 +309,193 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 12542500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 25086 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 13358500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 26718 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4377 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6059 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1001 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 399 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 4379 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6026 # Number of instructions fetch has processed +system.cpu.fetch.Branches 994 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 395 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1172 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 877 # Number of cache lines fetched +system.cpu.fetch.CacheLines 872 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 147 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6970 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.869297 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.271813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.858649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.260497 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5938 85.19% 85.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 27 0.39% 85.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 100 1.43% 87.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 87 1.25% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 141 2.02% 90.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 81 1.16% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 45 0.65% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 76 1.09% 93.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 475 6.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5993 85.39% 85.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 27 0.38% 85.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 97 1.38% 87.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 87 1.24% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 140 1.99% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 81 1.15% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 45 0.64% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 75 1.07% 93.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 473 6.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6970 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.039903 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.241529 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5221 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 627 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 919 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 7018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037203 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.225541 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5261 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 642 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 913 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 39 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5274 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 5228 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 263 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5296 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 881 # Number of cycles rename is running +system.cpu.rename.IdleCycles 5336 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 333 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 302 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 873 # Number of cycles rename is running system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5069 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 5015 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3638 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5669 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5662 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 3598 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5603 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5596 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1870 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 1830 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 62 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 846 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.memDep0.insertedLoads 838 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 424 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4387 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4336 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3758 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 28 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2005 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1025 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3724 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1954 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 987 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6970 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.539168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.278867 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.530636 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.266302 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5524 79.25% 79.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 467 6.70% 85.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 343 4.92% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 254 3.64% 94.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 193 2.77% 97.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 103 1.48% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 56 0.80% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 20 0.29% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5580 79.51% 79.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 466 6.64% 86.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 341 4.86% 91.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 254 3.62% 94.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 190 2.71% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 104 1.48% 98.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 55 0.78% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 20 0.28% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7018 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 31 50.82% 60.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 24 39.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 10.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 30 50.00% 60.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 24 40.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2627 69.90% 69.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 757 20.14% 90.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 373 9.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2606 69.98% 69.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 745 20.01% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 372 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3758 # Type of FU issued -system.cpu.iq.rate 0.149805 # Inst issue rate -system.cpu.iq.fu_busy_cnt 61 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14562 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6395 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3419 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3724 # Type of FU issued +system.cpu.iq.rate 0.139382 # Inst issue rate +system.cpu.iq.fu_busy_cnt 60 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016112 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14532 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6293 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3394 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3812 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3777 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 431 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 423 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 130 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 42 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 299 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 304 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 4700 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 4648 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 846 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 838 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 424 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -493,41 +503,41 @@ system.cpu.iew.memOrderViolationEvents 4 # Nu system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 132 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 165 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3634 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 727 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 3600 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 717 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 124 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 307 # number of nop insts executed -system.cpu.iew.exec_refs 1093 # number of memory reference insts executed -system.cpu.iew.exec_branches 599 # Number of branches executed -system.cpu.iew.exec_stores 366 # Number of stores executed -system.cpu.iew.exec_rate 0.144862 # Inst execution rate -system.cpu.iew.wb_sent 3483 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3425 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1633 # num instructions producing a value -system.cpu.iew.wb_consumers 2097 # num instructions consuming a value -system.cpu.iew.wb_rate 0.136530 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.778732 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2122 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 306 # number of nop insts executed +system.cpu.iew.exec_refs 1082 # number of memory reference insts executed +system.cpu.iew.exec_branches 595 # Number of branches executed +system.cpu.iew.exec_stores 365 # Number of stores executed +system.cpu.iew.exec_rate 0.134741 # Inst execution rate +system.cpu.iew.wb_sent 3453 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3400 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1619 # num instructions producing a value +system.cpu.iew.wb_consumers 2076 # num instructions consuming a value +system.cpu.iew.wb_rate 0.127255 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.779865 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 2070 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6555 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.392982 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.248476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 6610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.389713 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.245121 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5684 86.71% 86.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 198 3.02% 89.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 318 4.85% 94.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 118 1.80% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 63 0.96% 97.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.81% 98.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 37 0.56% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23 0.35% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 61 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5740 86.84% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 197 2.98% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 319 4.83% 94.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 117 1.77% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 63 0.95% 97.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.80% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 36 0.54% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23 0.35% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 62 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6555 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6610 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -573,47 +583,47 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 10945 # The number of ROB reads -system.cpu.rob.rob_writes 9815 # The number of ROB writes +system.cpu.commit.bw_lim_events 62 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 10947 # The number of ROB reads +system.cpu.rob.rob_writes 9704 # The number of ROB writes system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18116 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19700 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.509426 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.509426 # CPI: Total CPI of All Threads -system.cpu.ipc 0.095153 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.095153 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4383 # number of integer regfile reads -system.cpu.int_regfile_writes 2640 # number of integer regfile writes +system.cpu.cpi 11.193129 # CPI: Cycles Per Instruction +system.cpu.cpi_total 11.193129 # CPI: Total CPI of All Threads +system.cpu.ipc 0.089341 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.089341 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4344 # number of integer regfile reads +system.cpu.int_regfile_writes 2618 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.419736 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 735 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 45.378002 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.647059 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.419736 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011089 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011089 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.378002 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011079 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011079 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1919 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1919 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 522 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 522 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1935 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1935 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 530 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 530 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 735 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 735 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 735 # number of overall hits -system.cpu.dcache.overall_hits::total 735 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits +system.cpu.dcache.overall_hits::total 743 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses @@ -622,43 +632,43 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6754500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6754500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5744000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5744000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12498500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12498500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12498500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 623 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 623 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7124500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7124500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6134000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6134000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13258500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13258500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13258500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13258500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 631 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 631 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 917 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 917 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 917 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 917 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.162119 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.162119 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 925 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 925 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 925 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 925 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.160063 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.160063 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.198473 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.198473 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.198473 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.198473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66876.237624 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66876.237624 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70913.580247 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70913.580247 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68673.076923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68673.076923 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 260 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.196757 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.196757 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.196757 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.196757 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70539.603960 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70539.603960 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75728.395062 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75728.395062 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72848.901099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72848.901099 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits @@ -676,138 +686,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1875000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1875000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6733000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6733000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6733000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6733000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.097913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.097913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5157500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5157500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2004000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2004000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7161500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7161500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7161500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7161500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096672 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.092694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.092694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79639.344262 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79639.344262 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78125 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78125 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79211.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79211.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79211.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79211.764706 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091892 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091892 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091892 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091892 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84549.180328 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84549.180328 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84252.941176 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84252.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84252.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84252.941176 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 90.302659 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 624 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 89.996713 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 618 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.336898 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.304813 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 90.302659 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044093 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044093 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 89.996713 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.043944 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.043944 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1941 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1941 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 624 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 624 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 624 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 624 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 624 # number of overall hits -system.cpu.icache.overall_hits::total 624 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses -system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19081499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19081499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19081499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19081499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19081499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19081499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 877 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 877 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 877 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 877 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.288483 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.288483 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.288483 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.288483 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.288483 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.288483 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75420.944664 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75420.944664 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75420.944664 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75420.944664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75420.944664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75420.944664 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 1931 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1931 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 618 # number of overall hits +system.cpu.icache.overall_hits::total 618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 254 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 254 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 254 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 254 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 254 # number of overall misses +system.cpu.icache.overall_misses::total 254 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20808999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20808999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20808999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20808999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20808999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20808999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 872 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 872 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 872 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 872 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.291284 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.291284 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.291284 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.291284 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.291284 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.291284 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81925.192913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 81925.192913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 81925.192913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 81925.192913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 81925.192913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 81925.192913 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14560999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14560999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14560999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14560999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14560999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14560999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.213227 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.213227 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.213227 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77866.304813 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77866.304813 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77866.304813 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77866.304813 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77866.304813 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77866.304813 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15635499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15635499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15635499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15635499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15635499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15635499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.214450 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.214450 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.214450 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83612.294118 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83612.294118 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83612.294118 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83612.294118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83612.294118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83612.294118 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 135.950101 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 135.588512 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 272 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.459206 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.490894 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002761 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001388 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.143699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.444813 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002751 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001387 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004138 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 272 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008301 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses @@ -820,18 +830,18 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1837500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1837500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14279500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 14279500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4766500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4766500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14279500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6604000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20883500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14279500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6604000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20883500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1966500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1966500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15354000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 15354000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5066000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5066000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15354000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7032500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22386500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15354000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7032500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22386500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) @@ -856,18 +866,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76360.962567 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76360.962567 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78139.344262 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78139.344262 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76777.573529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76777.573529 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81937.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81937.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82106.951872 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82106.951872 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83049.180328 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83049.180328 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82303.308824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82303.308824 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,18 +896,18 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1597500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1597500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12409500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12409500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4156500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4156500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12409500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5754000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18163500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12409500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5754000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18163500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1726500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1726500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13484000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13484000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4456000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4456000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13484000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6182500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19666500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13484000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6182500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19666500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -910,25 +920,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66360.962567 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66360.962567 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68139.344262 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68139.344262 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71937.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71937.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72106.951872 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72106.951872 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73049.180328 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73049.180328 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution @@ -954,9 +964,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. @@ -965,7 +975,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution @@ -987,8 +997,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram system.membus.reqLayer0.occupancy 337500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1440000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.5 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1437500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini index 214f11946..41209dc7f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,10 +270,15 @@ children=directory requestToDir responseFromDir responseFromMemory responseToDir buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=6 eventq_index=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -311,6 +337,7 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED enable_prefetch=false eventq_index=0 l1_request_latency=2 @@ -319,6 +346,10 @@ l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 optionalQueue=system.ruby.l1_cntrl0.optionalQueue +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null prefetcher=system.ruby.l1_cntrl0.prefetcher recycle_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache @@ -447,17 +478,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -480,10 +516,15 @@ L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 l2_request_latency=2 l2_response_latency=2 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache @@ -574,18 +615,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -748,42 +794,216 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 +power_model=Null router_id=0 virt_nets=3 @@ -875,8 +1095,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 +power_model=Null router_id=1 virt_nets=3 @@ -968,8 +1194,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 +power_model=Null router_id=2 virt_nets=3 @@ -1061,8 +1293,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 +power_model=Null router_id=3 virt_nets=3 @@ -1195,9 +1433,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr index 1c18978fa..63982fce4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr @@ -4,9 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout index 321d1816d..fcadeb2be 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout +Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:01:33 -gem5 started Jan 21 2016 14:02:10 -gem5 executing on zizzer, pid 44711 -command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level +gem5 compiled Oct 13 2016 20:28:06 +gem5 started Oct 13 2016 20:28:32 +gem5 executing on e108600-lin, pid 8237 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 45733 because target called exit() +Exiting @ tick 48659 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 5ca935512..d4dee56c3 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000046 # Number of seconds simulated -sim_ticks 45733 # Number of ticks simulated -final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000049 # Number of seconds simulated +sim_ticks 48659 # Number of ticks simulated +final_tick 48659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 61876 # Simulator instruction rate (inst/s) -host_op_rate 61863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1097622 # Simulator tick rate (ticks/s) -host_mem_usage 452416 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 43978 # Simulator instruction rate (inst/s) +host_op_rate 43962 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 829814 # Simulator tick rate (ticks/s) +host_mem_usage 410700 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 35008 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 35008 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6592 # Number of bytes written to this memory @@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 547 # system.mem_ctrls.num_reads::total 547 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 103 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 103 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 765486629 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 765486629 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 144140992 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 144140992 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 909627621 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 909627621 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 719455805 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 719455805 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 135473396 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 135473396 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 854929201 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 854929201 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 547 # Number of read requests accepted system.mem_ctrls.writeReqs 103 # Number of write requests accepted system.mem_ctrls.readBursts 547 # Number of DRAM read bursts, including those serviced by the write queue @@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 45654 # Total gap between requests +system.mem_ctrls.totGap 48574 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 74 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 358.054054 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 233.275053 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 307.922241 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 18 24.32% 24.32% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 18 24.32% 48.65% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 8 10.81% 59.46% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 4 5.41% 64.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 9 12.16% 77.03% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 7 9.46% 86.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 3 4.05% 90.54% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1 1.35% 91.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 6 8.11% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 74 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 83 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 339.277108 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 221.785975 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 292.728223 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 23 27.71% 27.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 19 22.89% 50.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6 7.23% 57.83% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 10 12.05% 69.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 11 13.25% 83.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 4 4.82% 87.95% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 3.61% 91.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 3.61% 95.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 4 4.82% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 83 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 268 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 268.000000 # Reads before turning the bus around for writes @@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 2733 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 11055 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 5659 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 13981 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 2190 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.24 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 12.92 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.24 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 612.95 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 22.39 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 765.49 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 144.14 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.92 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 576.09 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 21.04 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 719.46 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 135.47 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.96 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.79 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.17 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.67 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.50 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.16 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 22.48 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 356 # Number of row buffer hits during reads +system.mem_ctrls.readRowHits 349 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.28 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 79.68 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 70.24 # Average gap between requests -system.mem_ctrls.pageHitRate 76.65 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 143640 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 79800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1797120 # Energy for read commands per rank (pJ) +system.mem_ctrls.avgGap 74.73 # Average gap between requests +system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 199920 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 92736 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2124864 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 26498844 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 269400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 31331604 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 799.479561 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 528 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 37581 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 362880 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 201600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2882880 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 26204040 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 528000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 32888088 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 839.195917 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 754 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 37150 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.mem_ctrls_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 3071616 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 85248 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 18833256 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 153600 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 28249080 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 580.552005 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 41659 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 54 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 400 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 5344 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 41301 # Time in different power states +system.mem_ctrls_1.actEnergy 442680 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 227976 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2878848 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 4289136 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 272256 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 17021568 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 466944 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 29420880 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 604.633881 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 37647 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 541 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 1216 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 8014 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 37328 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 45733 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45733 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 48659 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 48659 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 45733 # Number of busy cycles +system.cpu.num_busy_cycles 48659 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 3612 # delay histogram for all message @@ -374,10 +384,10 @@ system.ruby.outstanding_req_hist_seqr::total 3295 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 12.883728 -system.ruby.latency_hist_seqr::gmean 2.062291 -system.ruby.latency_hist_seqr::stdev 28.863704 -system.ruby.latency_hist_seqr | 2856 86.70% 86.70% | 432 13.11% 99.82% | 1 0.03% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 13.772010 +system.ruby.latency_hist_seqr::gmean 2.084389 +system.ruby.latency_hist_seqr::stdev 31.264017 +system.ruby.latency_hist_seqr | 2856 86.70% 86.70% | 431 13.08% 99.79% | 1 0.03% 99.82% | 0 0.00% 99.82% | 2 0.06% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 3294 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -389,12 +399,12 @@ system.ruby.hit_latency_hist_seqr::total 2722 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 572 -system.ruby.miss_latency_hist_seqr::mean 69.435315 -system.ruby.miss_latency_hist_seqr::gmean 64.604000 -system.ruby.miss_latency_hist_seqr::stdev 30.458568 -system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 432 75.52% 98.95% | 1 0.17% 99.13% | 0 0.00% 99.13% | 1 0.17% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 74.550699 +system.ruby.miss_latency_hist_seqr::gmean 68.693513 +system.ruby.miss_latency_hist_seqr::stdev 34.041428 +system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 431 75.35% 98.78% | 1 0.17% 98.95% | 0 0.00% 98.95% | 2 0.35% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 572 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -410,15 +420,15 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 4.350250 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 4.088658 system.ruby.network.routers0.msg_count.Control::0 572 system.ruby.network.routers0.msg_count.Request_Control::2 431 system.ruby.network.routers0.msg_count.Response_Data::1 572 @@ -435,8 +445,8 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 2176 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 8.380163 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.876241 system.ruby.network.routers1.msg_count.Control::0 1119 system.ruby.network.routers1.msg_count.Request_Control::2 431 system.ruby.network.routers1.msg_count.Response_Data::1 1222 @@ -453,16 +463,16 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 2176 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 4.029913 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 3.787583 system.ruby.network.routers2.msg_count.Control::0 547 system.ruby.network.routers2.msg_count.Response_Data::1 650 system.ruby.network.routers2.msg_count.Response_Control::1 975 system.ruby.network.routers2.msg_bytes.Control::0 4376 system.ruby.network.routers2.msg_bytes.Response_Data::1 46800 system.ruby.network.routers2.msg_bytes.Response_Control::1 7800 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 5.586775 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 5.250827 system.ruby.network.routers3.msg_count.Control::0 1119 system.ruby.network.routers3.msg_count.Request_Control::2 431 system.ruby.network.routers3.msg_count.Response_Data::1 1222 @@ -479,7 +489,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 2176 system.ruby.network.routers3.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers3.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 632 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 3357 system.ruby.network.msg_count.Request_Control 1293 system.ruby.network.msg_count.Response_Data 3666 @@ -492,15 +502,15 @@ system.ruby.network.msg_byte.Response_Data 263952 system.ruby.network.msg_byte.Response_Control 41760 system.ruby.network.msg_byte.Writeback_Data 23112 system.ruby.network.msg_byte.Writeback_Control 1896 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.235104 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 5.860170 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 124 system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 3448 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 41184 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 992 -system.ruby.network.routers0.throttle1.link_utilization 2.465397 +system.ruby.network.routers0.throttle1.link_utilization 2.317146 system.ruby.network.routers0.throttle1.msg_count.Control::0 572 system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 369 system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 272 @@ -513,7 +523,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 217 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.throttle0.link_utilization 8.437015 +system.ruby.network.routers1.throttle0.link_utilization 7.929674 system.ruby.network.routers1.throttle0.msg_count.Control::0 572 system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 547 system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 908 @@ -528,7 +538,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 217 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.throttle1.link_utilization 8.323311 +system.ruby.network.routers1.throttle1.link_utilization 7.822808 system.ruby.network.routers1.throttle1.msg_count.Control::0 547 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 431 system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 675 @@ -537,26 +547,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4376 system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 3448 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 48600 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 4480 -system.ruby.network.routers2.throttle0.link_utilization 2.088208 +system.ruby.network.routers2.throttle0.link_utilization 1.962638 system.ruby.network.routers2.throttle0.msg_count.Control::0 547 system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 103 system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 436 system.ruby.network.routers2.throttle0.msg_bytes.Control::0 4376 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 7416 system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 3488 -system.ruby.network.routers2.throttle1.link_utilization 5.971618 +system.ruby.network.routers2.throttle1.link_utilization 5.612528 system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 547 system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 539 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 39384 system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 4312 -system.ruby.network.routers3.throttle0.link_utilization 6.235104 +system.ruby.network.routers3.throttle0.link_utilization 5.860170 system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 431 system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 572 system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 124 system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 3448 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 41184 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 992 -system.ruby.network.routers3.throttle1.link_utilization 8.437015 +system.ruby.network.routers3.throttle1.link_utilization 7.929674 system.ruby.network.routers3.throttle1.msg_count.Control::0 572 system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 547 system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 908 @@ -571,7 +581,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 217 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers3.throttle2.link_utilization 2.088208 +system.ruby.network.routers3.throttle2.link_utilization 1.962638 system.ruby.network.routers3.throttle2.msg_count.Control::0 547 system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 103 system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 436 @@ -597,13 +607,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 431 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 431 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 431 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 31.356627 -system.ruby.LD.latency_hist_seqr::gmean 7.342788 -system.ruby.LD.latency_hist_seqr::stdev 35.995277 -system.ruby.LD.latency_hist_seqr | 223 53.73% 53.73% | 75 18.07% 71.81% | 106 25.54% 97.35% | 10 2.41% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% +system.ruby.LD.latency_hist_seqr::mean 33.824096 +system.ruby.LD.latency_hist_seqr::gmean 7.531942 +system.ruby.LD.latency_hist_seqr::stdev 41.807535 +system.ruby.LD.latency_hist_seqr | 298 71.81% 71.81% | 115 27.71% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 415 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -612,21 +622,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 211 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 211 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 204 -system.ruby.LD.miss_latency_hist_seqr::mean 62.754902 -system.ruby.LD.miss_latency_hist_seqr::gmean 57.734169 -system.ruby.LD.miss_latency_hist_seqr::stdev 26.340677 -system.ruby.LD.miss_latency_hist_seqr | 12 5.88% 5.88% | 75 36.76% 42.65% | 106 51.96% 94.61% | 10 4.90% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 67.774510 +system.ruby.LD.miss_latency_hist_seqr::gmean 60.800044 +system.ruby.LD.miss_latency_hist_seqr::stdev 35.866860 +system.ruby.LD.miss_latency_hist_seqr | 87 42.65% 42.65% | 115 56.37% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 2 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 204 -system.ruby.ST.latency_hist_seqr::bucket_size 64 -system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::bucket_size 16 +system.ruby.ST.latency_hist_seqr::max_bucket 159 system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 14.789116 -system.ruby.ST.latency_hist_seqr::gmean 2.517478 -system.ruby.ST.latency_hist_seqr::stdev 31.573573 -system.ruby.ST.latency_hist_seqr | 264 89.80% 89.80% | 29 9.86% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 14.469388 +system.ruby.ST.latency_hist_seqr::gmean 2.523301 +system.ruby.ST.latency_hist_seqr::stdev 26.779037 +system.ruby.ST.latency_hist_seqr | 226 76.87% 76.87% | 4 1.36% 78.23% | 33 11.22% 89.46% | 1 0.34% 89.80% | 14 4.76% 94.56% | 14 4.76% 99.32% | 2 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 294 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -635,21 +645,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 226 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 226 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 system.ruby.ST.miss_latency_hist_seqr::samples 68 -system.ruby.ST.miss_latency_hist_seqr::mean 60.617647 -system.ruby.ST.miss_latency_hist_seqr::gmean 54.148546 -system.ruby.ST.miss_latency_hist_seqr::stdev 39.831747 -system.ruby.ST.miss_latency_hist_seqr | 38 55.88% 55.88% | 29 42.65% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 1 1.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 59.235294 +system.ruby.ST.miss_latency_hist_seqr::gmean 54.692111 +system.ruby.ST.miss_latency_hist_seqr::stdev 22.140068 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 4 5.88% 5.88% | 33 48.53% 54.41% | 1 1.47% 55.88% | 14 20.59% 76.47% | 14 20.59% 97.06% | 2 2.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 68 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 9.701354 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.644214 -system.ruby.IFETCH.latency_hist_seqr::stdev 25.994801 -system.ruby.IFETCH.latency_hist_seqr | 2294 88.74% 88.74% | 287 11.10% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 3 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 10.473501 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.659469 +system.ruby.IFETCH.latency_hist_seqr::stdev 28.438724 +system.ruby.IFETCH.latency_hist_seqr | 2294 88.74% 88.74% | 286 11.06% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 2585 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -661,10 +671,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 2285 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 300 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 75.976667 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 72.583942 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.223784 -system.ruby.IFETCH.miss_latency_hist_seqr | 9 3.00% 3.00% | 287 95.67% 98.67% | 1 0.33% 99.00% | 0 0.00% 99.00% | 0 0.00% 99.00% | 3 1.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 82.630000 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 78.596235 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 32.857141 +system.ruby.IFETCH.miss_latency_hist_seqr | 9 3.00% 3.00% | 286 95.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 300 system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% system.ruby.Directory_Controller.Data 103 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 2ad2eb8ea..70212c16a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,11 +270,16 @@ children=directory forwardFromDir requestToDir responseFromDir responseFromMemor buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=6 eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -320,10 +346,15 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache @@ -433,17 +464,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -466,8 +502,13 @@ L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 request_latency=2 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache @@ -566,18 +607,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -740,42 +786,216 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 +power_model=Null router_id=0 virt_nets=3 @@ -867,8 +1087,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 +power_model=Null router_id=1 virt_nets=3 @@ -960,8 +1186,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 +power_model=Null router_id=2 virt_nets=3 @@ -1053,8 +1285,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 +power_model=Null router_id=3 virt_nets=3 @@ -1187,9 +1425,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr index 1c18978fa..63982fce4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr @@ -4,9 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index 28c1f1cb8..42fdb4cc6 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:06:59 -gem5 started Jan 21 2016 14:07:35 -gem5 executing on zizzer, pid 50069 -command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory +gem5 compiled Oct 13 2016 20:30:58 +gem5 started Oct 13 2016 20:31:25 +gem5 executing on e108600-lin, pid 17791 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 41712 because target called exit() +Exiting @ tick 44230 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 1d68008a1..9bed4b569 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000042 # Number of seconds simulated -sim_ticks 41712 # Number of ticks simulated -final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000044 # Number of seconds simulated +sim_ticks 44230 # Number of ticks simulated +final_tick 44230 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 62826 # Simulator instruction rate (inst/s) -host_op_rate 62813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1016484 # Simulator tick rate (ticks/s) -host_mem_usage 457644 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 44627 # Simulator instruction rate (inst/s) +host_op_rate 44610 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 765394 # Simulator tick rate (ticks/s) +host_mem_usage 414624 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 29696 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 29696 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4992 # Number of bytes written to this memory @@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 464 # system.mem_ctrls.num_reads::total 464 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 78 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 78 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 711929421 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 711929421 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 119677791 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 119677791 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 831607211 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 831607211 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 671399503 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 671399503 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 112864572 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 112864572 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 784264074 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 784264074 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 464 # Number of read requests accepted system.mem_ctrls.writeReqs 78 # Number of write requests accepted system.mem_ctrls.readBursts 464 # Number of DRAM read bursts, including those serviced by the write queue @@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 41632 # Total gap between requests +system.mem_ctrls.totGap 44144 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 72 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 336 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 226.772547 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 284.954160 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 17 23.61% 23.61% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 17 23.61% 47.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 12 16.67% 63.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 5 6.94% 70.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 7 9.72% 80.56% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 6 8.33% 88.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2 2.78% 91.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 4.17% 95.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 3 4.17% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 72 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 75 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 308.906667 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 203.362375 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 281.413861 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 21 28.00% 28.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 20 26.67% 54.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 8 10.67% 65.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 8 10.67% 76.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6 8.00% 84.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3 4.00% 88.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 5.33% 93.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1 1.33% 94.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 4 5.33% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 75 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 248 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 248.000000 # Reads before turning the bus around for writes @@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 2393 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 9689 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 4911 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 12207 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 1920 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.23 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 12.79 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.23 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 589.18 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 24.55 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 711.93 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 119.68 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.79 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 555.64 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 23.15 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 671.40 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 112.86 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.79 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.60 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.19 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.52 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.34 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.18 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.63 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 305 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 21.61 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.43 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 78.65 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 76.81 # Average gap between requests -system.mem_ctrls.pageHitRate 74.42 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1809600 # Energy for read commands per rank (pJ) +system.mem_ctrls.avgGap 81.45 # Average gap between requests +system.mem_ctrls.pageHitRate 73.72 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 178500 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 81144 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1793568 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 24398280 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 2114400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 31112040 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 793.795989 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 3488 # Time in different power states +system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 2736456 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 72192 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 16199400 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 966144 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 25100604 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 567.501786 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 37998 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 48 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 34510 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 214200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2708160 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 26293644 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 449400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 32759652 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 835.918653 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 623 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 2516 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 4841 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 35525 # Time in different power states +system.mem_ctrls_1.actEnergy 414120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 208656 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2593248 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 3830856 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 258048 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 15964560 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 56448 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 26532768 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 599.881709 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 34371 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 532 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 37281 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 147 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 7241 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 35010 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 41712 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 41712 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 44230 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 41712 # Number of busy cycles +system.cpu.num_busy_cycles 44230 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 3295 @@ -364,13 +374,13 @@ system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 32 -system.ruby.latency_hist_seqr::max_bucket 319 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 11.663024 -system.ruby.latency_hist_seqr::gmean 1.954156 -system.ruby.latency_hist_seqr::stdev 27.142816 -system.ruby.latency_hist_seqr | 2830 85.91% 85.91% | 80 2.43% 88.34% | 359 10.90% 99.24% | 18 0.55% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 1 0.03% 99.91% | 3 0.09% 100.00% +system.ruby.latency_hist_seqr::mean 12.427444 +system.ruby.latency_hist_seqr::gmean 1.971908 +system.ruby.latency_hist_seqr::stdev 29.452789 +system.ruby.latency_hist_seqr | 2910 88.34% 88.34% | 377 11.45% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 3294 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -379,30 +389,30 @@ system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist_seqr::total 2750 -system.ruby.miss_latency_hist_seqr::bucket_size 32 -system.ruby.miss_latency_hist_seqr::max_bucket 319 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 544 -system.ruby.miss_latency_hist_seqr::mean 65.566176 -system.ruby.miss_latency_hist_seqr::gmean 57.783054 -system.ruby.miss_latency_hist_seqr::stdev 31.323348 -system.ruby.miss_latency_hist_seqr | 80 14.71% 14.71% | 80 14.71% 29.41% | 359 65.99% 95.40% | 18 3.31% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 1 0.18% 99.26% | 0 0.00% 99.26% | 1 0.18% 99.45% | 3 0.55% 100.00% +system.ruby.miss_latency_hist_seqr::mean 70.194853 +system.ruby.miss_latency_hist_seqr::gmean 61.035379 +system.ruby.miss_latency_hist_seqr::stdev 35.442152 +system.ruby.miss_latency_hist_seqr | 160 29.41% 29.41% | 377 69.30% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 3 0.55% 99.63% | 2 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 544 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 435 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 274 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 464 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 6.800201 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 6.413068 system.ruby.network.routers0.msg_count.Request_Control::0 544 system.ruby.network.routers0.msg_count.Response_Data::2 464 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 80 @@ -415,8 +425,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5760 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 10.372914 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 9.782388 system.ruby.network.routers1.msg_count.Request_Control::0 544 system.ruby.network.routers1.msg_count.Request_Control::1 464 system.ruby.network.routers1.msg_count.Response_Data::2 928 @@ -433,8 +443,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 40320 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 1248 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 8216 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.572713 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 3.369319 system.ruby.network.routers2.msg_count.Request_Control::1 464 system.ruby.network.routers2.msg_count.Response_Data::2 464 system.ruby.network.routers2.msg_count.Writeback_Data::2 78 @@ -445,8 +455,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 33408 system.ruby.network.routers2.msg_bytes.Writeback_Data::2 5616 system.ruby.network.routers2.msg_bytes.Writeback_Control::1 1248 system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 6.915276 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 6.521592 system.ruby.network.routers3.msg_count.Request_Control::0 544 system.ruby.network.routers3.msg_count.Request_Control::1 464 system.ruby.network.routers3.msg_count.Response_Data::2 928 @@ -463,7 +473,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2 40320 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 1248 system.ruby.network.routers3.msg_bytes.Unblock_Control::2 8216 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 3024 system.ruby.network.msg_count.Response_Data 2784 system.ruby.network.msg_count.ResponseL2hit_Data 240 @@ -476,15 +486,15 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 17280 system.ruby.network.msg_byte.Writeback_Data 120960 system.ruby.network.msg_byte.Writeback_Control 27840 system.ruby.network.msg_byte.Unblock_Control 24648 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.470560 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 6.102193 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 464 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 80 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 502 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 33408 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 5760 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers0.throttle1.link_utilization 7.129843 +system.ruby.network.routers0.throttle1.link_utilization 6.723943 system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 544 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 482 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 502 @@ -493,7 +503,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 4352 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 4016 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.throttle0.link_utilization 12.229095 +system.ruby.network.routers1.throttle0.link_utilization 11.532896 system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 544 system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 464 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 482 @@ -506,7 +516,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 4016 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.throttle1.link_utilization 8.516734 +system.ruby.network.routers1.throttle1.link_utilization 8.031879 system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 464 system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 464 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 80 @@ -521,7 +531,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 5616 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 4016 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers2.throttle0.link_utilization 2.046174 +system.ruby.network.routers2.throttle0.link_utilization 1.929686 system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 464 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 78 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 78 @@ -530,19 +540,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 3712 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 5616 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers2.throttle1.link_utilization 5.099252 +system.ruby.network.routers2.throttle1.link_utilization 4.808953 system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 464 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 78 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 33408 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers3.throttle0.link_utilization 6.470560 +system.ruby.network.routers3.throttle0.link_utilization 6.102193 system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 464 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 80 system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 502 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 33408 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 5760 system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers3.throttle1.link_utilization 12.229095 +system.ruby.network.routers3.throttle1.link_utilization 11.532896 system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 544 system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 464 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 482 @@ -555,7 +565,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 4016 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers3.throttle2.link_utilization 2.046174 +system.ruby.network.routers3.throttle2.link_utilization 1.929686 system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 464 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 78 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 78 @@ -564,13 +574,13 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 3712 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 5616 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 3704 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 25.657831 -system.ruby.LD.latency_hist_seqr::gmean 5.487426 -system.ruby.LD.latency_hist_seqr::stdev 34.035908 -system.ruby.LD.latency_hist_seqr | 275 66.27% 66.27% | 45 10.84% 77.11% | 85 20.48% 97.59% | 8 1.93% 99.52% | 1 0.24% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 27.790361 +system.ruby.LD.latency_hist_seqr::gmean 5.600782 +system.ruby.LD.latency_hist_seqr::stdev 40.269706 +system.ruby.LD.latency_hist_seqr | 320 77.11% 77.11% | 92 22.17% 99.28% | 1 0.24% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 415 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -579,21 +589,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 233 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 182 -system.ruby.LD.miss_latency_hist_seqr::mean 57.225275 -system.ruby.LD.miss_latency_hist_seqr::gmean 48.520263 -system.ruby.LD.miss_latency_hist_seqr::stdev 29.410954 -system.ruby.LD.miss_latency_hist_seqr | 42 23.08% 23.08% | 45 24.73% 47.80% | 85 46.70% 94.51% | 8 4.40% 98.90% | 1 0.55% 99.45% | 0 0.00% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 62.087912 +system.ruby.LD.miss_latency_hist_seqr::gmean 50.836003 +system.ruby.LD.miss_latency_hist_seqr::stdev 40.030554 +system.ruby.LD.miss_latency_hist_seqr | 87 47.80% 47.80% | 92 50.55% 98.35% | 1 0.55% 98.90% | 0 0.00% 98.90% | 1 0.55% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 182 system.ruby.ST.latency_hist_seqr::bucket_size 16 system.ruby.ST.latency_hist_seqr::max_bucket 159 system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 18.809524 -system.ruby.ST.latency_hist_seqr::gmean 3.456048 -system.ruby.ST.latency_hist_seqr::stdev 29.072895 -system.ruby.ST.latency_hist_seqr | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 38 12.93% 97.62% | 6 2.04% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 19.755102 +system.ruby.ST.latency_hist_seqr::gmean 3.497030 +system.ruby.ST.latency_hist_seqr::stdev 31.010753 +system.ruby.ST.latency_hist_seqr | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 0 0.00% 84.69% | 44 14.97% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 294 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -605,18 +615,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 202 system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 system.ruby.ST.miss_latency_hist_seqr::samples 92 -system.ruby.ST.miss_latency_hist_seqr::mean 57.913043 -system.ruby.ST.miss_latency_hist_seqr::gmean 52.615480 -system.ruby.ST.miss_latency_hist_seqr::stdev 21.714254 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 38 41.30% 92.39% | 6 6.52% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 60.934783 +system.ruby.ST.miss_latency_hist_seqr::gmean 54.635401 +system.ruby.ST.miss_latency_hist_seqr::stdev 24.518127 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 0 0.00% 51.09% | 44 47.83% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 92 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 8.603482 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.551701 -system.ruby.IFETCH.latency_hist_seqr::stdev 24.714457 -system.ruby.IFETCH.latency_hist_seqr | 2341 90.56% 90.56% | 0 0.00% 90.56% | 230 8.90% 99.46% | 9 0.35% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.04% 99.88% | 3 0.12% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 9.127660 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.562445 +system.ruby.IFETCH.latency_hist_seqr::stdev 26.109704 +system.ruby.IFETCH.latency_hist_seqr | 2341 90.56% 90.56% | 240 9.28% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 2585 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -625,13 +635,13 @@ system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist_seqr::total 2315 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 270 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.796296 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.113694 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.225253 -system.ruby.IFETCH.miss_latency_hist_seqr | 26 9.63% 9.63% | 0 0.00% 9.63% | 230 85.19% 94.81% | 9 3.33% 98.15% | 1 0.37% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 1 0.37% 98.89% | 3 1.11% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.814815 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 71.697206 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.251813 +system.ruby.IFETCH.miss_latency_hist_seqr | 26 9.63% 9.63% | 240 88.89% 98.52% | 1 0.37% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 270 system.ruby.Directory_Controller.GETX 80 0.00% 0.00% system.ruby.Directory_Controller.GETS 384 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index c78531ccf..cf25b799b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persiste buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=5 distributed_persistent=true @@ -258,8 +280,12 @@ eventq_index=0 fixed_timeout_latency=100 l2_select_num_bits=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir persistentToDir=system.ruby.dir_cntrl0.persistentToDir +power_model=Null recycle_latency=10 reissue_wakeup_latency=10 requestFromDir=system.ruby.dir_cntrl0.requestFromDir @@ -361,6 +387,7 @@ N_tokens=2 buffer_size=0 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED dynamic_timeout_enabled=true eventq_index=0 fixed_timeout_latency=300 @@ -370,8 +397,12 @@ l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue no_mig_atomic=true number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache +power_model=Null recycle_latency=10 reissue_wakeup_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache @@ -497,17 +528,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -524,12 +560,17 @@ N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 filtering_enabled=true l2_request_latency=5 l2_response_latency=5 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache +power_model=Null recycle_latency=10 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache @@ -626,18 +667,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -926,42 +972,342 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers40] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers41] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers42] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers43] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers44] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers45] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers46] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers47] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers48] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers49] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers50] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers51] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers52] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers53] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers54] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers55] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers56] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers57] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers58] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers59] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers60] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers61] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers62] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers63] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers64] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers65] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers66] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers67] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers68] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers69] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers70] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers71] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 system.ruby.network.routers0.port_buffers18 system.ruby.network.routers0.port_buffers19 system.ruby.network.routers0.port_buffers20 system.ruby.network.routers0.port_buffers21 system.ruby.network.routers0.port_buffers22 system.ruby.network.routers0.port_buffers23 +power_model=Null router_id=0 virt_nets=6 @@ -1137,8 +1483,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 system.ruby.network.routers1.port_buffers18 system.ruby.network.routers1.port_buffers19 system.ruby.network.routers1.port_buffers20 system.ruby.network.routers1.port_buffers21 system.ruby.network.routers1.port_buffers22 system.ruby.network.routers1.port_buffers23 +power_model=Null router_id=1 virt_nets=6 @@ -1314,8 +1666,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 +power_model=Null router_id=2 virt_nets=6 @@ -1491,8 +1849,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35 +power_model=Null router_id=3 virt_nets=6 @@ -1751,9 +2115,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr index 1c18978fa..63982fce4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr @@ -4,9 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index 9a1a80ba2..57e88573f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:12:23 -gem5 started Jan 21 2016 14:13:00 -gem5 executing on zizzer, pid 55410 -command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token +gem5 compiled Oct 13 2016 20:33:48 +gem5 started Oct 13 2016 20:34:16 +gem5 executing on e108600-lin, pid 27527 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 40527 because target called exit() +Exiting @ tick 42756 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 20325d4b9..0254766b0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000041 # Number of seconds simulated -sim_ticks 40527 # Number of ticks simulated -final_tick 40527 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000043 # Number of seconds simulated +sim_ticks 42756 # Number of ticks simulated +final_tick 42756 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 89328 # Simulator instruction rate (inst/s) -host_op_rate 89293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1403832 # Simulator tick rate (ticks/s) -host_mem_usage 454496 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 50628 # Simulator instruction rate (inst/s) +host_op_rate 50604 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 839232 # Simulator tick rate (ticks/s) +host_mem_usage 411504 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28672 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 28672 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5376 # Number of bytes written to this memory @@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 448 # system.mem_ctrls.num_reads::total 448 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 84 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 84 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 707478965 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 707478965 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 132652306 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 132652306 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 840131271 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 840131271 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 670595940 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 670595940 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 125736739 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 125736739 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 796332678 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 796332678 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 448 # Number of read requests accepted system.mem_ctrls.writeReqs 84 # Number of write requests accepted system.mem_ctrls.readBursts 448 # Number of DRAM read bursts, including those serviced by the write queue @@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 40452 # Total gap between requests +system.mem_ctrls.totGap 42675 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 73 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 334.027397 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 221.884458 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 291.386817 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 19 26.03% 26.03% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 15 20.55% 46.58% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 13 17.81% 64.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 6 8.22% 72.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 7 9.59% 82.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5 6.85% 89.04% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1 1.37% 90.41% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 2 2.74% 93.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 73 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 72 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 326.222222 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 214.888456 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 283.209683 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20 27.78% 27.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 16 22.22% 50.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 10 13.89% 63.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 5 6.94% 70.83% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 9 12.50% 83.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 2 2.78% 86.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 8.33% 94.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 2.78% 97.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 2 2.78% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 72 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 245 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 245.000000 # Reads before turning the bus around for writes @@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 2601 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 9726 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 4832 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 11957 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.94 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 12.89 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.94 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 592.20 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 25.27 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 707.48 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 132.65 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.89 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 561.32 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 23.95 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 670.60 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 125.74 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.82 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.20 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.57 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.39 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.19 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.86 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 297 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 21.84 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 296 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.20 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 78.93 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 76.04 # Average gap between requests -system.mem_ctrls.pageHitRate 74.11 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1896960 # Energy for read commands per rank (pJ) +system.mem_ctrls.avgGap 80.22 # Average gap between requests +system.mem_ctrls.pageHitRate 73.87 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 178500 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 81144 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1816416 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 25074756 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 1518600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 31280076 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 798.164736 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 2492 # Time in different power states +system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 2612424 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 73344 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 15837336 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 808320 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 24480684 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 572.567219 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 36801 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 51 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 35499 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 393120 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 218400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2658240 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 26158212 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 568200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 32704860 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 834.520541 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 821 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 2105 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 4569 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 34731 # Time in different power states +system.mem_ctrls_1.actEnergy 392700 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 197064 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2467584 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 3542208 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 293376 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 15524520 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 68736 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 25693020 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 600.921976 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 33391 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 512 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 37083 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 179 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 6720 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 34045 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 40527 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40527 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 42756 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 42756 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 40527 # Number of busy cycles +system.cpu.num_busy_cycles 42756 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 3295 @@ -367,44 +377,44 @@ system.ruby.outstanding_req_hist_seqr::total 3295 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 11.303279 -system.ruby.latency_hist_seqr::gmean 1.905847 -system.ruby.latency_hist_seqr::stdev 27.108694 -system.ruby.latency_hist_seqr | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 11.979964 +system.ruby.latency_hist_seqr::gmean 1.922311 +system.ruby.latency_hist_seqr::stdev 28.863148 +system.ruby.latency_hist_seqr | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 3294 system.ruby.hit_latency_hist_seqr::bucket_size 4 system.ruby.hit_latency_hist_seqr::max_bucket 39 system.ruby.hit_latency_hist_seqr::samples 2846 -system.ruby.hit_latency_hist_seqr::mean 1.554814 -system.ruby.hit_latency_hist_seqr::gmean 1.080771 -system.ruby.hit_latency_hist_seqr::stdev 3.499483 -system.ruby.hit_latency_hist_seqr | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 9 0.32% 97.86% | 61 2.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::mean 1.555868 +system.ruby.hit_latency_hist_seqr::gmean 1.080822 +system.ruby.hit_latency_hist_seqr::stdev 3.505788 +system.ruby.hit_latency_hist_seqr | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 8 0.28% 97.82% | 62 2.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist_seqr::total 2846 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 448 -system.ruby.miss_latency_hist_seqr::mean 73.232143 -system.ruby.miss_latency_hist_seqr::gmean 69.999992 -system.ruby.miss_latency_hist_seqr::stdev 29.782878 -system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 78.200893 +system.ruby.miss_latency_hist_seqr::gmean 74.547837 +system.ruby.miss_latency_hist_seqr::stdev 31.179064 +system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 0 0.00% 99.11% | 4 0.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 448 system.ruby.Directory.incomplete_times_seqr 447 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 248 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 5.992918 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 5.680489 system.ruby.network.routers0.msg_count.Request_Control::1 518 system.ruby.network.routers0.msg_count.Response_Data::4 448 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 70 @@ -417,8 +427,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 128 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 4.472327 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 4.239171 system.ruby.network.routers1.msg_count.Request_Control::1 518 system.ruby.network.routers1.msg_count.Request_Control::2 454 system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 70 @@ -433,8 +443,8 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.463740 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 3.283165 system.ruby.network.routers2.msg_count.Request_Control::2 454 system.ruby.network.routers2.msg_count.Response_Data::4 448 system.ruby.network.routers2.msg_count.Writeback_Data::4 84 @@ -445,8 +455,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 32256 system.ruby.network.routers2.msg_bytes.Writeback_Data::4 6048 system.ruby.network.routers2.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers2.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 4.642995 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 4.400942 system.ruby.network.routers3.msg_count.Request_Control::1 518 system.ruby.network.routers3.msg_count.Request_Control::2 454 system.ruby.network.routers3.msg_count.Response_Data::4 448 @@ -463,7 +473,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::4 8 system.ruby.network.routers3.msg_bytes.Writeback_Data::4 42192 system.ruby.network.routers3.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers3.msg_bytes.Persistent_Control::3 128 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 2916 system.ruby.network.msg_count.Response_Data 1344 system.ruby.network.msg_count.ResponseL2hit_Data 210 @@ -478,8 +488,8 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 126576 system.ruby.network.msg_byte.Writeback_Control 8760 system.ruby.network.msg_byte.Persistent_Control 384 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 5.762825 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 5.462391 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1 @@ -488,21 +498,21 @@ system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 32256 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers0.throttle1.link_utilization 6.223012 +system.ruby.network.routers0.throttle1.link_utilization 5.898587 system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 518 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 502 system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 8 system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 4144 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers1.throttle0.link_utilization 6.223012 +system.ruby.network.routers1.throttle0.link_utilization 5.898587 system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 518 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 502 system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 8 system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 4144 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers1.throttle1.link_utilization 2.721642 +system.ruby.network.routers1.throttle1.link_utilization 2.579755 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 454 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 70 system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 @@ -513,7 +523,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 5 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 6048 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers2.throttle0.link_utilization 1.953019 +system.ruby.network.routers2.throttle0.link_utilization 1.851202 system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 454 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 84 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 365 @@ -522,24 +532,24 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 3632 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 6048 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers2.throttle1.link_utilization 4.974461 +system.ruby.network.routers2.throttle1.link_utilization 4.715128 system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 448 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers3.throttle0.link_utilization 5.752955 +system.ruby.network.routers3.throttle0.link_utilization 5.453036 system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 70 system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 32256 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.throttle1.link_utilization 6.223012 +system.ruby.network.routers3.throttle1.link_utilization 5.898587 system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 518 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 502 system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 8 system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 4144 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers3.throttle2.link_utilization 1.953019 +system.ruby.network.routers3.throttle2.link_utilization 1.851202 system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 454 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 84 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 365 @@ -548,36 +558,36 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 3632 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 6048 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 64 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 16 +system.ruby.LD.latency_hist_seqr::max_bucket 159 system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 27.009639 -system.ruby.LD.latency_hist_seqr::gmean 5.745092 -system.ruby.LD.latency_hist_seqr::stdev 35.695436 -system.ruby.LD.latency_hist_seqr | 266 64.10% 64.10% | 50 12.05% 76.14% | 86 20.72% 96.87% | 10 2.41% 99.28% | 2 0.48% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% +system.ruby.LD.latency_hist_seqr::mean 27.997590 +system.ruby.LD.latency_hist_seqr::gmean 5.837138 +system.ruby.LD.latency_hist_seqr::stdev 35.585408 +system.ruby.LD.latency_hist_seqr | 233 56.14% 56.14% | 33 7.95% 64.10% | 48 11.57% 75.66% | 2 0.48% 76.14% | 68 16.39% 92.53% | 18 4.34% 96.87% | 10 2.41% 99.28% | 1 0.24% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% system.ruby.LD.latency_hist_seqr::total 415 system.ruby.LD.hit_latency_hist_seqr::bucket_size 4 system.ruby.LD.hit_latency_hist_seqr::max_bucket 39 system.ruby.LD.hit_latency_hist_seqr::samples 266 -system.ruby.LD.hit_latency_hist_seqr::mean 3.834586 -system.ruby.LD.hit_latency_hist_seqr::gmean 1.482071 -system.ruby.LD.hit_latency_hist_seqr::stdev 7.549265 -system.ruby.LD.hit_latency_hist_seqr | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 2 0.75% 88.35% | 31 11.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::mean 3.845865 +system.ruby.LD.hit_latency_hist_seqr::gmean 1.482816 +system.ruby.LD.hit_latency_hist_seqr::stdev 7.577195 +system.ruby.LD.hit_latency_hist_seqr | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 1 0.38% 87.97% | 32 12.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 266 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 16 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 159 system.ruby.LD.miss_latency_hist_seqr::samples 149 -system.ruby.LD.miss_latency_hist_seqr::mean 68.382550 -system.ruby.LD.miss_latency_hist_seqr::gmean 64.532565 -system.ruby.LD.miss_latency_hist_seqr::stdev 27.813471 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 71.114094 +system.ruby.LD.miss_latency_hist_seqr::gmean 67.393219 +system.ruby.LD.miss_latency_hist_seqr::stdev 22.792700 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 68 45.64% 79.19% | 18 12.08% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 0 0.00% 98.66% | 2 1.34% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 149 system.ruby.ST.latency_hist_seqr::bucket_size 16 system.ruby.ST.latency_hist_seqr::max_bucket 159 system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 12.595238 -system.ruby.ST.latency_hist_seqr::gmean 2.381363 -system.ruby.ST.latency_hist_seqr::stdev 23.818056 +system.ruby.ST.latency_hist_seqr::mean 13.153061 +system.ruby.ST.latency_hist_seqr::gmean 2.398410 +system.ruby.ST.latency_hist_seqr::stdev 25.296880 system.ruby.ST.latency_hist_seqr | 228 77.55% 77.55% | 14 4.76% 82.31% | 20 6.80% 89.12% | 3 1.02% 90.14% | 23 7.82% 97.96% | 6 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 294 system.ruby.ST.hit_latency_hist_seqr::bucket_size 4 @@ -591,18 +601,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 242 system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 system.ruby.ST.miss_latency_hist_seqr::samples 52 -system.ruby.ST.miss_latency_hist_seqr::mean 60.865385 -system.ruby.ST.miss_latency_hist_seqr::gmean 58.719474 -system.ruby.ST.miss_latency_hist_seqr::stdev 16.012286 +system.ruby.ST.miss_latency_hist_seqr::mean 64.019231 +system.ruby.ST.miss_latency_hist_seqr::gmean 61.135942 +system.ruby.ST.miss_latency_hist_seqr::stdev 18.838311 system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 52 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 8.634816 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.556513 -system.ruby.IFETCH.latency_hist_seqr::stdev 24.922226 -system.ruby.IFETCH.latency_hist_seqr | 2338 90.44% 90.44% | 243 9.40% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 9.275048 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.568384 +system.ruby.IFETCH.latency_hist_seqr::stdev 27.157574 +system.ruby.IFETCH.latency_hist_seqr | 2338 90.44% 90.44% | 242 9.36% 99.81% | 0 0.00% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 4 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 2585 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 4 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 39 @@ -615,10 +625,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 2338 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 247 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.761134 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.290474 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.873920 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 85.461538 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 82.604305 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.418255 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 0 0.00% 98.38% | 4 1.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 247 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 @@ -630,18 +640,18 @@ system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 2776 system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 4 system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 39 system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 70 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.557143 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.524270 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.199465 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 12.86% 12.86% | 61 87.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.600000 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.569187 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.159710 +system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 11.43% 11.43% | 62 88.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 70 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 448 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 73.232143 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 69.999992 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 29.782878 -system.ruby.Directory.miss_mach_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 78.200893 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 74.547837 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.179064 +system.ruby.Directory.miss_mach_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 0 0.00% 99.11% | 4 0.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 448 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -679,18 +689,18 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 233 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 33 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.848485 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.840140 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.618527 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 6.06% 6.06% | 31 93.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.939394 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.936802 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.348155 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 3.03% 3.03% | 32 96.97% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 33 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 149 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 68.382550 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 64.532565 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.813471 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 71.114094 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 67.393219 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 22.792700 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 68 45.64% 79.19% | 18 12.08% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 0 0.00% 98.66% | 2 1.34% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 149 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 @@ -710,9 +720,9 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 14 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 52 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 60.865385 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 58.719474 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 16.012286 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 64.019231 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 61.135942 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 18.838311 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 52 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 @@ -732,10 +742,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 23 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 247 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 78.761134 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.290474 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.873920 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 85.461538 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 82.604305 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.418255 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 0 0.00% 98.38% | 4 1.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 247 system.ruby.Directory_Controller.GETX 61 0.00% 0.00% system.ruby.Directory_Controller.GETS 398 0.00% 0.00% @@ -752,6 +762,7 @@ system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% @@ -760,9 +771,9 @@ system.ruby.Directory_Controller.L.Unlockdown 4 0.00% 0.00% system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 4 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 4 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 444 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 445 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -781,7 +792,7 @@ system.ruby.L1Cache_Controller.S.Ifetch 158 0.00% 0.00% system.ruby.L1Cache_Controller.S.Store 8 0.00% 0.00% system.ruby.L1Cache_Controller.S.L1_Replacement 48 0.00% 0.00% system.ruby.L1Cache_Controller.M.Load 66 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 1099 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 1098 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 29 0.00% 0.00% system.ruby.L1Cache_Controller.M.L1_Replacement 358 0.00% 0.00% system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 4 0.00% 0.00% @@ -789,7 +800,7 @@ system.ruby.L1Cache_Controller.MM.Load 96 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Store 103 0.00% 0.00% system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Load 36 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Ifetch 1058 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Ifetch 1059 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Store 3 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.L1_Replacement 1 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 392 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 18d7c2ab4..8207d6ac7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir @@ -257,6 +279,10 @@ forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir from_memory_controller_latency=2 full_bit_dir_enabled=false number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeFilter=system.ruby.dir_cntrl0.probeFilter probe_filter_enabled=false recycle_latency=10 @@ -384,6 +410,7 @@ buffer_size=0 cache_response_latency=10 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 @@ -391,6 +418,10 @@ l2_cache_hit_latency=10 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue no_mig_atomic=true number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -522,17 +553,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -560,18 +596,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -766,32 +807,234 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers40] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers41] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers42] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers43] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers44] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers45] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers46] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers47] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 +power_model=Null router_id=0 virt_nets=6 @@ -925,8 +1168,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 +power_model=Null router_id=1 virt_nets=6 @@ -1060,8 +1309,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 +power_model=Null router_id=2 virt_nets=6 @@ -1236,9 +1491,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr index 1c18978fa..63982fce4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr @@ -4,9 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 2cf0cc885..35b481dda 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:56:08 -gem5 started Jan 21 2016 13:56:42 -gem5 executing on zizzer, pid 39363 -command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer +gem5 compiled Oct 13 2016 20:24:36 +gem5 started Oct 13 2016 20:24:58 +gem5 executing on e108600-lin, pid 38874 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 32936 because target called exit() +Exiting @ tick 35056 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 71e93d920..4d9201d35 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32936 # Number of ticks simulated -final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000035 # Number of seconds simulated +sim_ticks 35056 # Number of ticks simulated +final_tick 35056 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 91605 # Simulator instruction rate (inst/s) -host_op_rate 91573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1170024 # Simulator tick rate (ticks/s) -host_mem_usage 453424 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 50934 # Simulator instruction rate (inst/s) +host_op_rate 50910 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 692254 # Simulator tick rate (ticks/s) +host_mem_usage 411180 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28224 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 28224 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5184 # Number of bytes written to this memory @@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 441 # system.mem_ctrls.num_reads::total 441 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 81 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 81 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 856934661 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 856934661 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 157396162 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 157396162 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1014330823 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1014330823 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 805111821 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 805111821 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 147877681 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 147877681 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 952989503 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 952989503 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 441 # Number of read requests accepted system.mem_ctrls.writeReqs 81 # Number of write requests accepted system.mem_ctrls.readBursts 441 # Number of DRAM read bursts, including those serviced by the write queue @@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 32872 # Total gap between requests +system.mem_ctrls.totGap 34986 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -186,17 +186,17 @@ system.mem_ctrls.wrQLenPdf::61 0 # Wh system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 67 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 358.208955 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 229.774303 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 311.560906 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 18 26.87% 26.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 13 19.40% 46.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 8 11.94% 58.21% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 7 10.45% 68.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 5 7.46% 76.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 6 8.96% 85.07% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2 2.99% 88.06% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 5.97% 94.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 356.298507 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 230.035457 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 306.978482 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 19 28.36% 28.36% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 11 16.42% 44.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 10 14.93% 59.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 7 10.45% 70.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6 8.96% 79.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 4 5.97% 85.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 4.48% 89.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 4.48% 94.03% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 4 5.97% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 67 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes @@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 2381 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 9506 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 4501 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 11626 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.35 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 12.00 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.35 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 728.69 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 31.09 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 856.93 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 157.40 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.00 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 684.62 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 29.21 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 805.11 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 147.88 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.94 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 5.69 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.24 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 5.58 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.35 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.23 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.54 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 21.49 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 80.53 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 62.97 # Average gap between requests +system.mem_ctrls.avgGap 67.02 # Average gap between requests system.mem_ctrls.pageHitRate 75.30 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 84000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1859520 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.actEnergy 164220 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 77280 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1839264 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 21272400 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 182400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 25583760 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 814.665648 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 206 # Time in different power states +system.mem_ctrls_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 2689032 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 56064 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 13011960 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 183552 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 20479932 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 584.206184 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 29013 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 34 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 30172 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 355320 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 197400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2620800 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 20904408 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 505200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 26783256 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 852.861292 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1046 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 478 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 4969 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 28535 # Time in different power states +system.mem_ctrls_1.actEnergy 364140 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 181608 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2444736 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 3405408 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 211968 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 12011952 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 266496 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 21478500 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 612.691123 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 26306 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 440 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 29634 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 694 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 6540 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 26342 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 32936 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 32936 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 35056 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 35056 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 32936 # Number of busy cycles +system.cpu.num_busy_cycles 35056 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 3295 @@ -364,13 +374,13 @@ system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::bucket_size 32 +system.ruby.latency_hist_seqr::max_bucket 319 system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 8.998786 -system.ruby.latency_hist_seqr::gmean 1.800750 -system.ruby.latency_hist_seqr::stdev 22.386902 -system.ruby.latency_hist_seqr | 3204 97.27% 97.27% | 86 2.61% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.06% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 9.642380 +system.ruby.latency_hist_seqr::gmean 1.819734 +system.ruby.latency_hist_seqr::stdev 23.663336 +system.ruby.latency_hist_seqr | 2910 88.34% 88.34% | 293 8.89% 97.24% | 85 2.58% 99.82% | 2 0.06% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 4 0.12% 100.00% system.ruby.latency_hist_seqr::total 3294 system.ruby.hit_latency_hist_seqr::bucket_size 2 system.ruby.hit_latency_hist_seqr::max_bucket 19 @@ -380,19 +390,19 @@ system.ruby.hit_latency_hist_seqr::gmean 1.059708 system.ruby.hit_latency_hist_seqr::stdev 1.536503 system.ruby.hit_latency_hist_seqr | 2784 97.58% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 69 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist_seqr::total 2853 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::bucket_size 32 +system.ruby.miss_latency_hist_seqr::max_bucket 319 system.ruby.miss_latency_hist_seqr::samples 441 -system.ruby.miss_latency_hist_seqr::mean 59.181406 -system.ruby.miss_latency_hist_seqr::gmean 55.608631 -system.ruby.miss_latency_hist_seqr::stdev 28.659343 -system.ruby.miss_latency_hist_seqr | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 63.988662 +system.ruby.miss_latency_hist_seqr::gmean 60.139666 +system.ruby.miss_latency_hist_seqr::stdev 27.525151 +system.ruby.miss_latency_hist_seqr | 57 12.93% 12.93% | 293 66.44% 79.37% | 85 19.27% 98.64% | 2 0.45% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 4 0.91% 100.00% system.ruby.miss_latency_hist_seqr::total 441 system.ruby.Directory.incomplete_times_seqr 440 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -402,12 +412,12 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 5.141031 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 4.830129 system.ruby.network.routers0.msg_count.Request_Control::2 441 system.ruby.network.routers0.msg_count.Response_Data::4 441 system.ruby.network.routers0.msg_count.Writeback_Data::5 81 @@ -422,8 +432,8 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 5.141031 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 4.830129 system.ruby.network.routers1.msg_count.Request_Control::2 441 system.ruby.network.routers1.msg_count.Response_Data::4 441 system.ruby.network.routers1.msg_count.Writeback_Data::5 81 @@ -438,8 +448,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 5.141031 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 4.830129 system.ruby.network.routers2.msg_count.Request_Control::2 441 system.ruby.network.routers2.msg_count.Response_Data::4 441 system.ruby.network.routers2.msg_count.Writeback_Data::5 81 @@ -454,7 +464,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 1323 system.ruby.network.msg_count.Response_Data 1323 system.ruby.network.msg_count.Writeback_Data 243 @@ -465,13 +475,13 @@ system.ruby.network.msg_byte.Response_Data 95256 system.ruby.network.msg_byte.Writeback_Data 17496 system.ruby.network.msg_byte.Writeback_Control 28656 system.ruby.network.msg_byte.Unblock_Control 10560 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.670513 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 6.267115 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31752 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers0.throttle1.link_utilization 3.611550 +system.ruby.network.routers0.throttle1.link_utilization 3.393142 system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 441 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 81 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 425 @@ -482,7 +492,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 5832 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.throttle0.link_utilization 3.611550 +system.ruby.network.routers1.throttle0.link_utilization 3.393142 system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 441 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 81 system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 425 @@ -493,17 +503,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 5832 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.throttle1.link_utilization 6.670513 +system.ruby.network.routers1.throttle1.link_utilization 6.267115 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 441 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 425 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31752 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers2.throttle0.link_utilization 6.670513 +system.ruby.network.routers2.throttle0.link_utilization 6.267115 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 425 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31752 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers2.throttle1.link_utilization 3.611550 +system.ruby.network.routers2.throttle1.link_utilization 3.393142 system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 441 system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 81 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 425 @@ -517,10 +527,10 @@ system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 3520 system.ruby.LD.latency_hist_seqr::bucket_size 16 system.ruby.LD.latency_hist_seqr::max_bucket 159 system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 19.850602 -system.ruby.LD.latency_hist_seqr::gmean 4.833066 -system.ruby.LD.latency_hist_seqr::stdev 26.151303 -system.ruby.LD.latency_hist_seqr | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 70 16.87% 92.53% | 20 4.82% 97.35% | 11 2.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 21.354217 +system.ruby.LD.latency_hist_seqr::gmean 4.945859 +system.ruby.LD.latency_hist_seqr::stdev 28.670834 +system.ruby.LD.latency_hist_seqr | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 69 16.63% 92.29% | 18 4.34% 96.63% | 14 3.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 415 system.ruby.LD.hit_latency_hist_seqr::bucket_size 2 system.ruby.LD.hit_latency_hist_seqr::max_bucket 19 @@ -533,18 +543,18 @@ system.ruby.LD.hit_latency_hist_seqr::total 269 system.ruby.LD.miss_latency_hist_seqr::bucket_size 16 system.ruby.LD.miss_latency_hist_seqr::max_bucket 159 system.ruby.LD.miss_latency_hist_seqr::samples 146 -system.ruby.LD.miss_latency_hist_seqr::mean 52.116438 -system.ruby.LD.miss_latency_hist_seqr::gmean 48.763829 -system.ruby.LD.miss_latency_hist_seqr::stdev 17.717519 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 56.390411 +system.ruby.LD.miss_latency_hist_seqr::gmean 52.068669 +system.ruby.LD.miss_latency_hist_seqr::stdev 20.461022 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 69 47.26% 78.08% | 18 12.33% 90.41% | 14 9.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 146 -system.ruby.ST.latency_hist_seqr::bucket_size 32 -system.ruby.ST.latency_hist_seqr::max_bucket 319 +system.ruby.ST.latency_hist_seqr::bucket_size 8 +system.ruby.ST.latency_hist_seqr::max_bucket 79 system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 10.064626 -system.ruby.ST.latency_hist_seqr::gmean 2.035894 -system.ruby.ST.latency_hist_seqr::stdev 25.936505 -system.ruby.ST.latency_hist_seqr | 262 89.12% 89.12% | 22 7.48% 96.60% | 9 3.06% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% +system.ruby.ST.latency_hist_seqr::mean 9.778912 +system.ruby.ST.latency_hist_seqr::gmean 2.043604 +system.ruby.ST.latency_hist_seqr::stdev 20.538869 +system.ruby.ST.latency_hist_seqr | 236 80.27% 80.27% | 11 3.74% 84.01% | 0 0.00% 84.01% | 15 5.10% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 22 7.48% 96.60% | 5 1.70% 98.30% | 5 1.70% 100.00% system.ruby.ST.latency_hist_seqr::total 294 system.ruby.ST.hit_latency_hist_seqr::bucket_size 2 system.ruby.ST.hit_latency_hist_seqr::max_bucket 19 @@ -554,21 +564,21 @@ system.ruby.ST.hit_latency_hist_seqr::gmean 1.112699 system.ruby.ST.hit_latency_hist_seqr::stdev 2.066980 system.ruby.ST.hit_latency_hist_seqr | 236 95.55% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 11 4.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 247 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 8 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 79 system.ruby.ST.miss_latency_hist_seqr::samples 47 -system.ruby.ST.miss_latency_hist_seqr::mean 55.361702 -system.ruby.ST.miss_latency_hist_seqr::gmean 48.711518 -system.ruby.ST.miss_latency_hist_seqr::stdev 42.031265 -system.ruby.ST.miss_latency_hist_seqr | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 53.574468 +system.ruby.ST.miss_latency_hist_seqr::gmean 49.876949 +system.ruby.ST.miss_latency_hist_seqr::stdev 18.206240 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 5 10.64% 89.36% | 5 10.64% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 47 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 7.135397 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.515500 -system.ruby.IFETCH.latency_hist_seqr::stdev 20.744191 -system.ruby.IFETCH.latency_hist_seqr | 2536 98.10% 98.10% | 46 1.78% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.04% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 7.746615 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.529553 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.548460 +system.ruby.IFETCH.latency_hist_seqr | 2337 90.41% 90.41% | 199 7.70% 98.10% | 43 1.66% 99.77% | 2 0.08% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 4 0.15% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 2585 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 @@ -578,13 +588,13 @@ system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.022830 system.ruby.IFETCH.hit_latency_hist_seqr::stdev 0.965875 system.ruby.IFETCH.hit_latency_hist_seqr | 2315 99.06% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 22 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist_seqr::total 2337 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 system.ruby.IFETCH.miss_latency_hist_seqr::samples 248 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.064516 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.606137 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.893804 -system.ruby.IFETCH.miss_latency_hist_seqr | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.435484 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.827440 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 30.751253 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 199 80.24% 80.24% | 43 17.34% 97.58% | 2 0.81% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 4 1.61% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 248 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 @@ -600,13 +610,13 @@ system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 11 system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 11.000000 system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 69 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 32 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 319 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 441 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.181406 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 55.608631 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.659343 -system.ruby.Directory.miss_mach_latency_hist_seqr | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 63.988662 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 60.139666 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 27.525151 +system.ruby.Directory.miss_mach_latency_hist_seqr | 57 12.93% 12.93% | 293 66.44% 79.37% | 85 19.27% 98.64% | 2 0.45% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 4 0.91% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 441 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -651,10 +661,10 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 36 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 146 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.116438 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 48.763829 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 17.717519 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.390411 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.068669 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 20.461022 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 69 47.26% 78.08% | 18 12.33% 90.41% | 14 9.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 146 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 @@ -670,13 +680,13 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 11 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 8 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 79 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 47 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.361702 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.711518 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 42.031265 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.574468 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 49.876949 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 18.206240 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 5 10.64% 89.36% | 5 10.64% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 47 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 @@ -692,13 +702,13 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 22 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 22 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 248 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.064516 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.606137 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.893804 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.435484 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 67.827440 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 30.751253 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 199 80.24% 80.24% | 43 17.34% 97.58% | 2 0.81% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 4 1.61% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 248 system.ruby.Directory_Controller.GETX 51 0.00% 0.00% system.ruby.Directory_Controller.GETS 410 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 538bb6cd3..7199cc5b0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=12 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir @@ -256,6 +278,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -329,11 +355,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -415,17 +446,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -438,18 +474,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -616,32 +657,206 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null router_id=0 virt_nets=5 @@ -754,8 +969,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null router_id=1 virt_nets=5 @@ -868,8 +1089,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null router_id=2 virt_nets=5 @@ -1016,9 +1243,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr index 1c18978fa..63982fce4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr @@ -4,9 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index 98025cd1e..d4c6f5ba8 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:26 -gem5 executing on zizzer, pid 34072 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:46 +gem5 executing on e108600-lin, pid 28078 +command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 41659 because target called exit() +Exiting @ tick 43520 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index f97a14626..535942f10 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000042 # Number of seconds simulated -sim_ticks 41659 # Number of ticks simulated -final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000044 # Number of seconds simulated +sim_ticks 43520 # Number of ticks simulated +final_tick 43520 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 54027 # Simulator instruction rate (inst/s) -host_op_rate 54016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 873053 # Simulator tick rate (ticks/s) -host_mem_usage 453224 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 93431 # Simulator instruction rate (inst/s) +host_op_rate 93392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1576605 # Simulator tick rate (ticks/s) +host_mem_usage 411000 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 40064 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 40064 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39808 # Number of bytes written to this memory @@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 626 # system.mem_ctrls.num_reads::total 626 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 622 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 622 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 961712955 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 961712955 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 955567824 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 955567824 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1917280780 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1917280780 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 920588235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 920588235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 914705882 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 914705882 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1835294118 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1835294118 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 626 # Number of read requests accepted system.mem_ctrls.writeReqs 622 # Number of write requests accepted system.mem_ctrls.readBursts 626 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 622 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24960 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 15104 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 24000 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 24512 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 15552 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 23424 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 40064 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 39808 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 236 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 219 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 243 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 231 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 23 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 24 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 58 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 62 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 15 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 32 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 53 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 53 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 68 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 5 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 14 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 30 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 68 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 22 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 32 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 54 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 57 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 65 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 21 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 48 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 5 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 23 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 15 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 63 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 65 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 41626 # Total gap between requests +system.mem_ctrls.totGap 43487 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 622 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 390 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 383 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,24 +136,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 18 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 25 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 27 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 27 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 25 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 25 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 17 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 26 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 28 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 24 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 22 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -185,89 +185,98 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 105 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 455.923810 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 317.170384 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 344.729986 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 11 10.48% 10.48% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 29 27.62% 38.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 10 9.52% 47.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 10 9.52% 57.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 14 13.33% 70.48% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5 4.76% 75.24% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 4 3.81% 79.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 4.76% 83.81% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 17 16.19% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 105 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.434783 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.058223 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 4.388270 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 3 13.04% 13.04% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 10 43.48% 56.52% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 5 21.74% 78.26% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 17.39% 95.65% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 4.35% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 23 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.304348 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.283756 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.875670 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 20 86.96% 86.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 4.35% 91.30% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 8.70% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 23 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 4371 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 11781 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1950 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11.21 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 113 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 404.389381 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 273.588270 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 327.373952 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20 17.70% 17.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 26 23.01% 40.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 16 14.16% 54.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 15 13.27% 68.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 5 4.42% 72.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 5.31% 77.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 7.08% 84.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 4.42% 89.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 12 10.62% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 113 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.662586 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 4.253850 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 8 36.36% 36.36% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 8 36.36% 72.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 5 22.73% 95.45% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 4.55% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 22 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.636364 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.596436 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.216766 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 17 77.27% 77.27% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1 4.55% 81.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 4 18.18% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 22 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 6435 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 13712 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 1915 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 16.80 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 30.21 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 599.15 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 576.11 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 961.71 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 955.57 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 35.80 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 563.24 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 538.24 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 920.59 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 914.71 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 9.18 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.68 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.50 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.61 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.40 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.20 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.82 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 298 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 355 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 76.41 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 88.09 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.35 # Average gap between requests -system.mem_ctrls.pageHitRate 82.35 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 234360 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 130200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1971840 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1555200 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 26028252 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 682200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 33144852 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 845.747691 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 1011 # Time in different power states +system.mem_ctrls.avgWrQLen 24.70 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 286 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 342 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 74.67 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 87.47 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 34.85 # Average gap between requests +system.mem_ctrls.pageHitRate 81.14 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 264180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 127512 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1850688 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1236096 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 3917040 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 69120 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 15256848 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 496128 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 26290812 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 604.108732 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 34684 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 40 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 36893 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 536760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 298200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2608320 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 2166912 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 26345628 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 403800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 34902420 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 890.595050 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 832 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 1292 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7430 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 33458 # Time in different power states +system.mem_ctrls_1.actEnergy 599760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 309120 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2524704 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 1820736 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 5746968 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 231168 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 13781232 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 35712 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 28122600 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 646.199449 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 29649 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 448 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 37357 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 93 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 11457 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 30222 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -302,8 +311,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 41659 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 41659 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 43520 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 43520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -322,7 +331,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 41659 # Number of busy cycles +system.cpu.num_busy_cycles 43520 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -362,7 +371,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 1248 # delay histogram for all message @@ -378,10 +387,10 @@ system.ruby.outstanding_req_hist_seqr::total 3295 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 11.646934 -system.ruby.latency_hist_seqr::gmean 2.114776 -system.ruby.latency_hist_seqr::stdev 26.263922 -system.ruby.latency_hist_seqr | 3185 96.69% 96.69% | 90 2.73% 99.42% | 14 0.43% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 12.211900 +system.ruby.latency_hist_seqr::gmean 2.131468 +system.ruby.latency_hist_seqr::stdev 27.594720 +system.ruby.latency_hist_seqr | 2924 88.77% 88.77% | 353 10.72% 99.48% | 12 0.36% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 3294 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -393,21 +402,21 @@ system.ruby.hit_latency_hist_seqr::total 2668 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 626 -system.ruby.miss_latency_hist_seqr::mean 57.023962 -system.ruby.miss_latency_hist_seqr::gmean 51.467697 -system.ruby.miss_latency_hist_seqr::stdev 32.986607 -system.ruby.miss_latency_hist_seqr | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 59.996805 +system.ruby.miss_latency_hist_seqr::gmean 53.641558 +system.ruby.miss_latency_hist_seqr::stdev 34.472574 +system.ruby.miss_latency_hist_seqr | 256 40.89% 40.89% | 353 56.39% 97.28% | 12 1.92% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 626 system.ruby.Directory.incomplete_times_seqr 625 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.489378 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.169118 system.ruby.network.routers0.msg_count.Control::2 626 system.ruby.network.routers0.msg_count.Data::2 622 system.ruby.network.routers0.msg_count.Response_Data::4 626 @@ -416,8 +425,8 @@ system.ruby.network.routers0.msg_bytes.Control::2 5008 system.ruby.network.routers0.msg_bytes.Data::2 44784 system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.489378 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.169118 system.ruby.network.routers1.msg_count.Control::2 626 system.ruby.network.routers1.msg_count.Data::2 622 system.ruby.network.routers1.msg_count.Response_Data::4 626 @@ -426,8 +435,8 @@ system.ruby.network.routers1.msg_bytes.Control::2 5008 system.ruby.network.routers1.msg_bytes.Data::2 44784 system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.489378 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.169118 system.ruby.network.routers2.msg_count.Control::2 626 system.ruby.network.routers2.msg_count.Data::2 622 system.ruby.network.routers2.msg_count.Response_Data::4 626 @@ -436,7 +445,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 5008 system.ruby.network.routers2.msg_bytes.Data::2 44784 system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 1878 system.ruby.network.msg_count.Data 1866 system.ruby.network.msg_count.Response_Data 1878 @@ -445,33 +454,33 @@ system.ruby.network.msg_byte.Control 15024 system.ruby.network.msg_byte.Data 134352 system.ruby.network.msg_byte.Response_Data 135216 system.ruby.network.msg_byte.Writeback_Control 14928 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.508582 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.187500 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers0.throttle1.link_utilization 7.470175 +system.ruby.network.routers0.throttle1.link_utilization 7.150735 system.ruby.network.routers0.throttle1.msg_count.Control::2 626 system.ruby.network.routers0.throttle1.msg_count.Data::2 622 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle0.link_utilization 7.470175 +system.ruby.network.routers1.throttle0.link_utilization 7.150735 system.ruby.network.routers1.throttle0.msg_count.Control::2 626 system.ruby.network.routers1.throttle0.msg_count.Data::2 622 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle1.link_utilization 7.508582 +system.ruby.network.routers1.throttle1.link_utilization 7.187500 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle0.link_utilization 7.508582 +system.ruby.network.routers2.throttle0.link_utilization 7.187500 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle1.link_utilization 7.470175 +system.ruby.network.routers2.throttle1.link_utilization 7.150735 system.ruby.network.routers2.throttle1.msg_count.Control::2 626 system.ruby.network.routers2.throttle1.msg_count.Data::2 622 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008 @@ -486,13 +495,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 622 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 622 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 30.537349 -system.ruby.LD.latency_hist_seqr::gmean 9.686440 -system.ruby.LD.latency_hist_seqr::stdev 30.265140 -system.ruby.LD.latency_hist_seqr | 170 40.96% 40.96% | 203 48.92% 89.88% | 35 8.43% 98.31% | 3 0.72% 99.04% | 3 0.72% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 33.354217 +system.ruby.LD.latency_hist_seqr::gmean 9.992707 +system.ruby.LD.latency_hist_seqr::stdev 38.395820 +system.ruby.LD.latency_hist_seqr | 297 71.57% 71.57% | 114 27.47% 99.04% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 415 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -501,21 +510,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 170 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 245 -system.ruby.LD.miss_latency_hist_seqr::mean 51.032653 -system.ruby.LD.miss_latency_hist_seqr::gmean 46.821080 -system.ruby.LD.miss_latency_hist_seqr::stdev 22.902478 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 55.804082 +system.ruby.LD.miss_latency_hist_seqr::gmean 49.356103 +system.ruby.LD.miss_latency_hist_seqr::stdev 35.580698 +system.ruby.LD.miss_latency_hist_seqr | 127 51.84% 51.84% | 114 46.53% 98.37% | 2 0.82% 99.18% | 0 0.00% 99.18% | 0 0.00% 99.18% | 2 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 245 -system.ruby.ST.latency_hist_seqr::bucket_size 64 -system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::bucket_size 32 +system.ruby.ST.latency_hist_seqr::max_bucket 319 system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 16.663265 -system.ruby.ST.latency_hist_seqr::gmean 3.036238 -system.ruby.ST.latency_hist_seqr::stdev 32.952425 -system.ruby.ST.latency_hist_seqr | 283 96.26% 96.26% | 6 2.04% 98.30% | 4 1.36% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 16.173469 +system.ruby.ST.latency_hist_seqr::gmean 3.033104 +system.ruby.ST.latency_hist_seqr::stdev 28.208400 +system.ruby.ST.latency_hist_seqr | 210 71.43% 71.43% | 44 14.97% 86.39% | 36 12.24% 98.64% | 1 0.34% 98.98% | 2 0.68% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 294 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -524,21 +533,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 210 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 system.ruby.ST.miss_latency_hist_seqr::samples 84 -system.ruby.ST.miss_latency_hist_seqr::mean 55.821429 -system.ruby.ST.miss_latency_hist_seqr::gmean 48.772534 -system.ruby.ST.miss_latency_hist_seqr::stdev 40.751129 -system.ruby.ST.miss_latency_hist_seqr | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 54.107143 +system.ruby.ST.miss_latency_hist_seqr::gmean 48.596564 +system.ruby.ST.miss_latency_hist_seqr::stdev 27.751487 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 44 52.38% 52.38% | 36 42.86% 95.24% | 1 1.19% 96.43% | 2 2.38% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 84 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 8.043714 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.589638 -system.ruby.IFETCH.latency_hist_seqr::stdev 23.152025 -system.ruby.IFETCH.latency_hist_seqr | 2529 97.83% 97.83% | 46 1.78% 99.61% | 6 0.23% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 8.367118 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.597827 +system.ruby.IFETCH.latency_hist_seqr::stdev 23.571466 +system.ruby.IFETCH.latency_hist_seqr | 2373 91.80% 91.80% | 202 7.81% 99.61% | 7 0.27% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 2585 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -550,18 +559,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 2288 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 297 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 62.306397 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 56.498895 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.624977 -system.ruby.IFETCH.miss_latency_hist_seqr | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.121212 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 59.083052 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.625488 +system.ruby.IFETCH.miss_latency_hist_seqr | 85 28.62% 28.62% | 202 68.01% 96.63% | 7 2.36% 98.99% | 0 0.00% 98.99% | 2 0.67% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 297 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 626 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.023962 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 51.467697 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.986607 -system.ruby.Directory.miss_mach_latency_hist_seqr | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.996805 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 53.641558 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.472574 +system.ruby.Directory.miss_mach_latency_hist_seqr | 256 40.89% 40.89% | 353 56.39% 97.28% | 12 1.92% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 626 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -589,29 +598,29 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 245 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 51.032653 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.821080 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 22.902478 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 55.804082 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.356103 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.580698 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 127 51.84% 51.84% | 114 46.53% 98.37% | 2 0.82% 99.18% | 0 0.00% 99.18% | 0 0.00% 99.18% | 2 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 245 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 84 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.821429 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.772534 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 40.751129 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 54.107143 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.596564 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 27.751487 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 44 52.38% 52.38% | 36 42.86% 95.24% | 1 1.19% 96.43% | 2 2.38% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 84 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 297 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 62.306397 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 56.498895 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.624977 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.121212 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 59.083052 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.625488 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 85 28.62% 28.62% | 202 68.01% 96.63% | 7 2.36% 98.99% | 0 0.00% 98.99% | 2 0.67% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 297 system.ruby.Directory_Controller.GETX 626 0.00% 0.00% system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% |