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-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini82
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr1
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt31
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini18
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr2
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt13
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr1
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt15
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini60
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr1
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt15
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini60
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr1
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt15
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini55
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr1
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt15
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini52
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr1
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt15
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini31
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr1
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt31
32 files changed, 443 insertions, 145 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index b9dbe7d51..15208c06e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -64,6 +68,8 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -128,6 +134,7 @@ BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
+eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
@@ -143,6 +150,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -151,6 +159,7 @@ mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
+sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
@@ -165,26 +174,32 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
+sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
+eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
@@ -193,16 +208,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=2
+eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
+eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
@@ -211,22 +229,26 @@ opLat=20
type=FUDesc
children=opList0 opList1 opList2
count=4
+eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
@@ -235,22 +257,26 @@ opLat=2
type=FUDesc
children=opList0 opList1 opList2
count=2
+eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
+eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
+eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
@@ -259,10 +285,12 @@ opLat=24
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
@@ -271,124 +299,145 @@ opLat=1
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
+eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
@@ -397,10 +446,12 @@ opLat=1
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -409,16 +460,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=4
+eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -427,10 +481,12 @@ opLat=1
type=FUDesc
children=opList
count=1
+eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
+eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
@@ -441,6 +497,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -449,6 +506,7 @@ mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
+sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
@@ -463,17 +521,23 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
+sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu.isa]
type=AlphaISA
+eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu.l2cache]
@@ -482,6 +546,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -490,6 +555,7 @@ mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
+sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
@@ -504,12 +570,15 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=20
+sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -519,6 +588,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -528,7 +598,8 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -542,11 +613,13 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+eventq_index=0
voltage_domain=system.voltage_domain
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -566,6 +639,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+eventq_index=0
in_addr_map=true
mem_sched_policy=frfcfs
null=false
@@ -577,17 +651,21 @@ static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCL=13750
+tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
+tRRD=6250
tWTR=7500
tXAW=40000
write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
index 27f858d8f..62976a831 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index 4cf5ca9ef..da1484dec 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:20
+gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 11933500 because target called exit()
+Exiting @ tick 11990500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 5e19e4b84..baea5f5eb 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds 0.000012 # Nu
sim_ticks 11990500 # Number of ticks simulated
final_tick 11990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 47015 # Simulator instruction rate (inst/s)
-host_op_rate 46988 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 235942636 # Simulator tick rate (ticks/s)
-host_mem_usage 225832 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 21306 # Simulator instruction rate (inst/s)
+host_op_rate 21301 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 106974940 # Simulator tick rate (ticks/s)
+host_mem_usage 229436 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
system.physmem.bytes_read::total 17472 # Number of bytes read from this memory
@@ -211,6 +213,7 @@ system.membus.reqLayer0.occupancy 344000 # La
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 2551500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 21.3 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 1176 # Number of BP lookups
system.cpu.branchPred.condPredicted 619 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect
@@ -541,6 +544,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
system.cpu.icache.tags.occ_blocks::cpu.inst 93.236237 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.045526 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.045526 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.091797 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 2318 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 2318 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 815 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 815 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 815 # number of demand (read+write) hits
@@ -627,6 +636,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 28.688277
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002851 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.003727 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 249 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007599 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 2457 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 2457 # Number of data accesses
system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses
@@ -744,6 +759,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy
system.cpu.dcache.tags.occ_blocks::cpu.data 45.667407 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.011149 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.011149 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1989 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1989 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index b66459c3a..aca9f495e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
@@ -74,20 +79,26 @@ icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu.isa]
type=AlphaISA
+eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -97,7 +108,8 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -111,11 +123,13 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+eventq_index=0
voltage_domain=system.voltage_domain
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -128,6 +142,7 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
@@ -137,5 +152,6 @@ port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
index bcbfa5445..32998f270 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,2 @@
-warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
index 034bc5823..33ba2e738 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:27
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:20
+gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index aec79b975..04acc5c7e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,13 +4,15 @@ sim_seconds 0.000001 # Nu
sim_ticks 1297500 # Number of ticks simulated
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 388869 # Simulator instruction rate (inst/s)
-host_op_rate 388153 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 195100518 # Simulator tick rate (ticks/s)
-host_mem_usage 215488 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 31206 # Simulator instruction rate (inst/s)
+host_op_rate 31196 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15701703 # Simulator tick rate (ticks/s)
+host_mem_usage 219708 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory
system.physmem.bytes_read::total 13356 # Number of bytes read from this memory
@@ -36,6 +38,7 @@ system.physmem.bw_total::total 11879768786 # To
system.membus.throughput 11879768786 # Throughput (bytes/s)
system.membus.data_through_bus 15414 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
index f2dc4f3e0..8168c285c 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -88,6 +88,7 @@ eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
@@ -107,7 +108,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
index 492f3e68f..a30a2a95c 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
@@ -4,4 +4,3 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
index 5722711d2..f35dc8674 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 22 2013 05:27:02
-gem5 started Sep 22 2013 05:27:13
-gem5 executing on zizzer
-command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Jan 22 2014 16:37:52
+gem5 started Jan 22 2014 17:26:00
+gem5 executing on u200540-lin
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 52575 because target called exit()
+Exiting @ tick 52548 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
index 1d9a45506..96547c7d5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,13 +4,16 @@ sim_seconds 0.000053 # Nu
sim_ticks 52548 # Number of ticks simulated
final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 16682 # Simulator instruction rate (inst/s)
-host_op_rate 16680 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 340078 # Simulator tick rate (ticks/s)
-host_mem_usage 169540 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
+host_inst_rate 25744 # Simulator instruction rate (inst/s)
+host_op_rate 25740 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 524809 # Simulator tick rate (ticks/s)
+host_mem_usage 124924 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1 # Clock period in ticks
+system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 3612 # delay histogram for all message
@@ -100,6 +103,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 2176
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632
+system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.dir_cntrl0.memBuffer.memReq 650 # Total number of memory requests
system.ruby.dir_cntrl0.memBuffer.memRead 547 # Number of memory reads
system.ruby.dir_cntrl0.memBuffer.memWrite 103 # Number of memory writes
@@ -148,6 +152,7 @@ system.ruby.network.msg_byte.Response_Data 263952
system.ruby.network.msg_byte.Response_Control 41760
system.ruby.network.msg_byte.Writeback_Data 23112
system.ruby.network.msg_byte.Writeback_Control 1896
+system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 1cc47929f..647bb1e23 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.cpu.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu.isa]
type=AlphaISA
+eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -95,7 +107,8 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -111,6 +124,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=30
latency_var=0
@@ -119,18 +133,22 @@ range=0:134217727
[system.ruby]
type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
mem_size=268435456
no_mem_vec=false
+num_of_sequencers=1
random_seed=1234
randomization=false
-stats_filename=ruby.stats
[system.ruby.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.ruby.dir_cntrl0]
@@ -138,9 +156,10 @@ type=Directory_Controller
children=directory memBuffer
buffer_size=0
clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
directory=system.ruby.dir_cntrl0.directory
directory_latency=6
+eventq_index=0
memBuffer=system.ruby.dir_cntrl0.memBuffer
number_of_TBEs=256
peer=Null
@@ -151,6 +170,7 @@ version=0
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
+eventq_index=0
map_levels=4
numa_high_bit=5
size=268435456
@@ -167,6 +187,7 @@ basic_bus_busy_time=2
clk_domain=system.ruby.memctrl_clk_domain
dimm_bit_0=12
dimms_per_channel=2
+eventq_index=0
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
@@ -186,7 +207,8 @@ L1Dcache=system.ruby.l1_cntrl0.L1Dcache
L1Icache=system.ruby.l1_cntrl0.L1Icache
buffer_size=0
clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
l2_select_num_bits=0
number_of_TBEs=256
peer=Null
@@ -204,6 +226,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
@@ -218,6 +241,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=true
latency=3
replacement_policy=PSEUDO_LRU
@@ -233,6 +257,7 @@ access_phys_mem=false
clk_domain=system.ruby.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
+eventq_index=0
icache=system.ruby.l1_cntrl0.L1Icache
max_outstanding_requests=16
ruby_system=system.ruby
@@ -250,7 +275,8 @@ children=L2cache
L2cache=system.ruby.l2_cntrl0.L2cache
buffer_size=0
clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
number_of_TBEs=256
peer=Null
recycle_latency=10
@@ -265,6 +291,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=false
latency=15
replacement_policy=PSEUDO_LRU
@@ -278,6 +305,7 @@ tagArrayBanks=1
type=DerivedClockDomain
clk_divider=3
clk_domain=system.ruby.clk_domain
+eventq_index=0
[system.ruby.network]
type=SimpleNetwork
@@ -287,6 +315,7 @@ buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
endpoint_bandwidth=1000
+eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
number_of_virtual_networks=10
@@ -297,6 +326,7 @@ topology=Crossbar
[system.ruby.network.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.l1_cntrl0
int_node=system.ruby.network.routers0
latency=1
@@ -306,6 +336,7 @@ weight=1
[system.ruby.network.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.l2_cntrl0
int_node=system.ruby.network.routers1
latency=1
@@ -315,6 +346,7 @@ weight=1
[system.ruby.network.ext_links2]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.dir_cntrl0
int_node=system.ruby.network.routers2
latency=1
@@ -324,6 +356,7 @@ weight=1
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=3
node_a=system.ruby.network.routers0
@@ -333,6 +366,7 @@ weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=4
node_a=system.ruby.network.routers1
@@ -342,6 +376,7 @@ weight=1
[system.ruby.network.int_links2]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=5
node_a=system.ruby.network.routers2
@@ -351,38 +386,36 @@ weight=1
[system.ruby.network.routers0]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=0
virt_nets=10
[system.ruby.network.routers1]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=1
virt_nets=10
[system.ruby.network.routers2]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=2
virt_nets=10
[system.ruby.network.routers3]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=3
virt_nets=10
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
clk_domain=system.clk_domain
+eventq_index=0
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
@@ -394,5 +427,6 @@ slave=system.system_port
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
index 492f3e68f..a30a2a95c 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -4,4 +4,3 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index e2683dd74..c37233c6d 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 22 2013 05:36:12
-gem5 started Sep 22 2013 05:36:23
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:42:56
+gem5 started Jan 22 2014 17:26:33
+gem5 executing on u200540-lin
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 5ece97b1b..b3553454d 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,13 +4,16 @@ sim_seconds 0.000045 # Nu
sim_ticks 44968 # Number of ticks simulated
final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 16150 # Simulator instruction rate (inst/s)
-host_op_rate 16148 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 281738 # Simulator tick rate (ticks/s)
-host_mem_usage 171884 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 17948 # Simulator instruction rate (inst/s)
+host_op_rate 17946 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 313128 # Simulator tick rate (ticks/s)
+host_mem_usage 128348 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1 # Clock period in ticks
+system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
system.ruby.outstanding_req_hist::samples 3295
@@ -82,6 +85,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 6512
system.ruby.network.routers1.msg_bytes.Writeback_Control::2 2648
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 7464
+system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.dir_cntrl0.memBuffer.memReq 499 # Total number of memory requests
system.ruby.dir_cntrl0.memBuffer.memRead 423 # Number of memory reads
system.ruby.dir_cntrl0.memBuffer.memWrite 76 # Number of memory writes
@@ -139,6 +143,7 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 18792
system.ruby.network.msg_byte.Writeback_Data 124848
system.ruby.network.msg_byte.Writeback_Control 51576
system.ruby.network.msg_byte.Unblock_Control 22384
+system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 57448e3a7..2bf0001da 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.cpu.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu.isa]
type=AlphaISA
+eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -95,7 +107,8 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -111,6 +124,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=30
latency_var=0
@@ -119,18 +133,22 @@ range=0:134217727
[system.ruby]
type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
mem_size=268435456
no_mem_vec=false
+num_of_sequencers=1
random_seed=1234
randomization=false
-stats_filename=ruby.stats
[system.ruby.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.ruby.dir_cntrl0]
@@ -138,10 +156,11 @@ type=Directory_Controller
children=directory memBuffer
buffer_size=0
clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
directory=system.ruby.dir_cntrl0.directory
directory_latency=5
distributed_persistent=true
+eventq_index=0
fixed_timeout_latency=100
l2_select_num_bits=0
memBuffer=system.ruby.dir_cntrl0.memBuffer
@@ -155,6 +174,7 @@ version=0
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
+eventq_index=0
map_levels=4
numa_high_bit=5
size=268435456
@@ -171,6 +191,7 @@ basic_bus_busy_time=2
clk_domain=system.ruby.memctrl_clk_domain
dimm_bit_0=12
dimms_per_channel=2
+eventq_index=0
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
@@ -191,8 +212,9 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
N_tokens=2
buffer_size=0
clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
dynamic_timeout_enabled=true
+eventq_index=0
fixed_timeout_latency=300
l1_request_latency=2
l1_response_latency=2
@@ -215,6 +237,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
@@ -229,6 +252,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
@@ -244,6 +268,7 @@ access_phys_mem=false
clk_domain=system.ruby.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
+eventq_index=0
icache=system.ruby.l1_cntrl0.L1Icache
max_outstanding_requests=16
ruby_system=system.ruby
@@ -262,7 +287,8 @@ L2cache=system.ruby.l2_cntrl0.L2cache
N_tokens=2
buffer_size=0
clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
filtering_enabled=true
l2_request_latency=5
l2_response_latency=5
@@ -278,6 +304,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
@@ -291,6 +318,7 @@ tagArrayBanks=1
type=DerivedClockDomain
clk_divider=3
clk_domain=system.ruby.clk_domain
+eventq_index=0
[system.ruby.network]
type=SimpleNetwork
@@ -300,6 +328,7 @@ buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
endpoint_bandwidth=1000
+eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
number_of_virtual_networks=10
@@ -310,6 +339,7 @@ topology=Crossbar
[system.ruby.network.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.l1_cntrl0
int_node=system.ruby.network.routers0
latency=1
@@ -319,6 +349,7 @@ weight=1
[system.ruby.network.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.l2_cntrl0
int_node=system.ruby.network.routers1
latency=1
@@ -328,6 +359,7 @@ weight=1
[system.ruby.network.ext_links2]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.dir_cntrl0
int_node=system.ruby.network.routers2
latency=1
@@ -337,6 +369,7 @@ weight=1
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=3
node_a=system.ruby.network.routers0
@@ -346,6 +379,7 @@ weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=4
node_a=system.ruby.network.routers1
@@ -355,6 +389,7 @@ weight=1
[system.ruby.network.int_links2]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=5
node_a=system.ruby.network.routers2
@@ -364,38 +399,36 @@ weight=1
[system.ruby.network.routers0]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=0
virt_nets=10
[system.ruby.network.routers1]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=1
virt_nets=10
[system.ruby.network.routers2]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=2
virt_nets=10
[system.ruby.network.routers3]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=3
virt_nets=10
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
clk_domain=system.clk_domain
+eventq_index=0
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
@@ -407,5 +440,6 @@ slave=system.system_port
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
index 492f3e68f..a30a2a95c 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -4,4 +4,3 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 76c77f4a5..b3289a2c7 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 22 2013 05:44:48
-gem5 started Sep 22 2013 05:45:00
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:47:59
+gem5 started Jan 22 2014 17:27:30
+gem5 executing on u200540-lin
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 17ea98764..0c82e32e7 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,13 +4,16 @@ sim_seconds 0.000043 # Nu
sim_ticks 43073 # Number of ticks simulated
final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 7100 # Simulator instruction rate (inst/s)
-host_op_rate 7100 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 118667 # Simulator tick rate (ticks/s)
-host_mem_usage 169652 # Number of bytes of host memory used
-host_seconds 0.36 # Real time elapsed on the host
+host_inst_rate 26553 # Simulator instruction rate (inst/s)
+host_op_rate 26550 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 443703 # Simulator tick rate (ticks/s)
+host_mem_usage 126100 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1 # Clock period in ticks
+system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
system.ruby.outstanding_req_hist::samples 3295
@@ -76,6 +79,7 @@ system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 5040
system.ruby.network.routers1.msg_bytes.Response_Control::4 8
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920
+system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.dir_cntrl0.memBuffer.memReq 532 # Total number of memory requests
system.ruby.dir_cntrl0.memBuffer.memRead 448 # Number of memory reads
system.ruby.dir_cntrl0.memBuffer.memWrite 84 # Number of memory writes
@@ -125,6 +129,7 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 15120
system.ruby.network.msg_byte.Response_Control 24
system.ruby.network.msg_byte.Writeback_Data 126576
system.ruby.network.msg_byte.Writeback_Control 8760
+system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index fed15fed0..1829ec00a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.cpu.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu.isa]
type=AlphaISA
+eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -95,7 +107,8 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -111,6 +124,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=30
latency_var=0
@@ -119,18 +133,22 @@ range=0:134217727
[system.ruby]
type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
mem_size=268435456
no_mem_vec=false
+num_of_sequencers=1
random_seed=1234
randomization=false
-stats_filename=ruby.stats
[system.ruby.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.ruby.dir_cntrl0]
@@ -138,8 +156,9 @@ type=Directory_Controller
children=directory memBuffer probeFilter
buffer_size=0
clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
directory=system.ruby.dir_cntrl0.directory
+eventq_index=0
full_bit_dir_enabled=false
memBuffer=system.ruby.dir_cntrl0.memBuffer
memory_controller_latency=2
@@ -154,6 +173,7 @@ version=0
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
+eventq_index=0
map_levels=4
numa_high_bit=5
size=268435456
@@ -170,6 +190,7 @@ basic_bus_busy_time=2
clk_domain=system.ruby.memctrl_clk_domain
dimm_bit_0=12
dimms_per_channel=2
+eventq_index=0
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
@@ -187,6 +208,7 @@ type=RubyCache
assoc=4
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=false
latency=1
replacement_policy=PSEUDO_LRU
@@ -205,7 +227,8 @@ L2cache=system.ruby.l1_cntrl0.L2cache
buffer_size=0
cache_response_latency=10
clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
issue_latency=2
l2_cache_hit_latency=10
no_mig_atomic=true
@@ -223,6 +246,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=false
latency=2
replacement_policy=PSEUDO_LRU
@@ -237,6 +261,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=true
latency=2
replacement_policy=PSEUDO_LRU
@@ -251,6 +276,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=false
latency=10
replacement_policy=PSEUDO_LRU
@@ -266,6 +292,7 @@ access_phys_mem=false
clk_domain=system.ruby.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
+eventq_index=0
icache=system.ruby.l1_cntrl0.L1Icache
max_outstanding_requests=16
ruby_system=system.ruby
@@ -281,6 +308,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
type=DerivedClockDomain
clk_divider=3
clk_domain=system.ruby.clk_domain
+eventq_index=0
[system.ruby.network]
type=SimpleNetwork
@@ -290,6 +318,7 @@ buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
endpoint_bandwidth=1000
+eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
number_of_virtual_networks=10
@@ -300,6 +329,7 @@ topology=Crossbar
[system.ruby.network.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.l1_cntrl0
int_node=system.ruby.network.routers0
latency=1
@@ -309,6 +339,7 @@ weight=1
[system.ruby.network.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.dir_cntrl0
int_node=system.ruby.network.routers1
latency=1
@@ -318,6 +349,7 @@ weight=1
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=2
node_a=system.ruby.network.routers0
@@ -327,6 +359,7 @@ weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=3
node_a=system.ruby.network.routers1
@@ -336,32 +369,29 @@ weight=1
[system.ruby.network.routers0]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=0
virt_nets=10
[system.ruby.network.routers1]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=1
virt_nets=10
[system.ruby.network.routers2]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=2
virt_nets=10
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
clk_domain=system.clk_domain
+eventq_index=0
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
@@ -373,5 +403,6 @@ slave=system.system_port
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
index 492f3e68f..a30a2a95c 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
@@ -4,4 +4,3 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index fa7b05ab3..74d6c0f17 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 22 2013 05:17:28
-gem5 started Sep 22 2013 05:17:49
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:32:54
+gem5 started Jan 22 2014 17:25:27
+gem5 executing on u200540-lin
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index fc4b80ac1..fe7ac0efa 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,13 +4,16 @@ sim_seconds 0.000035 # Nu
sim_ticks 35432 # Number of ticks simulated
final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 20063 # Simulator instruction rate (inst/s)
-host_op_rate 20060 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 275767 # Simulator tick rate (ticks/s)
-host_mem_usage 169584 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 28350 # Simulator instruction rate (inst/s)
+host_op_rate 28346 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 389675 # Simulator tick rate (ticks/s)
+host_mem_usage 126044 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1 # Clock period in ticks
+system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
system.ruby.outstanding_req_hist::samples 3295
@@ -43,6 +46,7 @@ system.ruby.miss_latency_hist::stdev 8.819211
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 421 95.46% 95.46% | 2 0.45% 95.92% | 12 2.72% 98.64% | 0 0.00% 98.64% | 6 1.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist::total 441
system.ruby.Directory.incomplete_times 440
+system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
@@ -123,6 +127,7 @@ system.ruby.network.msg_byte.Response_Data 95256
system.ruby.network.msg_byte.Writeback_Data 17496
system.ruby.network.msg_byte.Writeback_Control 28656
system.ruby.network.msg_byte.Unblock_Control 10560
+system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 56f1e35ca..360da34a5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.cpu.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu.isa]
type=AlphaISA
+eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -95,7 +107,8 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -111,6 +124,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=30
latency_var=0
@@ -119,18 +133,22 @@ range=0:134217727
[system.ruby]
type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
mem_size=268435456
no_mem_vec=false
+num_of_sequencers=1
random_seed=1234
randomization=false
-stats_filename=ruby.stats
[system.ruby.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.ruby.dir_cntrl0]
@@ -138,9 +156,10 @@ type=Directory_Controller
children=directory memBuffer
buffer_size=0
clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
directory=system.ruby.dir_cntrl0.directory
directory_latency=12
+eventq_index=0
memBuffer=system.ruby.dir_cntrl0.memBuffer
number_of_TBEs=256
peer=Null
@@ -151,6 +170,7 @@ version=0
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
+eventq_index=0
map_levels=4
numa_high_bit=5
size=268435456
@@ -167,6 +187,7 @@ basic_bus_busy_time=2
clk_domain=system.ruby.memctrl_clk_domain
dimm_bit_0=12
dimms_per_channel=2
+eventq_index=0
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
@@ -186,7 +207,8 @@ buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12
clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
issue_latency=2
number_of_TBEs=256
peer=Null
@@ -202,6 +224,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
@@ -217,6 +240,7 @@ access_phys_mem=false
clk_domain=system.ruby.clk_domain
dcache=system.ruby.l1_cntrl0.cacheMemory
deadlock_threshold=500000
+eventq_index=0
icache=system.ruby.l1_cntrl0.cacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
@@ -232,6 +256,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
type=DerivedClockDomain
clk_divider=3
clk_domain=system.ruby.clk_domain
+eventq_index=0
[system.ruby.network]
type=SimpleNetwork
@@ -241,6 +266,7 @@ buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
endpoint_bandwidth=1000
+eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
number_of_virtual_networks=10
@@ -251,6 +277,7 @@ topology=Crossbar
[system.ruby.network.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.l1_cntrl0
int_node=system.ruby.network.routers0
latency=1
@@ -260,6 +287,7 @@ weight=1
[system.ruby.network.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.dir_cntrl0
int_node=system.ruby.network.routers1
latency=1
@@ -269,6 +297,7 @@ weight=1
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=2
node_a=system.ruby.network.routers0
@@ -278,6 +307,7 @@ weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=3
node_a=system.ruby.network.routers1
@@ -287,32 +317,29 @@ weight=1
[system.ruby.network.routers0]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=0
virt_nets=10
[system.ruby.network.routers1]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=1
virt_nets=10
[system.ruby.network.routers2]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=2
virt_nets=10
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
clk_domain=system.clk_domain
+eventq_index=0
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
@@ -324,5 +351,6 @@ slave=system.system_port
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
index 492f3e68f..a30a2a95c 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
@@ -4,4 +4,3 @@ warn: rounding error > tolerance
0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 980ebae91..11cc12ff4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:38
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:30
+gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index a74ef311a..845b4481e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -4,13 +4,16 @@ sim_seconds 0.000052 # Nu
sim_ticks 52498 # Number of ticks simulated
final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 27660 # Simulator instruction rate (inst/s)
-host_op_rate 27654 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 563232 # Simulator tick rate (ticks/s)
-host_mem_usage 168112 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 24935 # Simulator instruction rate (inst/s)
+host_op_rate 24932 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 507835 # Simulator tick rate (ticks/s)
+host_mem_usage 124536 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1 # Clock period in ticks
+system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 1248 # delay histogram for all message
@@ -47,6 +50,7 @@ system.ruby.miss_latency_hist::stdev 6.377524
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 142 22.68% 22.68% | 448 71.57% 94.25% | 36 5.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist::total 626
system.ruby.Directory.incomplete_times 625
+system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses
@@ -98,6 +102,7 @@ system.ruby.network.msg_byte.Control 15024
system.ruby.network.msg_byte.Data 134352
system.ruby.network.msg_byte.Response_Data 135216
system.ruby.network.msg_byte.Writeback_Control 14928
+system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 81f228137..7ab4d5c2a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
+sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
+sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu.icache]
@@ -106,6 +116,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -114,6 +125,7 @@ mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
+sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
+sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu.isa]
type=AlphaISA
+eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu.l2cache]
@@ -147,6 +165,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -155,6 +174,7 @@ mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
+sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=20
+sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -193,7 +217,8 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -207,11 +232,13 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+eventq_index=0
voltage_domain=system.voltage_domain
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -224,6 +251,7 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
@@ -233,5 +261,6 @@ port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
index 31ae36f2e..32998f270 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
index f5b60c70f..cd7b05e76 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:38
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:26
+gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 0eefef01d..3fc7cd393 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds 0.000017 # Nu
sim_ticks 16524000 # Number of ticks simulated
final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 70 # Simulator instruction rate (inst/s)
-host_op_rate 70 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 446596 # Simulator tick rate (ticks/s)
-host_mem_usage 222964 # Number of bytes of host memory used
-host_seconds 37.00 # Real time elapsed on the host
+host_inst_rate 33204 # Simulator instruction rate (inst/s)
+host_op_rate 33192 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 212757424 # Simulator tick rate (ticks/s)
+host_mem_usage 228444 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory
system.physmem.bytes_read::total 15680 # Number of bytes read from this memory
@@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 245000 # La
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 13.3 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -106,6 +109,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 5335 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
@@ -186,6 +195,12 @@ system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses
system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
@@ -303,6 +318,12 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy
system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits