diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha')
3 files changed, 1578 insertions, 1104 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 062194e2a..ecf052997 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21628500 # Number of ticks simulated -final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 19841500 # Number of ticks simulated +final_tick 19841500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34038 # Simulator instruction rate (inst/s) -host_op_rate 34033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115179622 # Simulator tick rate (ticks/s) -host_mem_usage 212112 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 31060 # Simulator instruction rate (inst/s) +host_op_rate 31057 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96425663 # Simulator tick rate (ticks/s) +host_mem_usage 216044 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::total 30016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 29952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19200 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 890676653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 497121853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1387798507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 890676653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 890676653 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 890676653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 497121853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1387798507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 468 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 967668775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 541894514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1509563289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 967668775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 967668775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 967668775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 541894514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1509563289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 469 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 29952 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 69 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 66 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 19827000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 469 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1719468 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11463468 # Sum of mem lat for all requests +system.physmem.totBusLat 1876000 # Total cycles spent in databus access +system.physmem.totBankLat 7868000 # Total cycles spent in bank access +system.physmem.avgQLat 3666.24 # Average queueing delay per request +system.physmem.avgBankLat 16776.12 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24442.36 # Average memory access latency +system.physmem.avgRdBW 1509.56 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1509.56 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.43 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 401 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42275.05 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +218,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 43258 # number of cpu cycles simulated +system.cpu.numCycles 39684 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1606 # Number of BP lookups @@ -90,12 +248,12 @@ system.cpu.execution_unit.executions 4463 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11913 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 526 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35855 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7403 # Number of cycles cpu stages are processed. -system.cpu.activity 17.113597 # Percentage of cycles cpu is active +system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32282 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7402 # Number of cycles cpu stages are processed. +system.cpu.activity 18.652354 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -107,72 +265,72 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 6.769640 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.210329 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.769640 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147718 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.210329 # CPI: Total CPI of All Threads +system.cpu.ipc 0.161022 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147718 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 38346 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.161022 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34772 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.355125 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 39380 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 12.377784 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35806 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.964816 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 39087 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.642147 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41918 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 9.772200 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 35512 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4172 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 10.513053 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 38344 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.097693 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38800 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.376676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35226 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.305608 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 11.233747 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.677886 # Cycle average of tags in use -system.cpu.icache.total_refs 557 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 142.150123 # Cycle average of tags in use +system.cpu.icache.total_refs 558 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.677886 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 557 # number of overall hits -system.cpu.icache.overall_hits::total 557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses -system.cpu.icache.overall_misses::total 351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19444500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19444500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19444500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19444500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19444500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19444500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 142.150123 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069409 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069409 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits +system.cpu.icache.overall_hits::total 558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17305000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17305000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17305000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17305000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17305000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17305000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386564 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.386564 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55397.435897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55397.435897 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49442.857143 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49442.857143 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49442.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49442.857143 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,46 +339,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 49 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 49 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 49 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 49 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16495000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16495000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16495000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16495000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16495000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16495000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14791500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14791500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14791500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14791500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14791500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14791500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54619.205298 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54619.205298 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48978.476821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48978.476821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.512660 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 104.047429 # Cycle average of tags in use system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.512660 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025028 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025028 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 104.047429 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025402 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits @@ -237,14 +395,14 @@ system.cpu.dcache.demand_misses::cpu.data 348 # n system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses system.cpu.dcache.overall_misses::total 348 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5810500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5810500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13883000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13883000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19693500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19693500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19693500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19693500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11296500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11296500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16650500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16650500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16650500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16650500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -261,20 +419,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.169922 system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59902.061856 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59902.061856 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55310.756972 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55310.756972 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55195.876289 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55195.876289 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45005.976096 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45005.976096 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47846.264368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47846.264368 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2586 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 91.351351 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 69.891892 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits @@ -293,14 +451,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9608500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9608500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9608500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9608500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3447000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8525500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8525500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8525500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8525500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -309,26 +467,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58021.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58021.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53457.894737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53457.894737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47219.178082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47219.178082 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 194.915514 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.193487 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.751655 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.163860 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001714 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005948 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.245680 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.947807 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006079 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -346,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16176500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5410500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21587000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4019000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4019000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16176500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9429500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25606000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16176500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9429500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25606000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14473000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19450000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3369500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3369500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8346500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22819500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14473000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8346500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22819500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -379,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53742.524917 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56952.631579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54512.626263 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55054.794521 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55054.794521 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54597.014925 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54597.014925 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48083.056478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52389.473684 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49116.161616 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46157.534247 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46157.534247 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 48655.650320 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 48655.650320 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12511500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4259000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16770500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3141000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3141000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12511500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19911500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12511500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19911500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10688499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3791620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14480119 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2447596 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2447596 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10688499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6239216 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16927715 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10688499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6239216 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16927715 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -431,17 +589,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41566.445183 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44831.578947 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42349.747475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43027.397260 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43027.397260 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35509.963455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39911.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36565.957071 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33528.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33528.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 1c9a49b18..d5736f11f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,210 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12394500 # Number of ticks simulated -final_tick 12394500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11568000 # Number of ticks simulated +final_tick 11568000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52290 # Simulator instruction rate (inst/s) -host_op_rate 52282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101684511 # Simulator tick rate (ticks/s) -host_mem_usage 219660 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 27765 # Simulator instruction rate (inst/s) +host_op_rate 27764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50400871 # Simulator tick rate (ticks/s) +host_mem_usage 217072 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11328 # Number of bytes read from this memory -system.physmem.bytes_read::total 31296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 177 # Number of read requests responded to by this memory -system.physmem.num_reads::total 489 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1611037154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 913953770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2524990923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1611037154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1611037154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1611037154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 913953770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2524990923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory +system.physmem.bytes_read::total 31104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory +system.physmem.num_reads::total 486 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1731673582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 957123098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2688796680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1731673582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1731673582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1731673582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 957123098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2688796680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 486 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 31104 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 11441000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 486 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3089486 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12593486 # Sum of mem lat for all requests +system.physmem.totBusLat 1944000 # Total cycles spent in databus access +system.physmem.totBankLat 7560000 # Total cycles spent in bank access +system.physmem.avgQLat 6356.97 # Average queueing delay per request +system.physmem.avgBankLat 15555.56 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25912.52 # Average memory access latency +system.physmem.avgRdBW 2688.80 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2688.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 16.80 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.09 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 416 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 23541.15 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1990 # DTB read hits -system.cpu.dtb.read_misses 56 # DTB read misses +system.cpu.dtb.read_hits 1960 # DTB read hits +system.cpu.dtb.read_misses 58 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2046 # DTB read accesses -system.cpu.dtb.write_hits 1084 # DTB write hits -system.cpu.dtb.write_misses 30 # DTB write misses +system.cpu.dtb.read_accesses 2018 # DTB read accesses +system.cpu.dtb.write_hits 1076 # DTB write hits +system.cpu.dtb.write_misses 32 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1114 # DTB write accesses -system.cpu.dtb.data_hits 3074 # DTB hits -system.cpu.dtb.data_misses 86 # DTB misses +system.cpu.dtb.write_accesses 1108 # DTB write accesses +system.cpu.dtb.data_hits 3036 # DTB hits +system.cpu.dtb.data_misses 90 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3160 # DTB accesses -system.cpu.itb.fetch_hits 2336 # ITB hits +system.cpu.dtb.data_accesses 3126 # DTB accesses +system.cpu.itb.fetch_hits 2261 # ITB hits system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2374 # ITB accesses +system.cpu.itb.fetch_accesses 2299 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,244 +218,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24790 # number of cpu cycles simulated +system.cpu.numCycles 23137 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2873 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 545 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2164 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits +system.cpu.BPredUnit.lookups 2774 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1638 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 514 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2124 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 769 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8141 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16442 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1200 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1838 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 885 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 405 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7948 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15915 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2774 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1174 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2854 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1765 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 730 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 739 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2336 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175940 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.562615 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2261 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.177755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.562670 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11043 78.98% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 296 2.12% 81.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 231 1.65% 82.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 234 1.67% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 276 1.97% 86.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 200 1.43% 87.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 274 1.96% 89.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 190 1.36% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1238 8.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10659 78.88% 78.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 293 2.17% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 218 1.61% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 238 1.76% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 276 2.04% 86.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 191 1.41% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 258 1.91% 89.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.30% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1205 8.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115894 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.663251 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9096 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 904 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2739 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1171 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 257 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 89 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15180 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1171 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9315 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 364 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2589 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 284 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14415 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 250 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10802 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18056 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18039 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119895 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.687859 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8886 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 751 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2667 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1129 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 236 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 88 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14776 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1129 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9097 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 177 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2538 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 227 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14039 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10509 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17564 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17547 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6232 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 728 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2652 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 5939 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 34 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 671 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2611 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1355 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12813 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10578 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6130 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13982 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.756544 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.394074 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10392 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3411 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.769037 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.410550 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9591 68.60% 68.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1568 11.21% 79.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1143 8.17% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 728 5.21% 93.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 479 3.43% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 273 1.95% 98.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 154 1.10% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33 0.24% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9295 68.79% 68.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1391 10.29% 79.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1141 8.44% 87.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 752 5.57% 93.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 3.45% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 269 1.99% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 153 1.13% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 32 0.24% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13513 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 8.70% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 56.52% 65.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 40 34.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 9.57% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 56.52% 66.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 33.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7162 67.71% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2248 21.25% 89.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1163 10.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7044 67.78% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2192 21.09% 88.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1151 11.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10578 # Type of FU issued -system.cpu.iq.rate 0.426704 # Inst issue rate +system.cpu.iq.FU_type_0::total 10392 # Type of FU issued +system.cpu.iq.rate 0.449151 # Inst issue rate system.cpu.iq.fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010872 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35279 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18978 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9581 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.011066 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34450 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18472 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9469 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10680 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10494 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1469 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 490 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1171 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12931 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2652 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1129 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2611 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1355 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 151 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 403 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 554 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9992 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2057 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 586 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 142 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 377 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9865 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2029 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 527 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88 # number of nop insts executed -system.cpu.iew.exec_refs 3174 # number of memory reference insts executed -system.cpu.iew.exec_branches 1621 # Number of branches executed -system.cpu.iew.exec_stores 1117 # Number of stores executed -system.cpu.iew.exec_rate 0.403066 # Inst execution rate -system.cpu.iew.wb_sent 9749 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9591 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5054 # num instructions producing a value -system.cpu.iew.wb_consumers 6863 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 3139 # number of memory reference insts executed +system.cpu.iew.exec_branches 1600 # Number of branches executed +system.cpu.iew.exec_stores 1110 # Number of stores executed +system.cpu.iew.exec_rate 0.426373 # Inst execution rate +system.cpu.iew.wb_sent 9638 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9479 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5022 # num instructions producing a value +system.cpu.iew.wb_consumers 6814 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.386890 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736413 # average fanout of values written-back +system.cpu.iew.wb_rate 0.409690 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737012 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6541 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6282 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12811 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.498712 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314684 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 432 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12384 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.515908 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.366435 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10031 78.30% 78.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1473 11.50% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 525 4.10% 93.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 241 1.88% 95.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.28% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 92 0.72% 97.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 108 0.84% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 98.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 140 1.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9732 78.59% 78.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1344 10.85% 89.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 509 4.11% 93.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 223 1.80% 95.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 188 1.52% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 75 0.61% 97.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 105 0.85% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 63 0.51% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 145 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12811 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12384 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -308,70 +466,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 140 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25250 # The number of ROB reads -system.cpu.rob.rob_writes 27045 # The number of ROB writes -system.cpu.timesIdled 255 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10808 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24559 # The number of ROB reads +system.cpu.rob.rob_writes 26483 # The number of ROB writes +system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9624 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 3.890458 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.890458 # CPI: Total CPI of All Threads -system.cpu.ipc 0.257039 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.257039 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12699 # number of integer regfile reads -system.cpu.int_regfile_writes 7211 # number of integer regfile writes +system.cpu.cpi 3.631042 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.631042 # CPI: Total CPI of All Threads +system.cpu.ipc 0.275403 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.275403 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12554 # number of integer regfile reads +system.cpu.int_regfile_writes 7112 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 158.537993 # Cycle average of tags in use -system.cpu.icache.total_refs 1881 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.009585 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 160.502909 # Cycle average of tags in use +system.cpu.icache.total_refs 1827 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.818471 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 158.537993 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077411 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077411 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1881 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1881 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1881 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1881 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1881 # number of overall hits -system.cpu.icache.overall_hits::total 1881 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses -system.cpu.icache.overall_misses::total 455 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15830500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15830500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15830500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15830500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15830500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15830500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2336 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2336 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2336 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2336 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194777 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194777 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194777 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194777 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194777 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194777 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34792.307692 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34792.307692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34792.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34792.307692 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 160.502909 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078371 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078371 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1827 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1827 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1827 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1827 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1827 # number of overall hits +system.cpu.icache.overall_hits::total 1827 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 434 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2261 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2261 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2261 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191950 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.191950 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.191950 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.191950 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.191950 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.191950 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30921.658986 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30921.658986 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30921.658986 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11526000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11526000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11526000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11526000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133990 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.133990 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.133990 # 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number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 120 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10333000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10333000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10333000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10333000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10333000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10333000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138877 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138877 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138877 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32907.643312 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32907.643312 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32907.643312 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32907.643312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32907.643312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32907.643312 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.969871 # Cycle average of tags in use -system.cpu.dcache.total_refs 2254 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 177 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.734463 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.685258 # Cycle average of tags in use +system.cpu.dcache.total_refs 2236 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.924855 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.969871 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026360 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026360 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1748 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1748 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2254 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2254 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2254 # number of overall hits -system.cpu.dcache.overall_hits::total 2254 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 527 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 527 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 527 # number of overall misses -system.cpu.dcache.overall_misses::total 527 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6365000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6365000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12897000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12897000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19262000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19262000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19262000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19262000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1916 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1916 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 107.685258 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026290 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026290 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1732 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1732 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 504 # 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number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2781 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2781 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2781 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2781 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087683 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087683 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.189500 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.189500 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.189500 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.189500 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37886.904762 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37886.904762 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35924.791086 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35924.791086 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36550.284630 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36550.284630 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2755 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2755 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2755 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2755 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083598 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083598 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.417341 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.188385 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188385 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188385 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188385 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38069.620253 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38069.620253 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26717.451524 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26717.451524 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.410405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30173.410405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.410405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30173.410405 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,119 +634,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 177 # 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average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39513.698630 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40822.033898 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 40822.033898 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40822.033898 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 40822.033898 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 289 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 289 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 346 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8904460 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5808612 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14713072 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997959 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997959 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32733.974359 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37548.076923 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33937.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35301.369863 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35301.369863 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28448.753994 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38015.800000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30765.230024 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 27493.589041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27493.589041 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 7f4e477cc..d5e0f20d7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7079000 # Number of ticks simulated -final_tick 7079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 6408000 # Number of ticks simulated +final_tick 6408000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 8209 # Simulator instruction rate (inst/s) -host_op_rate 8209 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24342914 # Simulator tick rate (ticks/s) -host_mem_usage 218360 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 494 # Simulator instruction rate (inst/s) +host_op_rate 494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1327192 # Simulator tick rate (ticks/s) +host_mem_usage 215760 # Number of bytes of host memory used +host_seconds 4.83 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,34 +19,192 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1699675095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 768470123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2468145218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1699675095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1699675095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1699675095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 768470123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2468145218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1877652934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 848938826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2726591760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1877652934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1877652934 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1877652934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 848938826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2726591760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 273 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 17472 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 6357500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 273 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1341773 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7053773 # Sum of mem lat for all requests +system.physmem.totBusLat 1092000 # Total cycles spent in databus access +system.physmem.totBankLat 4620000 # Total cycles spent in bank access +system.physmem.avgQLat 4914.92 # Average queueing delay per request +system.physmem.avgBankLat 16923.08 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25838.00 # Average memory access latency +system.physmem.avgRdBW 2726.59 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2726.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 17.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.10 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 229 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.88 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 23287.55 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 712 # DTB read hits -system.cpu.dtb.read_misses 34 # DTB read misses +system.cpu.dtb.read_hits 718 # DTB read hits +system.cpu.dtb.read_misses 36 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 746 # DTB read accesses -system.cpu.dtb.write_hits 367 # DTB write hits -system.cpu.dtb.write_misses 20 # DTB write misses +system.cpu.dtb.read_accesses 754 # DTB read accesses +system.cpu.dtb.write_hits 382 # DTB write hits +system.cpu.dtb.write_misses 24 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 387 # DTB write accesses -system.cpu.dtb.data_hits 1079 # DTB hits -system.cpu.dtb.data_misses 54 # DTB misses +system.cpu.dtb.write_accesses 406 # DTB write accesses +system.cpu.dtb.data_hits 1100 # DTB hits +system.cpu.dtb.data_misses 60 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1133 # DTB accesses -system.cpu.itb.fetch_hits 1015 # ITB hits +system.cpu.dtb.data_accesses 1160 # DTB accesses +system.cpu.itb.fetch_hits 1042 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1045 # ITB accesses +system.cpu.itb.fetch_accesses 1072 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,244 +218,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 14159 # number of cpu cycles simulated +system.cpu.numCycles 12817 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1131 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 255 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 792 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits +system.cpu.BPredUnit.lookups 1162 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 576 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 259 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 820 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 228 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 213 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4177 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6936 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 432 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 862 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 243 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 224 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 4082 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7077 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1162 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 261 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 902 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1015 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7112 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.975253 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.397370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 857 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1042 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.004827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.418564 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5922 83.27% 83.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 52 0.73% 84.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 129 1.81% 85.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100 1.41% 87.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 139 1.95% 89.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63 0.89% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 67 0.94% 91.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 67 0.94% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 573 8.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5820 82.64% 82.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52 0.74% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 133 1.89% 85.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 101 1.43% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 157 2.23% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 70 0.99% 89.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 69 0.98% 90.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.91% 91.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 577 8.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7112 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.079879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.489865 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5180 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1148 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 503 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 169 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6175 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 503 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5278 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 59 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 172 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1058 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5909 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 15 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4299 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6685 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6673 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 7043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090661 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.552157 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5035 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 297 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1173 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 523 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 176 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 84 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6290 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 301 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 523 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5140 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 24 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 214 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1083 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 59 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 6004 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4336 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6797 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6785 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2531 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2568 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 136 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 172 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 984 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 506 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5173 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4054 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4204 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2615 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1486 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7112 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.570022 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.279366 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7043 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.596905 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.307061 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5467 76.87% 76.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 597 8.39% 85.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 392 5.51% 90.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 263 3.70% 94.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 194 2.73% 97.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 122 1.72% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 53 0.75% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12 0.17% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5344 75.88% 75.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 621 8.82% 84.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 394 5.59% 90.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 268 3.81% 94.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 205 2.91% 97.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 132 1.87% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 55 0.78% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11 0.16% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7112 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7043 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 4.65% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18 41.86% 46.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.26% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 46.81% 51.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 48.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2869 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 786 19.39% 90.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 398 9.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2977 70.81% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 808 19.22% 90.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 418 9.94% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4054 # Type of FU issued -system.cpu.iq.rate 0.286320 # Inst issue rate -system.cpu.iq.fu_busy_cnt 43 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010607 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7459 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3702 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4204 # Type of FU issued +system.cpu.iq.rate 0.328002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 47 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011180 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15542 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7792 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3821 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4090 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4244 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 569 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 182 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 212 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 503 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 46 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5379 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 523 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5532 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 984 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 506 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 154 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 211 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3894 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 747 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 160 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 221 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 4011 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 193 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 342 # number of nop insts executed -system.cpu.iew.exec_refs 1134 # number of memory reference insts executed -system.cpu.iew.exec_branches 652 # Number of branches executed -system.cpu.iew.exec_stores 387 # Number of stores executed -system.cpu.iew.exec_rate 0.275019 # Inst execution rate -system.cpu.iew.wb_sent 3793 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3708 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1740 # num instructions producing a value -system.cpu.iew.wb_consumers 2258 # num instructions consuming a value +system.cpu.iew.exec_nop 353 # number of nop insts executed +system.cpu.iew.exec_refs 1161 # number of memory reference insts executed +system.cpu.iew.exec_branches 678 # Number of branches executed +system.cpu.iew.exec_stores 406 # Number of stores executed +system.cpu.iew.exec_rate 0.312944 # Inst execution rate +system.cpu.iew.wb_sent 3922 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3827 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1795 # num instructions producing a value +system.cpu.iew.wb_consumers 2353 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.261883 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.770593 # average fanout of values written-back +system.cpu.iew.wb_rate 0.298588 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762856 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2798 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2928 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 175 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6609 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.389772 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.242894 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.395092 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.243251 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5727 86.65% 86.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 217 3.28% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 312 4.72% 94.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 115 1.74% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 67 1.01% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.80% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 34 0.51% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 19 0.29% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 65 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5631 86.37% 86.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 221 3.39% 89.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 313 4.80% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 120 1.84% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 64 0.98% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 55 0.84% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 34 0.52% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22 0.34% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 60 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6520 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -308,69 +466,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 65 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11671 # The number of ROB reads -system.cpu.rob.rob_writes 11260 # The number of ROB writes -system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7047 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11717 # The number of ROB reads +system.cpu.rob.rob_writes 11541 # The number of ROB writes +system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5774 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.931713 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.931713 # CPI: Total CPI of All Threads -system.cpu.ipc 0.168585 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.168585 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4712 # number of integer regfile reads -system.cpu.int_regfile_writes 2874 # number of integer regfile writes +system.cpu.cpi 5.369501 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.369501 # CPI: Total CPI of All Threads +system.cpu.ipc 0.186237 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.186237 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4858 # number of integer regfile reads +system.cpu.int_regfile_writes 2964 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 93.783034 # Cycle average of tags in use -system.cpu.icache.total_refs 767 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 92.000483 # Cycle average of tags in use +system.cpu.icache.total_refs 799 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.079787 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.250000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 93.783034 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045792 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045792 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 767 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 767 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 767 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 767 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 767 # number of overall hits -system.cpu.icache.overall_hits::total 767 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses -system.cpu.icache.overall_misses::total 248 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 9016000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 9016000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 9016000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 9016000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 9016000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 9016000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1015 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1015 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1015 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1015 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1015 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1015 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244335 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.244335 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.244335 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.244335 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.244335 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.244335 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36354.838710 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36354.838710 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36354.838710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36354.838710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36354.838710 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 92.000483 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.044922 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.044922 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 799 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 799 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 799 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 799 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 799 # number of overall hits +system.cpu.icache.overall_hits::total 799 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 243 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 243 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 243 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 243 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 243 # number of overall misses +system.cpu.icache.overall_misses::total 243 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 7449000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 7449000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 7449000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 7449000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 7449000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 7449000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1042 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233205 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.233205 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.233205 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.233205 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.233205 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.233205 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30654.320988 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30654.320988 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30654.320988 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30654.320988 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30654.320988 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30654.320988 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,94 +537,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 55 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 55 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 55 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6948500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6948500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6948500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6948500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6948500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6948500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185222 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.185222 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185222 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.185222 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36960.106383 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36960.106383 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36960.106383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36960.106383 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5938000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5938000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5938000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5938000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5938000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5938000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.180422 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.180422 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.180422 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31585.106383 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31585.106383 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31585.106383 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 31585.106383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31585.106383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 31585.106383 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.970482 # Cycle average of tags in use -system.cpu.dcache.total_refs 773 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 44.834744 # Cycle average of tags in use +system.cpu.dcache.total_refs 777 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.094118 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.141176 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.970482 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011223 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011223 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 560 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 560 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 44.834744 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.010946 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.010946 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 564 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 564 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 773 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 773 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 773 # number of overall hits -system.cpu.dcache.overall_hits::total 773 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 777 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 777 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 777 # number of overall hits +system.cpu.dcache.overall_hits::total 777 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 120 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 120 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses -system.cpu.dcache.overall_misses::total 202 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4078500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4078500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3119500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3119500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7198000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7198000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7198000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7198000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 681 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 681 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 201 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 201 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 201 # number of overall misses +system.cpu.dcache.overall_misses::total 201 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3706500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3706500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2874500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2874500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6581000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6581000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6581000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6581000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 684 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 684 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 975 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 975 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 975 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 975 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.177680 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.177680 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 978 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 978 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 978 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 978 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.175439 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.175439 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.207179 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.207179 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.207179 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.207179 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33706.611570 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33706.611570 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38512.345679 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38512.345679 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35633.663366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35633.663366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35633.663366 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.205521 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.205521 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.205521 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.205521 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30887.500000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30887.500000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35487.654321 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35487.654321 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32741.293532 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32741.293532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32741.293532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32741.293532 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,14 +633,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 117 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 117 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 117 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 116 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 116 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 116 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -491,42 +649,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2530500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2530500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 981500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3512000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3512000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3512000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3512000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089574 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089574 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 953500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 953500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3370500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3370500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3370500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3370500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089181 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087179 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087179 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087179 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41483.606557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41483.606557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40895.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40895.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41317.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 41317.647059 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086912 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.086912 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086912 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.086912 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39622.950820 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39622.950820 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39652.941176 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 39652.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39652.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 39652.941176 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 122.770960 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 120.198004 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.868144 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.902816 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002865 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000882 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003747 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 92.103751 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.094254 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002811 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000857 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -538,17 +696,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6760000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2469500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9229500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 956000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 956000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3425500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10185500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6760000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3425500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10185500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 5749500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8105500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 928000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 928000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 5749500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3284000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9033500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 5749500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3284000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9033500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -571,17 +729,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35957.446809 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40483.606557 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 37066.265060 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39833.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39833.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40300 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37309.523810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35957.446809 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40300 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37309.523810 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 30582.446809 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38622.950820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 32552.208835 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 30582.446809 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38635.294118 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 33089.743590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 30582.446809 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38635.294118 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 33089.743590 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,17 +759,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6157500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2280500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8438000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 881500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 881500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6157500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3162000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9319500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6157500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3162000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9319500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5087760 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2153056 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7240816 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 847024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5087760 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3000080 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8087840 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5087760 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3000080 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8087840 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -623,17 +781,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32752.659574 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37385.245902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33887.550201 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36729.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36729.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32752.659574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37200 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34137.362637 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 27062.553191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29079.582329 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35292.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35292.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 27062.553191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35295.058824 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29625.787546 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 27062.553191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35295.058824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29625.787546 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |