diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/alpha')
6 files changed, 217 insertions, 181 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 1a6e00d22..e3deed2b6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37552000 # Number of ticks simulated -final_tick 37552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 37553000 # Number of ticks simulated +final_tick 37553000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72134 # Simulator instruction rate (inst/s) -host_op_rate 72118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 423067865 # Simulator tick rate (ticks/s) -host_mem_usage 288748 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 161315 # Simulator instruction rate (inst/s) +host_op_rate 161262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 945919395 # Simulator tick rate (ticks/s) +host_mem_usage 296228 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 620366425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 288027269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 908393694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 620366425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 620366425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 620366425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 288027269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 908393694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 620349905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 288019599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 908369504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 620349905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 620349905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 620349905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 288019599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 908369504 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37447500 # Total gap between requests +system.physmem.totGap 37448500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2665000 # To system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 908.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 908.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 908.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 908.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.10 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 437 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70257.97 # Average gap between requests +system.physmem.avgGap 70259.85 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ) @@ -293,24 +293,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 75104 # number of cpu cycles simulated +system.cpu.numCycles 75106 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.735000 # CPI: cycles per instruction -system.cpu.ipc 0.085215 # IPC: instructions per cycle +system.cpu.cpi 11.735312 # CPI: cycles per instruction +system.cpu.ipc 0.085213 # IPC: instructions per cycle system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62587 # Total number of cycles that the object has spent stopped +system.cpu.idleCycles 62589 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.919220 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.920661 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.919220 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 103.920661 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id @@ -417,14 +417,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.811080 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 175.815240 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2286 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.263014 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.811080 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085845 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.815240 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085847 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085847 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id @@ -443,12 +443,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27931500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27931500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27931500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27931500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27931500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27931500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27932500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27932500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27932500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27932500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27932500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27932500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2651 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2651 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2651 # number of demand (read+write) accesses @@ -461,12 +461,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.137684 system.cpu.icache.demand_miss_rate::total 0.137684 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.137684 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.137684 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76524.657534 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76524.657534 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76524.657534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76524.657534 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76527.397260 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76527.397260 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76527.397260 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76527.397260 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,33 +481,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27566500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27566500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27566500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27566500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27566500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27566500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27567500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27567500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27567500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27567500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27567500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27567500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137684 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.137684 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.137684 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75524.657534 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75524.657534 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75527.397260 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75527.397260 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.447652 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.452540 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.824515 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.828674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623866 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005366 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.007124 # Average percentage of cache occupancy @@ -640,6 +640,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 534 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -653,14 +659,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001873 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043274 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 533 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 85a8b430a..58b2620bf 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21900500 # Number of ticks simulated final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43231 # Simulator instruction rate (inst/s) -host_op_rate 43225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 148545474 # Simulator tick rate (ticks/s) -host_mem_usage 289772 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 94413 # Simulator instruction rate (inst/s) +host_op_rate 94393 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 324370159 # Simulator tick rate (ticks/s) +host_mem_usage 297000 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -698,12 +698,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 157.774053 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 157.774053 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id @@ -724,12 +724,12 @@ system.cpu.icache.demand_misses::cpu.inst 459 # n system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses system.cpu.icache.overall_misses::total 459 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32352500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32352500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32352500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32352500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32352500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32352500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses @@ -742,12 +742,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.220038 system.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70484.749455 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70484.749455 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70484.749455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70484.749455 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -768,24 +768,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 311 system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23859500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23859500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23859500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23859500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23859500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23859500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76718.649518 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76718.649518 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use @@ -927,6 +927,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution @@ -940,14 +946,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 2c1174c59..e7401ee31 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32544500 # Number of ticks simulated -final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32545500 # Number of ticks simulated +final_tick 32545500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 619666 # Simulator instruction rate (inst/s) -host_op_rate 618826 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3148046044 # Simulator tick rate (ticks/s) -host_mem_usage 291528 # Number of bytes of host memory used +host_inst_rate 507828 # Simulator instruction rate (inst/s) +host_op_rate 507304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2581337246 # Simulator tick rate (ticks/s) +host_mem_usage 294696 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 546680801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330368254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877049054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546680801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546680801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546680801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330368254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877049054 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 65089 # number of cpu cycles simulated +system.cpu.numCycles 65091 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 65089 # Number of busy cycles +system.cpu.num_busy_cycles 65091 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.755352 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.756988 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.755352 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 103.756988 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id @@ -226,14 +226,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.988451 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.992231 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.988451 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062494 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062494 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.992231 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id @@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15304500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15304500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15304500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15304500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15304500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15304500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54854.838710 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54854.838710 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54854.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54854.838710 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,36 +290,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15024500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15024500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15024500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15024500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15024500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15024500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15025500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15025500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53851.254480 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53851.254480 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53854.838710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53854.838710 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.465722 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.470347 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.994443 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.471279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.998222 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.472125 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005629 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id @@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -462,14 +468,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 2f7c0906a..a420f2b35 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20075000 # Number of ticks simulated final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42420 # Simulator instruction rate (inst/s) -host_op_rate 42407 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 329231154 # Simulator tick rate (ticks/s) -host_mem_usage 287436 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 131673 # Simulator instruction rate (inst/s) +host_op_rate 131586 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1021264689 # Simulator tick rate (ticks/s) +host_mem_usage 295944 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -634,6 +634,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 308 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -647,15 +653,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 6ee889334..c4983f8bd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 12363500 # Number of ticks simulated final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20992 # Simulator instruction rate (inst/s) -host_op_rate 20989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108692792 # Simulator tick rate (ticks/s) -host_mem_usage 288464 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 79745 # Simulator instruction rate (inst/s) +host_op_rate 79707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 412680664 # Simulator tick rate (ticks/s) +host_mem_usage 295680 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -919,6 +919,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution @@ -932,15 +938,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 7411927e4..6bacfac4e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000017 # Nu sim_ticks 16524500 # Number of ticks simulated final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 374183 # Simulator instruction rate (inst/s) -host_op_rate 373424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2390351512 # Simulator tick rate (ticks/s) -host_mem_usage 291260 # Number of bytes of host memory used +host_inst_rate 315037 # Simulator instruction rate (inst/s) +host_op_rate 314537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2013954906 # Simulator tick rate (ticks/s) +host_mem_usage 293376 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -443,6 +443,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -456,15 +462,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 245 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) |